diff --git a/Quartus/A1_Q5/db/prev_cmp_A1_Q5.qmsg b/Quartus/A1_Q5/db/prev_cmp_A1_Q5.qmsg index 8eedf84..3e8e78a 100644 --- a/Quartus/A1_Q5/db/prev_cmp_A1_Q5.qmsg +++ b/Quartus/A1_Q5/db/prev_cmp_A1_Q5.qmsg @@ -1,37 +1,137 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465036231 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465036232 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:37:16 2026 " "Processing started: Tue Sep 15 19:37:16 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465036232 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465036232 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465036232 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789465036549 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789465036550 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789465046004 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465046004 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789465046140 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789465046905 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789465047246 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789465047246 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789465047275 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789465047275 ""} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Implemented 32 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789465047275 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789465047275 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465047282 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:37:27 2026 " "Processing ended: Tue Sep 15 19:37:27 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465047282 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465047282 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465047282 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465047282 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1789465048807 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465048808 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:37:28 2026 " "Processing started: Tue Sep 15 19:37:28 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465048808 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1789465048808 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_fit --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1789465048808 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1789465048858 ""} -{ "Info" "0" "" "Project = A1_Q5" { } { } 0 0 "Project = A1_Q5" 0 0 "Fitter" 0 0 1789465048859 ""} -{ "Info" "0" "" "Revision = shifter" { } { } 0 0 "Revision = shifter" 0 0 "Fitter" 0 0 1789465048859 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789465049047 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789465049047 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789465049052 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465049129 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465049129 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789465049534 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789465049561 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789465049613 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 17 " "No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789465049868 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789465056595 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465056643 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789465056645 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465056646 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465056646 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789465056646 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789465056646 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789465056646 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789465056647 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789465056647 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789465056647 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465056666 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465117698 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465117698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:38:37 2026 " "Processing started: Tue Sep 15 19:38:37 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465117698 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465117698 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465117699 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789465118007 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789465118007 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789465126919 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465126919 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789465127060 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789465127834 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789465128194 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789465128194 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789465128236 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789465128236 ""} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Implemented 32 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789465128236 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789465128236 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:38:48 2026 " "Processing ended: Tue Sep 15 19:38:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465128243 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1789465129930 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465129930 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:38:49 2026 " "Processing started: Tue Sep 15 19:38:49 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465129930 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1789465129930 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_fit --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1789465129931 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1789465130003 ""} +{ "Info" "0" "" "Project = A1_Q5" { } { } 0 0 "Project = A1_Q5" 0 0 "Fitter" 0 0 1789465130005 ""} +{ "Info" "0" "" "Revision = shifter" { } { } 0 0 "Revision = shifter" 0 0 "Fitter" 0 0 1789465130005 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789465130214 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789465130214 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789465130221 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465130300 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465130300 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789465130803 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789465130840 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789465130902 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 17 " "No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789465131227 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789465138495 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465138551 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789465138553 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789465138555 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789465138555 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789465138555 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465138575 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789465145753 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789465145754 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789465145754 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789465145755 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789465145756 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789465145756 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789465145756 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789465145760 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789465145841 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465147357 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789465148341 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789465148587 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465148587 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789465149821 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789465158188 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789465158188 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789465158582 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789465158582 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789465158582 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465158584 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789465160095 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465160145 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465160585 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465160585 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465161535 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465164913 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789465165221 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1379 " "Peak virtual memory: 1379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:25 2026 " "Processing ended: Tue Sep 15 19:39:25 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:36 " "Elapsed time: 00:00:36" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:50 " "Total CPU time (on all processors): 00:00:50" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789465165869 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1789465167736 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465167737 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:27 2026 " "Processing started: Tue Sep 15 19:39:27 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465167737 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789465167737 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789465167737 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789465168580 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789465173536 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "507 " "Peak virtual memory: 507 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:33 2026 " "Processing ended: Tue Sep 15 19:39:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789465173727 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1789465174418 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1789465175261 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465175262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:34 2026 " "Processing started: Tue Sep 15 19:39:34 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465175262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465175262 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q5 -c shifter " "Command: quartus_sta A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465175262 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789465175322 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789465175845 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789465175845 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465175922 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465175922 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789465176538 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465176538 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465176539 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465176539 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465176539 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465176540 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789465176540 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789465176545 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465176545 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176547 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176550 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176551 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176552 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176553 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176553 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465176556 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465176606 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465178030 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178131 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178133 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178134 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178135 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178136 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178136 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465178138 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465178417 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465179197 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465179249 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179251 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179252 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179253 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179254 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179254 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465179256 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179415 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179416 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179417 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179418 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179418 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465180905 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465180906 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "777 " "Peak virtual memory: 777 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:40 2026 " "Processing ended: Tue Sep 15 19:39:40 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789465180932 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1789465182961 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465182961 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:42 2026 " "Processing started: Tue Sep 15 19:39:42 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465182961 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465182961 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465182961 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789465183869 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "shifter.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/ simulation " "Generated file shifter.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789465183961 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "666 " "Peak virtual memory: 666 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:44 2026 " "Processing ended: Tue Sep 15 19:39:44 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465184019 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 16 s " "Quartus Prime Full Compilation was successful. 0 errors, 16 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465184746 ""} diff --git a/Quartus/A1_Q5/db/shifter.asm.qmsg b/Quartus/A1_Q5/db/shifter.asm.qmsg index 36dd42e..c14f6cc 100644 --- a/Quartus/A1_Q5/db/shifter.asm.qmsg +++ b/Quartus/A1_Q5/db/shifter.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465167736 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465167737 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:27 2026 " "Processing started: Tue Sep 15 19:39:27 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465167737 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789465167737 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789465167737 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789465168580 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789465173536 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "507 " "Peak virtual memory: 507 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:33 2026 " "Processing ended: Tue Sep 15 19:39:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789465173727 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465765000 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465765000 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:49:24 2026 " "Processing started: Tue Sep 15 19:49:24 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465765000 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789465765000 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789465765000 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789465765662 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789465769958 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "518 " "Peak virtual memory: 518 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465770133 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:49:30 2026 " "Processing ended: Tue Sep 15 19:49:30 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465770133 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465770133 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465770133 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789465770133 ""} diff --git a/Quartus/A1_Q5/db/shifter.asm.rdb b/Quartus/A1_Q5/db/shifter.asm.rdb index e1c2f35..f0230c1 100644 Binary files a/Quartus/A1_Q5/db/shifter.asm.rdb and b/Quartus/A1_Q5/db/shifter.asm.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.cdb b/Quartus/A1_Q5/db/shifter.cmp.cdb index f410f43..f7daf84 100644 Binary files a/Quartus/A1_Q5/db/shifter.cmp.cdb and b/Quartus/A1_Q5/db/shifter.cmp.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.hdb b/Quartus/A1_Q5/db/shifter.cmp.hdb index 00c1666..c28a03c 100644 Binary files a/Quartus/A1_Q5/db/shifter.cmp.hdb and b/Quartus/A1_Q5/db/shifter.cmp.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.idb b/Quartus/A1_Q5/db/shifter.cmp.idb index 12a4086..94f0a16 100644 Binary files a/Quartus/A1_Q5/db/shifter.cmp.idb and b/Quartus/A1_Q5/db/shifter.cmp.idb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.logdb b/Quartus/A1_Q5/db/shifter.cmp.logdb index bc090df..4d7b3dd 100644 --- a/Quartus/A1_Q5/db/shifter.cmp.logdb +++ b/Quartus/A1_Q5/db/shifter.cmp.logdb @@ -29,9 +29,9 @@ IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, -IO_RULES_MATRIX,Total Pass,0;15;15;0;0;17;15;0;0;0;0;0;0;4;0;0;0;0;4;0;0;0;0;4;0;17;17;0, +IO_RULES_MATRIX,Total Pass,0;17;17;0;0;17;17;0;0;0;0;0;0;4;0;0;0;0;4;0;0;0;0;4;0;17;17;0, IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,17;2;2;17;17;0;2;17;17;17;17;17;17;13;17;17;17;17;13;17;17;17;17;13;17;0;0;17, +IO_RULES_MATRIX,Total Inapplicable,17;0;0;17;17;0;0;17;17;17;17;17;17;13;17;17;17;17;13;17;17;17;17;13;17;0;0;17, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, IO_RULES_MATRIX,OUT_1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,OUT_1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, @@ -43,8 +43,8 @@ IO_RULES_MATRIX,op[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass IO_RULES_MATRIX,op[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,C[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,C[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,B[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,B[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,A[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, diff --git a/Quartus/A1_Q5/db/shifter.cmp.rdb b/Quartus/A1_Q5/db/shifter.cmp.rdb index 010e7fe..d0fae2a 100644 Binary files a/Quartus/A1_Q5/db/shifter.cmp.rdb and b/Quartus/A1_Q5/db/shifter.cmp.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd index 5b25938..b19b6d1 100644 Binary files a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd and b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd index 0778662..118df22 100644 Binary files a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd and b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A1_Q5/db/shifter.eda.qmsg b/Quartus/A1_Q5/db/shifter.eda.qmsg index 08bfbd0..0cf3658 100644 --- a/Quartus/A1_Q5/db/shifter.eda.qmsg +++ b/Quartus/A1_Q5/db/shifter.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465182961 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465182961 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:42 2026 " "Processing started: Tue Sep 15 19:39:42 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465182961 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465182961 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465182961 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789465183869 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "shifter.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/ simulation " "Generated file shifter.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789465183961 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "666 " "Peak virtual memory: 666 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:44 2026 " "Processing ended: Tue Sep 15 19:39:44 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465184019 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465778550 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465778550 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:49:38 2026 " "Processing started: Tue Sep 15 19:49:38 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465778550 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465778550 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465778550 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789465779305 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "shifter.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/ simulation " "Generated file shifter.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789465779368 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "666 " "Peak virtual memory: 666 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465779415 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:49:39 2026 " "Processing ended: Tue Sep 15 19:49:39 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465779415 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465779415 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465779415 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465779415 ""} diff --git a/Quartus/A1_Q5/db/shifter.fit.qmsg b/Quartus/A1_Q5/db/shifter.fit.qmsg index 7754089..31f33b1 100644 --- a/Quartus/A1_Q5/db/shifter.fit.qmsg +++ b/Quartus/A1_Q5/db/shifter.fit.qmsg @@ -1,45 +1,44 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789465130214 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789465130214 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789465130221 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465130300 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465130300 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789465130803 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789465130840 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789465130902 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 17 " "No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789465131227 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789465138495 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465138551 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789465138553 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465138554 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465138554 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789465138554 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789465138554 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789465138554 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789465138555 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789465138555 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789465138555 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465138575 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789465145753 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789465145754 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789465145754 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789465145755 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789465145756 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789465145756 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789465145756 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789465145760 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789465145841 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465147357 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789465148341 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789465148587 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465148587 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789465149821 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789465158188 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789465158188 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789465158582 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789465158582 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789465158582 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465158584 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789465160095 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465160145 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465160585 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465160585 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465161535 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465164913 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789465165221 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1379 " "Peak virtual memory: 1379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:25 2026 " "Processing ended: Tue Sep 15 19:39:25 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:36 " "Elapsed time: 00:00:36" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:50 " "Total CPU time (on all processors): 00:00:50" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789465165869 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789465734967 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789465734967 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789465734972 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465735053 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465735053 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789465735458 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789465735488 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789465735543 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789465742376 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465742408 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789465742411 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465742411 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465742411 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789465742412 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789465742412 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789465742412 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789465742412 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789465742412 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789465742412 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465742432 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789465748280 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789465748281 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789465748281 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789465748282 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789465748283 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789465748284 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789465748284 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789465748287 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789465748364 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465749544 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789465750333 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789465750619 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465750619 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789465751545 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789465756981 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789465756981 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789465757285 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789465757285 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789465757285 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465757288 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789465758499 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465758536 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465758918 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465758918 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465759655 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465762493 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789465762775 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1382 " "Peak virtual memory: 1382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465763378 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:49:23 2026 " "Processing ended: Tue Sep 15 19:49:23 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465763378 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465763378 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:41 " "Total CPU time (on all processors): 00:00:41" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465763378 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789465763378 ""} diff --git a/Quartus/A1_Q5/db/shifter.hier_info b/Quartus/A1_Q5/db/shifter.hier_info index 2a52d65..2417933 100644 --- a/Quartus/A1_Q5/db/shifter.hier_info +++ b/Quartus/A1_Q5/db/shifter.hier_info @@ -63,9 +63,9 @@ C[0] => ShiftRight1.IN6 C[1] => ShiftLeft0.IN5 C[1] => ShiftRight0.IN5 C[1] => ShiftRight1.IN5 -OUT_1[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[0] << Mux3.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[1] << Mux2.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[2] << Mux1.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[3] << Mux0.DB_MAX_OUTPUT_PORT_TYPE diff --git a/Quartus/A1_Q5/db/shifter.map.cdb b/Quartus/A1_Q5/db/shifter.map.cdb index d026a47..e0917ce 100644 Binary files a/Quartus/A1_Q5/db/shifter.map.cdb and b/Quartus/A1_Q5/db/shifter.map.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.map.hdb b/Quartus/A1_Q5/db/shifter.map.hdb index 06823f2..4d4a3f5 100644 Binary files a/Quartus/A1_Q5/db/shifter.map.hdb and b/Quartus/A1_Q5/db/shifter.map.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.map.qmsg b/Quartus/A1_Q5/db/shifter.map.qmsg index 9da54d9..a6c45f0 100644 --- a/Quartus/A1_Q5/db/shifter.map.qmsg +++ b/Quartus/A1_Q5/db/shifter.map.qmsg @@ -1,11 +1,11 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465117698 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465117698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:38:37 2026 " "Processing started: Tue Sep 15 19:38:37 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465117698 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465117698 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465117699 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789465118007 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789465118007 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789465126919 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465126919 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789465127060 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789465127834 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789465128194 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789465128194 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789465128236 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789465128236 ""} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Implemented 32 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789465128236 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789465128236 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:38:48 2026 " "Processing ended: Tue Sep 15 19:38:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465128243 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465722532 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465722532 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:48:42 2026 " "Processing started: Tue Sep 15 19:48:42 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465722532 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465722532 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465722532 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789465722855 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789465722855 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789465731986 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465731986 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789465732120 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789465732859 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789465733205 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789465733205 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789465733235 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789465733235 ""} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Implemented 32 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789465733235 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789465733235 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465733241 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:48:53 2026 " "Processing ended: Tue Sep 15 19:48:53 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465733241 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465733241 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465733241 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465733241 ""} diff --git a/Quartus/A1_Q5/db/shifter.map.rdb b/Quartus/A1_Q5/db/shifter.map.rdb index f5cb174..f103500 100644 Binary files a/Quartus/A1_Q5/db/shifter.map.rdb and b/Quartus/A1_Q5/db/shifter.map.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.map_bb.cdb b/Quartus/A1_Q5/db/shifter.map_bb.cdb index e26dfbf..674c7bb 100644 Binary files a/Quartus/A1_Q5/db/shifter.map_bb.cdb and b/Quartus/A1_Q5/db/shifter.map_bb.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.map_bb.hdb b/Quartus/A1_Q5/db/shifter.map_bb.hdb index 9c83f7c..8779db9 100644 Binary files a/Quartus/A1_Q5/db/shifter.map_bb.hdb and b/Quartus/A1_Q5/db/shifter.map_bb.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.pre_map.hdb b/Quartus/A1_Q5/db/shifter.pre_map.hdb index 93e40dc..620ecf7 100644 Binary files a/Quartus/A1_Q5/db/shifter.pre_map.hdb and b/Quartus/A1_Q5/db/shifter.pre_map.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.routing.rdb b/Quartus/A1_Q5/db/shifter.routing.rdb index b5b070a..b007929 100644 Binary files a/Quartus/A1_Q5/db/shifter.routing.rdb and b/Quartus/A1_Q5/db/shifter.routing.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.rtlv.hdb b/Quartus/A1_Q5/db/shifter.rtlv.hdb index f0a202a..3dae875 100644 Binary files a/Quartus/A1_Q5/db/shifter.rtlv.hdb and b/Quartus/A1_Q5/db/shifter.rtlv.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb b/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb index 125fb57..7ba79cb 100644 Binary files a/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb and b/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.sta.qmsg b/Quartus/A1_Q5/db/shifter.sta.qmsg index cf8dbcf..5e089b8 100644 --- a/Quartus/A1_Q5/db/shifter.sta.qmsg +++ b/Quartus/A1_Q5/db/shifter.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465175261 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465175262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:34 2026 " "Processing started: Tue Sep 15 19:39:34 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465175262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465175262 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q5 -c shifter " "Command: quartus_sta A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465175262 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789465175322 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789465175845 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789465175845 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465175922 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465175922 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789465176538 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465176538 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465176539 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465176539 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465176539 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465176540 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789465176540 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789465176545 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465176545 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176547 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176550 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176551 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176552 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176553 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176553 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465176556 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465176606 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465178030 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178131 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178133 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178134 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178135 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178136 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178136 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465178138 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465178417 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465179197 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465179249 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179251 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179252 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179253 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179254 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179254 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465179256 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179415 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179416 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179417 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179418 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179418 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465180905 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465180906 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "777 " "Peak virtual memory: 777 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:40 2026 " "Processing ended: Tue Sep 15 19:39:40 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789465180932 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465771600 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465771601 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:49:31 2026 " "Processing started: Tue Sep 15 19:49:31 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465771601 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465771601 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q5 -c shifter " "Command: quartus_sta A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465771601 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789465771655 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789465772141 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789465772141 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465772218 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465772218 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789465772796 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465772797 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465772797 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465772798 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465772798 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465772798 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789465772799 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789465772805 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465772807 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465772809 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465772814 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465772815 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465772816 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465772817 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465772817 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465772819 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465772859 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465774184 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465774286 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465774286 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465774286 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465774287 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465774287 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465774289 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465774290 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465774291 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465774292 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465774293 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465774295 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465774565 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465775306 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465775352 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465775352 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465775352 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465775352 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775353 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775354 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775355 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775356 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775356 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465775358 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465775516 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465775516 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465775517 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465775517 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775518 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775519 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775520 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775521 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465775521 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465776935 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465776936 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "773 " "Peak virtual memory: 773 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465776958 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:49:36 2026 " "Processing ended: Tue Sep 15 19:49:36 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465776958 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465776958 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465776958 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789465776958 ""} diff --git a/Quartus/A1_Q5/db/shifter.sta.rdb b/Quartus/A1_Q5/db/shifter.sta.rdb index 3213de6..a706558 100644 Binary files a/Quartus/A1_Q5/db/shifter.sta.rdb and b/Quartus/A1_Q5/db/shifter.sta.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb index 75037be..b9c787c 100644 Binary files a/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb and b/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb index d870da6..2e95e9b 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb index 09dfe7d..66287ab 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb index ce4bfcd..9c733f5 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb index a407d67..e10ca28 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb index 471ce93..d26676e 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb index 59eb94c..1f55848 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tmw_info b/Quartus/A1_Q5/db/shifter.tmw_info index 3931c4b..96c3101 100644 --- a/Quartus/A1_Q5/db/shifter.tmw_info +++ b/Quartus/A1_Q5/db/shifter.tmw_info @@ -1,7 +1,7 @@ -start_full_compilation:s:00:01:08 +start_full_compilation:s:00:00:59 start_analysis_synthesis:s:00:00:12-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:38-start_full_compilation -start_assembler:s:00:00:08-start_full_compilation +start_fitter:s:00:00:31-start_full_compilation +start_assembler:s:00:00:06-start_full_compilation start_timing_analyzer:s:00:00:07-start_full_compilation start_eda_netlist_writer:s:00:00:03-start_full_compilation diff --git a/Quartus/A1_Q5/db/shifter.vpr.ammdb b/Quartus/A1_Q5/db/shifter.vpr.ammdb index ac5d8d5..2f89342 100644 Binary files a/Quartus/A1_Q5/db/shifter.vpr.ammdb and b/Quartus/A1_Q5/db/shifter.vpr.ammdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb index 1e0a846..7f44404 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb index 4325c99..560a174 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb index e5625c4..02ecd07 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb index d28b497..42a05b1 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb index 50072cb..47ef4a7 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb index 3e42912..8c2237c 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb index c965f78..d41be79 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb index 87d6272..466ee92 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb index f3c0da7..f58a186 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb index 1b48f45..1eed435 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb index db284db..58e5461 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb differ diff --git a/Quartus/A1_Q5/output_files/shifter.asm.rpt b/Quartus/A1_Q5/output_files/shifter.asm.rpt index c973bbb..31f1952 100644 --- a/Quartus/A1_Q5/output_files/shifter.asm.rpt +++ b/Quartus/A1_Q5/output_files/shifter.asm.rpt @@ -1,5 +1,5 @@ Assembler report for shifter -Tue Sep 15 19:39:33 2026 +Tue Sep 15 19:49:30 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Sep 15 19:39:33 2026 ; +; Assembler Status ; Successful - Tue Sep 15 19:49:30 2026 ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; ; Family ; Cyclone V ; @@ -67,8 +67,8 @@ on the Quartus Prime software download page. +----------------+----------------------+ ; Option ; Setting ; +----------------+----------------------+ -; JTAG usercode ; 0x007896D6 ; -; Checksum ; 0x007896D6 ; +; JTAG usercode ; 0x0078977F ; +; Checksum ; 0x0078977F ; +----------------+----------------------+ @@ -78,14 +78,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 19:39:27 2026 + Info: Processing started: Tue Sep 15 19:49:24 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 507 megabytes - Info: Processing ended: Tue Sep 15 19:39:33 2026 + Info: Peak virtual memory: 518 megabytes + Info: Processing ended: Tue Sep 15 19:49:30 2026 Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q5/output_files/shifter.done b/Quartus/A1_Q5/output_files/shifter.done index 879d0bb..1c4e9f0 100644 --- a/Quartus/A1_Q5/output_files/shifter.done +++ b/Quartus/A1_Q5/output_files/shifter.done @@ -1 +1 @@ -Tue Sep 15 19:39:44 2026 +Tue Sep 15 19:49:40 2026 diff --git a/Quartus/A1_Q5/output_files/shifter.eda.rpt b/Quartus/A1_Q5/output_files/shifter.eda.rpt index 9607ead..caf5c9e 100644 --- a/Quartus/A1_Q5/output_files/shifter.eda.rpt +++ b/Quartus/A1_Q5/output_files/shifter.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for shifter -Tue Sep 15 19:39:43 2026 +Tue Sep 15 19:49:39 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Sep 15 19:39:43 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Sep 15 19:49:39 2026 ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; ; Family ; Cyclone V ; @@ -81,14 +81,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 19:39:42 2026 + Info: Processing started: Tue Sep 15 19:49:38 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file shifter.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 666 megabytes - Info: Processing ended: Tue Sep 15 19:39:44 2026 - Info: Elapsed time: 00:00:02 + Info: Processing ended: Tue Sep 15 19:49:39 2026 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A1_Q5/output_files/shifter.fit.rpt b/Quartus/A1_Q5/output_files/shifter.fit.rpt index 602dd46..6b1c782 100644 --- a/Quartus/A1_Q5/output_files/shifter.fit.rpt +++ b/Quartus/A1_Q5/output_files/shifter.fit.rpt @@ -1,5 +1,5 @@ Fitter report for shifter -Tue Sep 15 19:39:25 2026 +Tue Sep 15 19:49:22 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -58,7 +58,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Sep 15 19:39:25 2026 ; +; Fitter Status ; Successful - Tue Sep 15 19:49:22 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; @@ -390,8 +390,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; A[3] ; Y16 ; 4A ; 46 ; 0 ; 17 ; 15 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; ; B[0] ; AD13 ; 4A ; 34 ; 0 ; 34 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; ; B[1] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; -; B[2] ; AF6 ; 3B ; 21 ; 0 ; 51 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; Fitter ; no ; -; B[3] ; AE6 ; 3B ; 21 ; 0 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; Fitter ; no ; +; B[2] ; W11 ; 3B ; 10 ; 0 ; 40 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; B[3] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; ; C[0] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 10 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; ; C[1] ; AE10 ; 4A ; 36 ; 0 ; 51 ; 10 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; ; op[0] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; @@ -494,7 +494,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 61 ; 3B ; B[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB13 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; @@ -568,7 +568,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; AE4 ; 23 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; AE5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AE6 ; 85 ; 3B ; B[3] ; input ; 1.2 V ; ; Column I/O ; N ; no ; Off ; +; AE6 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -593,7 +593,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AF5 ; 37 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; -; AF6 ; 83 ; 3B ; B[2] ; input ; 1.2 V ; ; Column I/O ; N ; no ; Off ; +; AF6 ; 83 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF7 ; 80 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF8 ; 78 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF9 ; 75 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1065,7 +1065,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 57 ; 3B ; B[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W14 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; @@ -1120,8 +1120,6 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; OUT_1[1] ; Incomplete set of assignments ; ; OUT_1[2] ; Incomplete set of assignments ; ; OUT_1[3] ; Incomplete set of assignments ; -; B[2] ; Missing location assignment ; -; B[3] ; Missing location assignment ; +----------+-------------------------------+ @@ -1146,16 +1144,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; A[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; op[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; op[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; C[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; C[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; B[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; A[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ @@ -1185,14 +1183,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; - Mux1~0 ; 0 ; 0 ; ; - Mux1~1 ; 0 ; 0 ; ; op[2] ; ; ; -; - Mux0~2 ; 1 ; 0 ; -; - Mux3~0 ; 1 ; 0 ; -; - Mux3~1 ; 1 ; 0 ; -; - Mux2~0 ; 1 ; 0 ; -; - Mux2~3 ; 1 ; 0 ; -; - Mux2~4 ; 1 ; 0 ; -; - Mux1~0 ; 1 ; 0 ; -; - Mux1~1 ; 1 ; 0 ; +; - Mux0~2 ; 0 ; 0 ; +; - Mux3~0 ; 0 ; 0 ; +; - Mux3~1 ; 0 ; 0 ; +; - Mux2~0 ; 0 ; 0 ; +; - Mux2~3 ; 0 ; 0 ; +; - Mux2~4 ; 0 ; 0 ; +; - Mux1~0 ; 0 ; 0 ; +; - Mux1~1 ; 0 ; 0 ; ; op[1] ; ; ; ; - Mux3~0 ; 0 ; 0 ; ; - Mux0~0 ; 0 ; 0 ; @@ -1200,16 +1198,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; - Mux1~2 ; 0 ; 0 ; ; - Mux0~1 ; 0 ; 0 ; ; C[1] ; ; ; -; - ShiftRight0~0 ; 0 ; 0 ; -; - ShiftRight1~0 ; 0 ; 0 ; -; - ShiftLeft0~0 ; 0 ; 0 ; -; - ShiftRight0~1 ; 0 ; 0 ; -; - Mux2~1 ; 0 ; 0 ; -; - Mux2~4 ; 0 ; 0 ; -; - ShiftLeft0~1 ; 0 ; 0 ; -; - ShiftRight0~2 ; 0 ; 0 ; -; - ShiftLeft0~2 ; 0 ; 0 ; -; - ShiftRight0~3 ; 0 ; 0 ; +; - ShiftRight0~0 ; 1 ; 0 ; +; - ShiftRight1~0 ; 1 ; 0 ; +; - ShiftLeft0~0 ; 1 ; 0 ; +; - ShiftRight0~1 ; 1 ; 0 ; +; - Mux2~1 ; 1 ; 0 ; +; - Mux2~4 ; 1 ; 0 ; +; - ShiftLeft0~1 ; 1 ; 0 ; +; - ShiftRight0~2 ; 1 ; 0 ; +; - ShiftLeft0~2 ; 1 ; 0 ; +; - ShiftRight0~3 ; 1 ; 0 ; ; C[0] ; ; ; ; - ShiftRight0~0 ; 1 ; 0 ; ; - ShiftRight1~0 ; 1 ; 0 ; @@ -1222,11 +1220,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; - ShiftLeft0~2 ; 1 ; 0 ; ; - ShiftRight0~3 ; 1 ; 0 ; ; B[2] ; ; ; -; - ShiftRight2~0 ; 1 ; 0 ; -; - ShiftLeft1~0 ; 1 ; 0 ; -; - ShiftLeft1~1 ; 1 ; 0 ; -; - ShiftRight2~2 ; 1 ; 0 ; -; - ShiftRight2~3 ; 1 ; 0 ; +; - ShiftRight2~0 ; 0 ; 0 ; +; - ShiftLeft1~0 ; 0 ; 0 ; +; - ShiftLeft1~1 ; 0 ; 0 ; +; - ShiftRight2~2 ; 0 ; 0 ; +; - ShiftRight2~3 ; 0 ; 0 ; ; B[3] ; ; ; ; - ShiftRight2~0 ; 1 ; 0 ; ; - ShiftLeft1~0 ; 1 ; 0 ; @@ -1268,18 +1266,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; - ShiftLeft0~2 ; 1 ; 0 ; ; - ShiftLeft1~3 ; 1 ; 0 ; ; A[1] ; ; ; -; - ShiftRight3~0 ; 1 ; 0 ; -; - ShiftRight1~0 ; 1 ; 0 ; -; - ShiftLeft0~0 ; 1 ; 0 ; -; - ShiftRight0~1 ; 1 ; 0 ; -; - ShiftLeft1~1 ; 1 ; 0 ; -; - ShiftRight2~1 ; 1 ; 0 ; -; - Mux2~2 ; 1 ; 0 ; -; - Mux2~4 ; 1 ; 0 ; -; - ShiftLeft0~1 ; 1 ; 0 ; -; - ShiftLeft1~2 ; 1 ; 0 ; -; - ShiftLeft0~2 ; 1 ; 0 ; -; - ShiftLeft1~3 ; 1 ; 0 ; +; - ShiftRight3~0 ; 0 ; 0 ; +; - ShiftRight1~0 ; 0 ; 0 ; +; - ShiftLeft0~0 ; 0 ; 0 ; +; - ShiftRight0~1 ; 0 ; 0 ; +; - ShiftLeft1~1 ; 0 ; 0 ; +; - ShiftRight2~1 ; 0 ; 0 ; +; - Mux2~2 ; 0 ; 0 ; +; - Mux2~4 ; 0 ; 0 ; +; - ShiftLeft0~1 ; 0 ; 0 ; +; - ShiftLeft1~2 ; 0 ; 0 ; +; - ShiftLeft0~2 ; 0 ; 0 ; +; - ShiftLeft1~3 ; 0 ; 0 ; ; A[3] ; ; ; ; - ShiftRight3~0 ; 0 ; 0 ; ; - ShiftRight1~0 ; 0 ; 0 ; @@ -1304,22 +1302,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------------------------+------------------------+ ; Routing Resource Type ; Usage ; +------------------------------+------------------------+ -; Block interconnects ; 42 / 217,884 ( < 1 % ) ; -; C12 interconnects ; 8 / 10,080 ( < 1 % ) ; +; Block interconnects ; 44 / 217,884 ( < 1 % ) ; +; C12 interconnects ; 9 / 10,080 ( < 1 % ) ; ; C2 interconnects ; 9 / 87,208 ( < 1 % ) ; -; C4 interconnects ; 57 / 41,360 ( < 1 % ) ; +; C4 interconnects ; 53 / 41,360 ( < 1 % ) ; ; DQS bus muxes ; 0 / 21 ( 0 % ) ; ; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; ; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; -; Direct links ; 0 / 217,884 ( 0 % ) ; +; Direct links ; 8 / 217,884 ( < 1 % ) ; ; Global clocks ; 0 / 16 ( 0 % ) ; ; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; -; Local interconnects ; 22 / 58,160 ( < 1 % ) ; +; Local interconnects ; 19 / 58,160 ( < 1 % ) ; ; Quadrant clocks ; 0 / 88 ( 0 % ) ; ; R14 interconnects ; 10 / 9,228 ( < 1 % ) ; ; R14/C12 interconnect drivers ; 15 / 15,096 ( < 1 % ) ; ; R3 interconnects ; 24 / 94,896 ( < 1 % ) ; -; R6 interconnects ; 23 / 194,640 ( < 1 % ) ; +; R6 interconnects ; 20 / 194,640 ( < 1 % ) ; ; Spine clocks ; 0 / 180 ( 0 % ) ; ; Wire stub REs ; 0 / 11,606 ( 0 % ) ; +------------------------------+------------------------+ @@ -1375,33 +1373,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Matrix ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ -; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ -; Total Pass ; 0 ; 15 ; 15 ; 0 ; 0 ; 17 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 17 ; 17 ; 0 ; -; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 17 ; 2 ; 2 ; 17 ; 17 ; 0 ; 2 ; 17 ; 17 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 0 ; 0 ; 17 ; -; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Total Pass ; 0 ; 17 ; 17 ; 0 ; 0 ; 17 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 17 ; 17 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 17 ; 0 ; 0 ; 17 ; 17 ; 0 ; 0 ; 17 ; 17 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 0 ; 0 ; 17 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +------------------------------------------------------------------------------------------------+ @@ -1458,13 +1456,12 @@ Info (21077): High junction temperature is 85 degrees C Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Critical Warning (169085): No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. Info (184020): Starting Fitter periphery placement operations Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks -Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08 +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07 Critical Warning (332012): Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. @@ -1474,7 +1471,7 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. Info (170189): Fitter placement preparation operations beginning Info (14951): The Fitter is using Advanced Physical Optimization. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 @@ -1485,17 +1482,17 @@ Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings - Info: Peak virtual memory: 1379 megabytes - Info: Processing ended: Tue Sep 15 19:39:25 2026 - Info: Elapsed time: 00:00:36 - Info: Total CPU time (on all processors): 00:00:50 +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 1382 megabytes + Info: Processing ended: Tue Sep 15 19:49:23 2026 + Info: Elapsed time: 00:00:29 + Info: Total CPU time (on all processors): 00:00:41 diff --git a/Quartus/A1_Q5/output_files/shifter.fit.summary b/Quartus/A1_Q5/output_files/shifter.fit.summary index a92456d..052503a 100644 --- a/Quartus/A1_Q5/output_files/shifter.fit.summary +++ b/Quartus/A1_Q5/output_files/shifter.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Sep 15 19:39:25 2026 +Fitter Status : Successful - Tue Sep 15 19:49:22 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : shifter Top-level Entity Name : shifter diff --git a/Quartus/A1_Q5/output_files/shifter.flow.rpt b/Quartus/A1_Q5/output_files/shifter.flow.rpt index 1c1dd35..bd4d3c3 100644 --- a/Quartus/A1_Q5/output_files/shifter.flow.rpt +++ b/Quartus/A1_Q5/output_files/shifter.flow.rpt @@ -1,5 +1,5 @@ Flow report for shifter -Tue Sep 15 19:39:43 2026 +Tue Sep 15 19:49:39 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,7 +41,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Sep 15 19:39:43 2026 ; +; Flow Status ; Successful - Tue Sep 15 19:49:39 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/15/2026 19:38:37 ; +; Start date & time ; 09/15/2026 19:48:42 ; ; Main task ; Compilation ; ; Revision Name ; shifter ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 268883478169649.178946511707335 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 268883478169649.178946572208013 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,12 +101,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ; -; Fitter ; 00:00:36 ; 1.0 ; 1379 MB ; 00:00:50 ; -; Assembler ; 00:00:06 ; 1.0 ; 507 MB ; 00:00:06 ; -; Timing Analyzer ; 00:00:06 ; 1.0 ; 777 MB ; 00:00:06 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:25 ; +; Fitter ; 00:00:28 ; 1.0 ; 1382 MB ; 00:00:41 ; +; Assembler ; 00:00:06 ; 1.0 ; 518 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:05 ; 1.0 ; 773 MB ; 00:00:06 ; ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ; -; Total ; 00:01:00 ; -- ; -- ; 00:01:27 ; +; Total ; 00:00:51 ; -- ; -- ; 00:01:18 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A1_Q5/output_files/shifter.map.rpt b/Quartus/A1_Q5/output_files/shifter.map.rpt index b988f60..b2191ac 100644 --- a/Quartus/A1_Q5/output_files/shifter.map.rpt +++ b/Quartus/A1_Q5/output_files/shifter.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for shifter -Tue Sep 15 19:38:48 2026 +Tue Sep 15 19:48:53 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -44,7 +44,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:38:48 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:48:53 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; @@ -274,7 +274,7 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 19:38:37 2026 + Info: Processing started: Tue Sep 15 19:48:42 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -290,8 +290,8 @@ Info (21057): Implemented 49 device resources after synthesis - the final resour Info (21061): Implemented 32 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning Info: Peak virtual memory: 433 megabytes - Info: Processing ended: Tue Sep 15 19:38:48 2026 + Info: Processing ended: Tue Sep 15 19:48:53 2026 Info: Elapsed time: 00:00:11 - Info: Total CPU time (on all processors): 00:00:24 + Info: Total CPU time (on all processors): 00:00:25 diff --git a/Quartus/A1_Q5/output_files/shifter.map.summary b/Quartus/A1_Q5/output_files/shifter.map.summary index dc60e32..7dd243c 100644 --- a/Quartus/A1_Q5/output_files/shifter.map.summary +++ b/Quartus/A1_Q5/output_files/shifter.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Tue Sep 15 19:38:48 2026 +Analysis & Synthesis Status : Successful - Tue Sep 15 19:48:53 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : shifter Top-level Entity Name : shifter diff --git a/Quartus/A1_Q5/output_files/shifter.pin b/Quartus/A1_Q5/output_files/shifter.pin index d468975..8396dc6 100644 --- a/Quartus/A1_Q5/output_files/shifter.pin +++ b/Quartus/A1_Q5/output_files/shifter.pin @@ -135,7 +135,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : NC : AB7 : : : : : GND : AB8 : gnd : : : : VCCPD3A : AB9 : power : : 2.5V : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B : +B[3] : AB10 : input : 1.2 V : : 3B : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B : VCCIO4A : AB13 : power : : 1.2V : 4A : @@ -209,7 +209,7 @@ GND : AE2 : gnd : : GXB_NC : AE3 : : : : B0L : GXB_NC : AE4 : : : : B0L : GND : AE5 : gnd : : : : -B[3] : AE6 : input : 1.2 V : : 3B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3B : GND : AE7 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B : @@ -234,7 +234,7 @@ GND : AF2 : gnd : : GND : AF3 : gnd : : : : GND : AF4 : gnd : : : : AS_DATA0, ASDO, DATA0 : AF5 : : : : 3A : -B[2] : AF6 : input : 1.2 V : : 3B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B : @@ -706,7 +706,7 @@ VCCA_FPLL : W7 : power : : 2.5V RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A : GND : W9 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : +B[2] : W11 : input : 1.2 V : : 3B : Y RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A : VCCIO4A : W14 : power : : 1.2V : 4A : diff --git a/Quartus/A1_Q5/output_files/shifter.sof b/Quartus/A1_Q5/output_files/shifter.sof index 6bb17cb..9a7423f 100644 Binary files a/Quartus/A1_Q5/output_files/shifter.sof and b/Quartus/A1_Q5/output_files/shifter.sof differ diff --git a/Quartus/A1_Q5/output_files/shifter.sta.rpt b/Quartus/A1_Q5/output_files/shifter.sta.rpt index e106151..6ac76a2 100644 --- a/Quartus/A1_Q5/output_files/shifter.sta.rpt +++ b/Quartus/A1_Q5/output_files/shifter.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for shifter -Tue Sep 15 19:39:40 2026 +Tue Sep 15 19:49:36 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -103,7 +103,7 @@ on the Quartus Prime software download page. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 3.0% ; +; Processor 2 ; 2.8% ; +----------------------------+-------------+ @@ -470,7 +470,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 19:39:34 2026 + Info: Processing started: Tue Sep 15 19:49:31 2026 Info: Command: quartus_sta A1_Q5 -c shifter Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -530,9 +530,9 @@ Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 777 megabytes - Info: Processing ended: Tue Sep 15 19:39:40 2026 - Info: Elapsed time: 00:00:06 + Info: Peak virtual memory: 773 megabytes + Info: Processing ended: Tue Sep 15 19:49:36 2026 + Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:06 diff --git a/Quartus/A1_Q5/shifter.qsf b/Quartus/A1_Q5/shifter.qsf index 2d2d6f9..2d61de3 100644 --- a/Quartus/A1_Q5/shifter.qsf +++ b/Quartus/A1_Q5/shifter.qsf @@ -90,4 +90,6 @@ set_location_assignment PIN_P11 -to A[0] set_location_assignment PIN_P12 -to A[1] set_location_assignment PIN_Y15 -to A[2] set_location_assignment PIN_Y16 -to A[3] +set_location_assignment PIN_W11 -to B[2] +set_location_assignment PIN_AB10 -to B[3] set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/A1_Q5/shifter.qws b/Quartus/A1_Q5/shifter.qws new file mode 100644 index 0000000..043c1c2 Binary files /dev/null and b/Quartus/A1_Q5/shifter.qws differ diff --git a/Quartus/A1_Q5/simulation/questa/shifter.svo b/Quartus/A1_Q5/simulation/questa/shifter.svo index 4c3c5f6..5c16df2 100644 --- a/Quartus/A1_Q5/simulation/questa/shifter.svo +++ b/Quartus/A1_Q5/simulation/questa/shifter.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "09/15/2026 19:39:43" +// DATE "09/15/2026 19:49:39" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 @@ -35,11 +35,11 @@ module shifter ( B, C, OUT_1); -input logic [2:0] op ; -input logic [3:0] A ; -input logic [3:0] B ; -input logic [1:0] C ; -output logic [3:0] OUT_1 ; +input [2:0] op; +input [3:0] A; +input [3:0] B; +input [1:0] C; +output [3:0] OUT_1; // Design Ports Information // OUT_1[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default @@ -52,8 +52,8 @@ output logic [3:0] OUT_1 ; // op[1] => Location: PIN_Y11, I/O Standard: 1.2 V, Current Strength: Default // C[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default // C[0] => Location: PIN_AC9, I/O Standard: 1.2 V, Current Strength: Default -// B[2] => Location: PIN_AF6, I/O Standard: 1.2 V, Current Strength: Default -// B[3] => Location: PIN_AE6, I/O Standard: 1.2 V, Current Strength: Default +// B[2] => Location: PIN_W11, I/O Standard: 1.2 V, Current Strength: Default +// B[3] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default // B[1] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default // B[0] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default // A[2] => Location: PIN_Y15, I/O Standard: 1.2 V, Current Strength: Default @@ -73,48 +73,48 @@ tri1 devclrn; tri1 devpor; tri1 devoe; wire \~QUARTUS_CREATED_GND~I_combout ; -wire \C[1]~input_o ; -wire \C[0]~input_o ; -wire \ShiftRight0~0_combout ; -wire \op[1]~input_o ; -wire \B[3]~input_o ; -wire \B[2]~input_o ; -wire \B[0]~input_o ; -wire \B[1]~input_o ; -wire \ShiftRight2~0_combout ; -wire \op[2]~input_o ; -wire \Mux3~0_combout ; wire \op[0]~input_o ; -wire \A[3]~input_o ; -wire \Mux0~0_combout ; wire \A[1]~input_o ; wire \A[0]~input_o ; wire \A[2]~input_o ; -wire \ShiftRight1~0_combout ; -wire \ShiftLeft1~0_combout ; +wire \A[3]~input_o ; +wire \B[1]~input_o ; +wire \B[0]~input_o ; wire \ShiftRight3~0_combout ; +wire \op[1]~input_o ; +wire \Mux0~0_combout ; +wire \B[3]~input_o ; +wire \B[2]~input_o ; +wire \ShiftLeft1~0_combout ; +wire \C[1]~input_o ; +wire \C[0]~input_o ; +wire \ShiftRight1~0_combout ; +wire \op[2]~input_o ; wire \Mux3~1_combout ; +wire \ShiftRight2~0_combout ; +wire \ShiftRight0~0_combout ; +wire \Mux3~0_combout ; wire \Mux3~2_combout ; -wire \Mux2~4_combout ; wire \Mux2~1_combout ; wire \Mux2~2_combout ; wire \Mux2~3_combout ; wire \ShiftLeft1~1_combout ; -wire \ShiftRight2~1_combout ; wire \ShiftLeft0~0_combout ; +wire \ShiftRight2~1_combout ; wire \ShiftRight0~1_combout ; wire \Mux2~0_combout ; +wire \Mux2~4_combout ; wire \Mux2~5_combout ; wire \Mux1~1_combout ; -wire \ShiftRight2~2_combout ; -wire \ShiftLeft0~1_combout ; -wire \ShiftLeft1~2_combout ; wire \ShiftRight0~2_combout ; +wire \ShiftRight2~2_combout ; +wire \ShiftLeft1~2_combout ; +wire \ShiftLeft0~1_combout ; wire \Mux1~0_combout ; wire \Mux1~2_combout ; -wire \ShiftRight0~3_combout ; -wire \ShiftRight2~3_combout ; wire \ShiftLeft1~3_combout ; +wire \ShiftRight2~3_combout ; +wire \ShiftRight0~3_combout ; wire \ShiftLeft0~2_combout ; wire \Mux0~2_combout ; wire \Mux0~1_combout ; @@ -184,166 +184,6 @@ defparam \OUT_1[3]~output .open_drain_output = "false"; defparam \OUT_1[3]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOIBUF_X36_Y0_N52 -cyclonev_io_ibuf \C[1]~input ( - .i(C[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\C[1]~input_o )); -// synopsys translate_off -defparam \C[1]~input .bus_hold = "false"; -defparam \C[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X14_Y0_N35 -cyclonev_io_ibuf \C[0]~input ( - .i(C[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\C[0]~input_o )); -// synopsys translate_off -defparam \C[0]~input .bus_hold = "false"; -defparam \C[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: MLABCELL_X19_Y4_N36 -cyclonev_lcell_comb \ShiftRight0~0 ( -// Equation(s): -// \ShiftRight0~0_combout = (!\C[1]~input_o & !\C[0]~input_o ) - - .dataa(gnd), - .datab(!\C[1]~input_o ), - .datac(!\C[0]~input_o ), - .datad(gnd), - .datae(gnd), - .dataf(gnd), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight0~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight0~0 .extended_lut = "off"; -defparam \ShiftRight0~0 .lut_mask = 64'hC0C0C0C0C0C0C0C0; -defparam \ShiftRight0~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: IOIBUF_X10_Y0_N58 -cyclonev_io_ibuf \op[1]~input ( - .i(op[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[1]~input_o )); -// synopsys translate_off -defparam \op[1]~input .bus_hold = "false"; -defparam \op[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X21_Y0_N35 -cyclonev_io_ibuf \B[3]~input ( - .i(B[3]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[3]~input_o )); -// synopsys translate_off -defparam \B[3]~input .bus_hold = "false"; -defparam \B[3]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X21_Y0_N52 -cyclonev_io_ibuf \B[2]~input ( - .i(B[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[2]~input_o )); -// synopsys translate_off -defparam \B[2]~input .bus_hold = "false"; -defparam \B[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X34_Y0_N35 -cyclonev_io_ibuf \B[0]~input ( - .i(B[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[0]~input_o )); -// synopsys translate_off -defparam \B[0]~input .bus_hold = "false"; -defparam \B[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X14_Y0_N52 -cyclonev_io_ibuf \B[1]~input ( - .i(B[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[1]~input_o )); -// synopsys translate_off -defparam \B[1]~input .bus_hold = "false"; -defparam \B[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LABCELL_X21_Y4_N0 -cyclonev_lcell_comb \ShiftRight2~0 ( -// Equation(s): -// \ShiftRight2~0_combout = (!\B[3]~input_o & (!\B[2]~input_o & (!\B[0]~input_o & !\B[1]~input_o ))) - - .dataa(!\B[3]~input_o ), - .datab(!\B[2]~input_o ), - .datac(!\B[0]~input_o ), - .datad(!\B[1]~input_o ), - .datae(gnd), - .dataf(gnd), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight2~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight2~0 .extended_lut = "off"; -defparam \ShiftRight2~0 .lut_mask = 64'h8000800080008000; -defparam \ShiftRight2~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: IOIBUF_X50_Y0_N35 -cyclonev_io_ibuf \op[2]~input ( - .i(op[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[2]~input_o )); -// synopsys translate_off -defparam \op[2]~input .bus_hold = "false"; -defparam \op[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: MLABCELL_X19_Y4_N39 -cyclonev_lcell_comb \Mux3~0 ( -// Equation(s): -// \Mux3~0_combout = ( \op[2]~input_o & ( (!\op[1]~input_o & !\ShiftRight2~0_combout ) ) ) # ( !\op[2]~input_o & ( (!\ShiftRight0~0_combout & !\op[1]~input_o ) ) ) - - .dataa(!\ShiftRight0~0_combout ), - .datab(gnd), - .datac(!\op[1]~input_o ), - .datad(!\ShiftRight2~0_combout ), - .datae(gnd), - .dataf(!\op[2]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux3~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux3~0 .extended_lut = "off"; -defparam \Mux3~0 .lut_mask = 64'hA0A0A0A0F000F000; -defparam \Mux3~0 .shared_arith = "off"; -// synopsys translate_on - // Location: IOIBUF_X12_Y0_N52 cyclonev_io_ibuf \op[0]~input ( .i(op[0]), @@ -355,41 +195,6 @@ defparam \op[0]~input .bus_hold = "false"; defparam \op[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: IOIBUF_X46_Y0_N18 -cyclonev_io_ibuf \A[3]~input ( - .i(A[3]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[3]~input_o )); -// synopsys translate_off -defparam \A[3]~input .bus_hold = "false"; -defparam \A[3]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: MLABCELL_X19_Y4_N21 -cyclonev_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = ( \A[3]~input_o & ( \op[1]~input_o ) ) - - .dataa(gnd), - .datab(gnd), - .datac(!\op[1]~input_o ), - .datad(gnd), - .datae(gnd), - .dataf(!\A[3]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux0~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux0~0 .extended_lut = "off"; -defparam \Mux0~0 .lut_mask = 64'h000000000F0F0F0F; -defparam \Mux0~0 .shared_arith = "off"; -// synopsys translate_on - // Location: IOIBUF_X21_Y0_N18 cyclonev_io_ibuf \A[1]~input ( .i(A[1]), @@ -423,56 +228,40 @@ defparam \A[2]~input .bus_hold = "false"; defparam \A[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: MLABCELL_X19_Y4_N12 -cyclonev_lcell_comb \ShiftRight1~0 ( -// Equation(s): -// \ShiftRight1~0_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[3]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[1]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o -// & ( \A[0]~input_o ) ) ) - - .dataa(!\A[1]~input_o ), - .datab(!\A[0]~input_o ), - .datac(!\A[3]~input_o ), - .datad(!\A[2]~input_o ), - .datae(!\C[1]~input_o ), - .dataf(!\C[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight1~0_combout ), - .sumout(), - .cout(), - .shareout()); +// Location: IOIBUF_X46_Y0_N18 +cyclonev_io_ibuf \A[3]~input ( + .i(A[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[3]~input_o )); // synopsys translate_off -defparam \ShiftRight1~0 .extended_lut = "off"; -defparam \ShiftRight1~0 .lut_mask = 64'h333300FF55550F0F; -defparam \ShiftRight1~0 .shared_arith = "off"; +defparam \A[3]~input .bus_hold = "false"; +defparam \A[3]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N3 -cyclonev_lcell_comb \ShiftLeft1~0 ( -// Equation(s): -// \ShiftLeft1~0_combout = (\B[2]~input_o ) # (\B[3]~input_o ) - - .dataa(!\B[3]~input_o ), - .datab(!\B[2]~input_o ), - .datac(gnd), - .datad(gnd), - .datae(gnd), - .dataf(gnd), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft1~0_combout ), - .sumout(), - .cout(), - .shareout()); +// Location: IOIBUF_X14_Y0_N52 +cyclonev_io_ibuf \B[1]~input ( + .i(B[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[1]~input_o )); // synopsys translate_off -defparam \ShiftLeft1~0 .extended_lut = "off"; -defparam \ShiftLeft1~0 .lut_mask = 64'h7777777777777777; -defparam \ShiftLeft1~0 .shared_arith = "off"; +defparam \B[1]~input .bus_hold = "false"; +defparam \B[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: MLABCELL_X19_Y4_N15 +// Location: IOIBUF_X34_Y0_N35 +cyclonev_io_ibuf \B[0]~input ( + .i(B[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[0]~input_o )); +// synopsys translate_off +defparam \B[0]~input .bus_hold = "false"; +defparam \B[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N21 cyclonev_lcell_comb \ShiftRight3~0 ( // Equation(s): // \ShiftRight3~0_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[3]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[1]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o @@ -497,19 +286,156 @@ defparam \ShiftRight3~0 .lut_mask = 64'h33330F0F555500FF; defparam \ShiftRight3~0 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X19_Y4_N54 +// Location: IOIBUF_X10_Y0_N58 +cyclonev_io_ibuf \op[1]~input ( + .i(op[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[1]~input_o )); +// synopsys translate_off +defparam \op[1]~input .bus_hold = "false"; +defparam \op[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X18_Y4_N9 +cyclonev_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\op[1]~input_o & \A[3]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(!\op[1]~input_o ), + .datad(!\A[3]~input_o ), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux0~0 .extended_lut = "off"; +defparam \Mux0~0 .lut_mask = 64'h000F000F000F000F; +defparam \Mux0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X12_Y0_N35 +cyclonev_io_ibuf \B[3]~input ( + .i(B[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[3]~input_o )); +// synopsys translate_off +defparam \B[3]~input .bus_hold = "false"; +defparam \B[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X10_Y0_N41 +cyclonev_io_ibuf \B[2]~input ( + .i(B[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[2]~input_o )); +// synopsys translate_off +defparam \B[2]~input .bus_hold = "false"; +defparam \B[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X18_Y4_N6 +cyclonev_lcell_comb \ShiftLeft1~0 ( +// Equation(s): +// \ShiftLeft1~0_combout = ( \B[2]~input_o ) # ( !\B[2]~input_o & ( \B[3]~input_o ) ) + + .dataa(gnd), + .datab(gnd), + .datac(!\B[3]~input_o ), + .datad(gnd), + .datae(gnd), + .dataf(!\B[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~0 .extended_lut = "off"; +defparam \ShiftLeft1~0 .lut_mask = 64'h0F0F0F0FFFFFFFFF; +defparam \ShiftLeft1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X36_Y0_N52 +cyclonev_io_ibuf \C[1]~input ( + .i(C[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[1]~input_o )); +// synopsys translate_off +defparam \C[1]~input .bus_hold = "false"; +defparam \C[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N35 +cyclonev_io_ibuf \C[0]~input ( + .i(C[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[0]~input_o )); +// synopsys translate_off +defparam \C[0]~input .bus_hold = "false"; +defparam \C[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N18 +cyclonev_lcell_comb \ShiftRight1~0 ( +// Equation(s): +// \ShiftRight1~0_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[3]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[1]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o +// & ( \A[0]~input_o ) ) ) + + .dataa(!\A[1]~input_o ), + .datab(!\A[0]~input_o ), + .datac(!\A[3]~input_o ), + .datad(!\A[2]~input_o ), + .datae(!\C[1]~input_o ), + .dataf(!\C[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight1~0 .extended_lut = "off"; +defparam \ShiftRight1~0 .lut_mask = 64'h333300FF55550F0F; +defparam \ShiftRight1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X50_Y0_N35 +cyclonev_io_ibuf \op[2]~input ( + .i(op[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[2]~input_o )); +// synopsys translate_off +defparam \op[2]~input .bus_hold = "false"; +defparam \op[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X18_Y4_N42 cyclonev_lcell_comb \Mux3~1 ( // Equation(s): -// \Mux3~1_combout = ( \ShiftLeft1~0_combout & ( \ShiftRight3~0_combout & ( (\op[0]~input_o & ((!\op[2]~input_o & ((\ShiftRight1~0_combout ))) # (\op[2]~input_o & (\Mux0~0_combout )))) ) ) ) # ( !\ShiftLeft1~0_combout & ( \ShiftRight3~0_combout & ( -// (\op[0]~input_o & ((\ShiftRight1~0_combout ) # (\op[2]~input_o ))) ) ) ) # ( \ShiftLeft1~0_combout & ( !\ShiftRight3~0_combout & ( (\op[0]~input_o & ((!\op[2]~input_o & ((\ShiftRight1~0_combout ))) # (\op[2]~input_o & (\Mux0~0_combout )))) ) ) ) # ( -// !\ShiftLeft1~0_combout & ( !\ShiftRight3~0_combout & ( (!\op[2]~input_o & (\op[0]~input_o & \ShiftRight1~0_combout )) ) ) ) +// \Mux3~1_combout = ( \op[0]~input_o & ( \op[2]~input_o & ( (!\ShiftLeft1~0_combout & (\ShiftRight3~0_combout )) # (\ShiftLeft1~0_combout & ((\Mux0~0_combout ))) ) ) ) # ( \op[0]~input_o & ( !\op[2]~input_o & ( \ShiftRight1~0_combout ) ) ) - .dataa(!\op[2]~input_o ), - .datab(!\op[0]~input_o ), - .datac(!\Mux0~0_combout ), + .dataa(!\ShiftRight3~0_combout ), + .datab(!\Mux0~0_combout ), + .datac(!\ShiftLeft1~0_combout ), .datad(!\ShiftRight1~0_combout ), - .datae(!\ShiftLeft1~0_combout ), - .dataf(!\ShiftRight3~0_combout ), + .datae(!\op[0]~input_o ), + .dataf(!\op[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -519,21 +445,93 @@ cyclonev_lcell_comb \Mux3~1 ( .shareout()); // synopsys translate_off defparam \Mux3~1 .extended_lut = "off"; -defparam \Mux3~1 .lut_mask = 64'h0022012311330123; +defparam \Mux3~1 .lut_mask = 64'h000000FF00005353; defparam \Mux3~1 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X19_Y4_N18 -cyclonev_lcell_comb \Mux3~2 ( +// Location: LABCELL_X18_Y4_N33 +cyclonev_lcell_comb \ShiftRight2~0 ( // Equation(s): -// \Mux3~2_combout = ( \A[0]~input_o & ( ((!\Mux3~0_combout & !\op[0]~input_o )) # (\Mux3~1_combout ) ) ) # ( !\A[0]~input_o & ( \Mux3~1_combout ) ) +// \ShiftRight2~0_combout = ( !\B[3]~input_o & ( (!\B[2]~input_o & (!\B[0]~input_o & !\B[1]~input_o )) ) ) .dataa(gnd), - .datab(!\Mux3~0_combout ), - .datac(!\Mux3~1_combout ), - .datad(!\op[0]~input_o ), + .datab(!\B[2]~input_o ), + .datac(!\B[0]~input_o ), + .datad(!\B[1]~input_o ), .datae(gnd), - .dataf(!\A[0]~input_o ), + .dataf(!\B[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight2~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight2~0 .extended_lut = "off"; +defparam \ShiftRight2~0 .lut_mask = 64'hC000C00000000000; +defparam \ShiftRight2~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N36 +cyclonev_lcell_comb \ShiftRight0~0 ( +// Equation(s): +// \ShiftRight0~0_combout = (!\C[1]~input_o & !\C[0]~input_o ) + + .dataa(!\C[1]~input_o ), + .datab(!\C[0]~input_o ), + .datac(gnd), + .datad(gnd), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight0~0 .extended_lut = "off"; +defparam \ShiftRight0~0 .lut_mask = 64'h8888888888888888; +defparam \ShiftRight0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N12 +cyclonev_lcell_comb \Mux3~0 ( +// Equation(s): +// \Mux3~0_combout = ( !\op[1]~input_o & ( (!\op[2]~input_o & ((!\ShiftRight0~0_combout ))) # (\op[2]~input_o & (!\ShiftRight2~0_combout )) ) ) + + .dataa(gnd), + .datab(!\ShiftRight2~0_combout ), + .datac(!\ShiftRight0~0_combout ), + .datad(!\op[2]~input_o ), + .datae(gnd), + .dataf(!\op[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~0 .extended_lut = "off"; +defparam \Mux3~0 .lut_mask = 64'hF0CCF0CC00000000; +defparam \Mux3~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X18_Y4_N21 +cyclonev_lcell_comb \Mux3~2 ( +// Equation(s): +// \Mux3~2_combout = ( \Mux3~0_combout & ( \Mux3~1_combout ) ) # ( !\Mux3~0_combout & ( ((!\op[0]~input_o & \A[0]~input_o )) # (\Mux3~1_combout ) ) ) + + .dataa(gnd), + .datab(!\op[0]~input_o ), + .datac(!\Mux3~1_combout ), + .datad(!\A[0]~input_o ), + .datae(gnd), + .dataf(!\Mux3~0_combout ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -543,45 +541,21 @@ cyclonev_lcell_comb \Mux3~2 ( .shareout()); // synopsys translate_off defparam \Mux3~2 .extended_lut = "off"; -defparam \Mux3~2 .lut_mask = 64'h0F0F0F0FCF0FCF0F; +defparam \Mux3~2 .lut_mask = 64'h0FCF0FCF0F0F0F0F; defparam \Mux3~2 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N12 -cyclonev_lcell_comb \Mux2~4 ( -// Equation(s): -// \Mux2~4_combout = ( \op[2]~input_o & ( (\A[1]~input_o & !\op[0]~input_o ) ) ) # ( !\op[2]~input_o & ( (\A[1]~input_o & ((!\op[0]~input_o ) # ((!\C[0]~input_o & !\C[1]~input_o )))) ) ) - - .dataa(!\C[0]~input_o ), - .datab(!\A[1]~input_o ), - .datac(!\op[0]~input_o ), - .datad(!\C[1]~input_o ), - .datae(gnd), - .dataf(!\op[2]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux2~4_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux2~4 .extended_lut = "off"; -defparam \Mux2~4 .lut_mask = 64'h3230323030303030; -defparam \Mux2~4 .shared_arith = "off"; -// synopsys translate_on - -// Location: MLABCELL_X19_Y4_N33 +// Location: LABCELL_X18_Y4_N12 cyclonev_lcell_comb \Mux2~1 ( // Equation(s): -// \Mux2~1_combout = ( \A[3]~input_o & ( ((\C[0]~input_o & \A[2]~input_o )) # (\C[1]~input_o ) ) ) # ( !\A[3]~input_o & ( (\C[0]~input_o & (\A[2]~input_o & !\C[1]~input_o )) ) ) +// \Mux2~1_combout = ( \C[0]~input_o & ( (!\C[1]~input_o & ((\A[2]~input_o ))) # (\C[1]~input_o & (\A[3]~input_o )) ) ) # ( !\C[0]~input_o & ( (\A[3]~input_o & \C[1]~input_o ) ) ) - .dataa(!\C[0]~input_o ), - .datab(!\A[2]~input_o ), + .dataa(gnd), + .datab(!\A[3]~input_o ), .datac(!\C[1]~input_o ), - .datad(gnd), + .datad(!\A[2]~input_o ), .datae(gnd), - .dataf(!\A[3]~input_o ), + .dataf(!\C[0]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -591,21 +565,21 @@ cyclonev_lcell_comb \Mux2~1 ( .shareout()); // synopsys translate_off defparam \Mux2~1 .extended_lut = "off"; -defparam \Mux2~1 .lut_mask = 64'h101010101F1F1F1F; +defparam \Mux2~1 .lut_mask = 64'h0303030303F303F3; defparam \Mux2~1 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X19_Y4_N30 +// Location: LABCELL_X18_Y4_N51 cyclonev_lcell_comb \Mux2~2 ( // Equation(s): -// \Mux2~2_combout = ( \B[0]~input_o & ( \A[2]~input_o ) ) # ( !\B[0]~input_o & ( \A[1]~input_o ) ) +// \Mux2~2_combout = (!\B[0]~input_o & (\A[1]~input_o )) # (\B[0]~input_o & ((\A[2]~input_o ))) - .dataa(gnd), - .datab(!\A[2]~input_o ), - .datac(!\A[1]~input_o ), - .datad(gnd), + .dataa(!\A[1]~input_o ), + .datab(gnd), + .datac(!\B[0]~input_o ), + .datad(!\A[2]~input_o ), .datae(gnd), - .dataf(!\B[0]~input_o ), + .dataf(gnd), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -615,21 +589,21 @@ cyclonev_lcell_comb \Mux2~2 ( .shareout()); // synopsys translate_off defparam \Mux2~2 .extended_lut = "off"; -defparam \Mux2~2 .lut_mask = 64'h0F0F0F0F33333333; +defparam \Mux2~2 .lut_mask = 64'h505F505F505F505F; defparam \Mux2~2 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X19_Y4_N6 +// Location: LABCELL_X18_Y4_N24 cyclonev_lcell_comb \Mux2~3 ( // Equation(s): -// \Mux2~3_combout = ( \ShiftLeft1~0_combout & ( \op[2]~input_o & ( \A[3]~input_o ) ) ) # ( !\ShiftLeft1~0_combout & ( \op[2]~input_o & ( (!\B[1]~input_o & ((\Mux2~2_combout ))) # (\B[1]~input_o & (\A[3]~input_o )) ) ) ) # ( \ShiftLeft1~0_combout & -// ( !\op[2]~input_o & ( \Mux2~1_combout ) ) ) # ( !\ShiftLeft1~0_combout & ( !\op[2]~input_o & ( \Mux2~1_combout ) ) ) +// \Mux2~3_combout = ( \B[1]~input_o & ( \op[2]~input_o & ( \A[3]~input_o ) ) ) # ( !\B[1]~input_o & ( \op[2]~input_o & ( (!\ShiftLeft1~0_combout & (\Mux2~2_combout )) # (\ShiftLeft1~0_combout & ((\A[3]~input_o ))) ) ) ) # ( \B[1]~input_o & ( +// !\op[2]~input_o & ( \Mux2~1_combout ) ) ) # ( !\B[1]~input_o & ( !\op[2]~input_o & ( \Mux2~1_combout ) ) ) - .dataa(!\A[3]~input_o ), - .datab(!\B[1]~input_o ), - .datac(!\Mux2~1_combout ), - .datad(!\Mux2~2_combout ), - .datae(!\ShiftLeft1~0_combout ), + .dataa(!\ShiftLeft1~0_combout ), + .datab(!\Mux2~1_combout ), + .datac(!\Mux2~2_combout ), + .datad(!\A[3]~input_o ), + .datae(!\B[1]~input_o ), .dataf(!\op[2]~input_o ), .datag(gnd), .cin(gnd), @@ -640,20 +614,20 @@ cyclonev_lcell_comb \Mux2~3 ( .shareout()); // synopsys translate_off defparam \Mux2~3 .extended_lut = "off"; -defparam \Mux2~3 .lut_mask = 64'h0F0F0F0F11DD5555; +defparam \Mux2~3 .lut_mask = 64'h333333330A5F00FF; defparam \Mux2~3 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N48 +// Location: LABCELL_X18_Y4_N54 cyclonev_lcell_comb \ShiftLeft1~1 ( // Equation(s): -// \ShiftLeft1~1_combout = ( \A[0]~input_o & ( \A[1]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & !\B[2]~input_o )) ) ) ) # ( !\A[0]~input_o & ( \A[1]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & (!\B[0]~input_o & !\B[2]~input_o ))) ) ) ) # ( -// \A[0]~input_o & ( !\A[1]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & (\B[0]~input_o & !\B[2]~input_o ))) ) ) ) +// \ShiftLeft1~1_combout = ( \A[0]~input_o & ( \A[1]~input_o & ( (!\B[2]~input_o & (!\B[1]~input_o & !\B[3]~input_o )) ) ) ) # ( !\A[0]~input_o & ( \A[1]~input_o & ( (!\B[2]~input_o & (!\B[1]~input_o & (!\B[3]~input_o & !\B[0]~input_o ))) ) ) ) # ( +// \A[0]~input_o & ( !\A[1]~input_o & ( (!\B[2]~input_o & (!\B[1]~input_o & (!\B[3]~input_o & \B[0]~input_o ))) ) ) ) - .dataa(!\B[3]~input_o ), + .dataa(!\B[2]~input_o ), .datab(!\B[1]~input_o ), - .datac(!\B[0]~input_o ), - .datad(!\B[2]~input_o ), + .datac(!\B[3]~input_o ), + .datad(!\B[0]~input_o ), .datae(!\A[0]~input_o ), .dataf(!\A[1]~input_o ), .datag(gnd), @@ -665,46 +639,21 @@ cyclonev_lcell_comb \ShiftLeft1~1 ( .shareout()); // synopsys translate_off defparam \ShiftLeft1~1 .extended_lut = "off"; -defparam \ShiftLeft1~1 .lut_mask = 64'h0000080080008800; +defparam \ShiftLeft1~1 .lut_mask = 64'h0000008080008080; defparam \ShiftLeft1~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N54 -cyclonev_lcell_comb \ShiftRight2~1 ( -// Equation(s): -// \ShiftRight2~1_combout = ( \B[0]~input_o & ( \A[2]~input_o & ( (!\ShiftLeft1~0_combout & !\B[1]~input_o ) ) ) ) # ( !\B[0]~input_o & ( \A[2]~input_o & ( (!\ShiftLeft1~0_combout & ((!\B[1]~input_o & (\A[1]~input_o )) # (\B[1]~input_o & -// ((\A[3]~input_o ))))) ) ) ) # ( !\B[0]~input_o & ( !\A[2]~input_o & ( (!\ShiftLeft1~0_combout & ((!\B[1]~input_o & (\A[1]~input_o )) # (\B[1]~input_o & ((\A[3]~input_o ))))) ) ) ) - - .dataa(!\ShiftLeft1~0_combout ), - .datab(!\B[1]~input_o ), - .datac(!\A[1]~input_o ), - .datad(!\A[3]~input_o ), - .datae(!\B[0]~input_o ), - .dataf(!\A[2]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight2~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight2~1 .extended_lut = "off"; -defparam \ShiftRight2~1 .lut_mask = 64'h082A0000082A8888; -defparam \ShiftRight2~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X21_Y4_N6 +// Location: LABCELL_X18_Y4_N30 cyclonev_lcell_comb \ShiftLeft0~0 ( // Equation(s): -// \ShiftLeft0~0_combout = (!\C[1]~input_o & ((!\C[0]~input_o & (\A[1]~input_o )) # (\C[0]~input_o & ((\A[0]~input_o ))))) +// \ShiftLeft0~0_combout = ( \A[1]~input_o & ( (!\C[1]~input_o & ((!\C[0]~input_o ) # (\A[0]~input_o ))) ) ) # ( !\A[1]~input_o & ( (\C[0]~input_o & (!\C[1]~input_o & \A[0]~input_o )) ) ) .dataa(!\C[0]~input_o ), - .datab(!\C[1]~input_o ), - .datac(!\A[1]~input_o ), + .datab(gnd), + .datac(!\C[1]~input_o ), .datad(!\A[0]~input_o ), .datae(gnd), - .dataf(gnd), + .dataf(!\A[1]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -714,22 +663,47 @@ cyclonev_lcell_comb \ShiftLeft0~0 ( .shareout()); // synopsys translate_off defparam \ShiftLeft0~0 .extended_lut = "off"; -defparam \ShiftLeft0~0 .lut_mask = 64'h084C084C084C084C; +defparam \ShiftLeft0~0 .lut_mask = 64'h00500050A0F0A0F0; defparam \ShiftLeft0~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N15 +// Location: LABCELL_X18_Y4_N0 +cyclonev_lcell_comb \ShiftRight2~1 ( +// Equation(s): +// \ShiftRight2~1_combout = ( \A[3]~input_o & ( \B[0]~input_o & ( (!\B[1]~input_o & (!\ShiftLeft1~0_combout & \A[2]~input_o )) ) ) ) # ( !\A[3]~input_o & ( \B[0]~input_o & ( (!\B[1]~input_o & (!\ShiftLeft1~0_combout & \A[2]~input_o )) ) ) ) # ( +// \A[3]~input_o & ( !\B[0]~input_o & ( (!\ShiftLeft1~0_combout & ((\B[1]~input_o ) # (\A[1]~input_o ))) ) ) ) # ( !\A[3]~input_o & ( !\B[0]~input_o & ( (\A[1]~input_o & (!\B[1]~input_o & !\ShiftLeft1~0_combout )) ) ) ) + + .dataa(!\A[1]~input_o ), + .datab(!\B[1]~input_o ), + .datac(!\ShiftLeft1~0_combout ), + .datad(!\A[2]~input_o ), + .datae(!\A[3]~input_o ), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight2~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight2~1 .extended_lut = "off"; +defparam \ShiftRight2~1 .lut_mask = 64'h4040707000C000C0; +defparam \ShiftRight2~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N57 cyclonev_lcell_comb \ShiftRight0~1 ( // Equation(s): -// \ShiftRight0~1_combout = ( \A[2]~input_o & ( (!\C[0]~input_o & ((!\C[1]~input_o & (\A[1]~input_o )) # (\C[1]~input_o & ((\A[3]~input_o ))))) # (\C[0]~input_o & (((!\C[1]~input_o )))) ) ) # ( !\A[2]~input_o & ( (!\C[0]~input_o & ((!\C[1]~input_o & -// (\A[1]~input_o )) # (\C[1]~input_o & ((\A[3]~input_o ))))) ) ) +// \ShiftRight0~1_combout = ( \A[1]~input_o & ( (!\C[0]~input_o & (((!\C[1]~input_o )) # (\A[3]~input_o ))) # (\C[0]~input_o & (((\A[2]~input_o & !\C[1]~input_o )))) ) ) # ( !\A[1]~input_o & ( (!\C[0]~input_o & (\A[3]~input_o & ((\C[1]~input_o )))) # +// (\C[0]~input_o & (((\A[2]~input_o & !\C[1]~input_o )))) ) ) - .dataa(!\C[0]~input_o ), - .datab(!\A[1]~input_o ), - .datac(!\C[1]~input_o ), - .datad(!\A[3]~input_o ), + .dataa(!\A[3]~input_o ), + .datab(!\C[0]~input_o ), + .datac(!\A[2]~input_o ), + .datad(!\C[1]~input_o ), .datae(gnd), - .dataf(!\A[2]~input_o ), + .dataf(!\A[1]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -739,22 +713,21 @@ cyclonev_lcell_comb \ShiftRight0~1 ( .shareout()); // synopsys translate_off defparam \ShiftRight0~1 .extended_lut = "off"; -defparam \ShiftRight0~1 .lut_mask = 64'h202A202A707A707A; +defparam \ShiftRight0~1 .lut_mask = 64'h03440344CF44CF44; defparam \ShiftRight0~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N30 +// Location: LABCELL_X18_Y4_N36 cyclonev_lcell_comb \Mux2~0 ( // Equation(s): -// \Mux2~0_combout = ( \ShiftRight0~1_combout & ( \op[2]~input_o & ( (!\op[0]~input_o & (\ShiftLeft1~1_combout )) # (\op[0]~input_o & ((\ShiftRight2~1_combout ))) ) ) ) # ( !\ShiftRight0~1_combout & ( \op[2]~input_o & ( (!\op[0]~input_o & -// (\ShiftLeft1~1_combout )) # (\op[0]~input_o & ((\ShiftRight2~1_combout ))) ) ) ) # ( \ShiftRight0~1_combout & ( !\op[2]~input_o & ( (\ShiftLeft0~0_combout ) # (\op[0]~input_o ) ) ) ) # ( !\ShiftRight0~1_combout & ( !\op[2]~input_o & ( -// (!\op[0]~input_o & \ShiftLeft0~0_combout ) ) ) ) +// \Mux2~0_combout = ( \op[0]~input_o & ( \op[2]~input_o & ( \ShiftRight2~1_combout ) ) ) # ( !\op[0]~input_o & ( \op[2]~input_o & ( \ShiftLeft1~1_combout ) ) ) # ( \op[0]~input_o & ( !\op[2]~input_o & ( \ShiftRight0~1_combout ) ) ) # ( +// !\op[0]~input_o & ( !\op[2]~input_o & ( \ShiftLeft0~0_combout ) ) ) .dataa(!\ShiftLeft1~1_combout ), - .datab(!\op[0]~input_o ), + .datab(!\ShiftLeft0~0_combout ), .datac(!\ShiftRight2~1_combout ), - .datad(!\ShiftLeft0~0_combout ), - .datae(!\ShiftRight0~1_combout ), + .datad(!\ShiftRight0~1_combout ), + .datae(!\op[0]~input_o ), .dataf(!\op[2]~input_o ), .datag(gnd), .cin(gnd), @@ -765,21 +738,45 @@ cyclonev_lcell_comb \Mux2~0 ( .shareout()); // synopsys translate_off defparam \Mux2~0 .extended_lut = "off"; -defparam \Mux2~0 .lut_mask = 64'h00CC33FF47474747; +defparam \Mux2~0 .lut_mask = 64'h333300FF55550F0F; defparam \Mux2~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N36 +// Location: LABCELL_X18_Y4_N48 +cyclonev_lcell_comb \Mux2~4 ( +// Equation(s): +// \Mux2~4_combout = ( \C[0]~input_o & ( (\A[1]~input_o & !\op[0]~input_o ) ) ) # ( !\C[0]~input_o & ( (\A[1]~input_o & ((!\op[0]~input_o ) # ((!\op[2]~input_o & !\C[1]~input_o )))) ) ) + + .dataa(!\A[1]~input_o ), + .datab(!\op[2]~input_o ), + .datac(!\C[1]~input_o ), + .datad(!\op[0]~input_o ), + .datae(gnd), + .dataf(!\C[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux2~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux2~4 .extended_lut = "off"; +defparam \Mux2~4 .lut_mask = 64'h5540554055005500; +defparam \Mux2~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X18_Y4_N18 cyclonev_lcell_comb \Mux2~5 ( // Equation(s): -// \Mux2~5_combout = ( \Mux2~0_combout & ( (!\op[1]~input_o ) # (((\op[0]~input_o & \Mux2~3_combout )) # (\Mux2~4_combout )) ) ) # ( !\Mux2~0_combout & ( (\op[1]~input_o & (((\op[0]~input_o & \Mux2~3_combout )) # (\Mux2~4_combout ))) ) ) +// \Mux2~5_combout = ( \Mux2~4_combout & ( (\Mux2~0_combout ) # (\op[1]~input_o ) ) ) # ( !\Mux2~4_combout & ( (!\op[1]~input_o & (((\Mux2~0_combout )))) # (\op[1]~input_o & (\op[0]~input_o & (\Mux2~3_combout ))) ) ) .dataa(!\op[1]~input_o ), - .datab(!\Mux2~4_combout ), - .datac(!\op[0]~input_o ), - .datad(!\Mux2~3_combout ), + .datab(!\op[0]~input_o ), + .datac(!\Mux2~3_combout ), + .datad(!\Mux2~0_combout ), .datae(gnd), - .dataf(!\Mux2~0_combout ), + .dataf(!\Mux2~4_combout ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -789,20 +786,20 @@ cyclonev_lcell_comb \Mux2~5 ( .shareout()); // synopsys translate_off defparam \Mux2~5 .extended_lut = "off"; -defparam \Mux2~5 .lut_mask = 64'h11151115BBBFBBBF; +defparam \Mux2~5 .lut_mask = 64'h01AB01AB55FF55FF; defparam \Mux2~5 .shared_arith = "off"; // synopsys translate_on // Location: MLABCELL_X19_Y4_N42 cyclonev_lcell_comb \Mux1~1 ( // Equation(s): -// \Mux1~1_combout = ( \A[2]~input_o & ( \A[3]~input_o ) ) # ( !\A[2]~input_o & ( \A[3]~input_o & ( (\op[0]~input_o & ((!\op[2]~input_o & ((!\ShiftRight0~0_combout ))) # (\op[2]~input_o & (!\ShiftRight2~0_combout )))) ) ) ) # ( \A[2]~input_o & ( -// !\A[3]~input_o & ( (!\op[0]~input_o ) # ((!\op[2]~input_o & ((\ShiftRight0~0_combout ))) # (\op[2]~input_o & (\ShiftRight2~0_combout ))) ) ) ) +// \Mux1~1_combout = ( \A[2]~input_o & ( \A[3]~input_o ) ) # ( !\A[2]~input_o & ( \A[3]~input_o & ( (\op[0]~input_o & ((!\op[2]~input_o & (!\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\ShiftRight2~0_combout ))))) ) ) ) # ( \A[2]~input_o & ( +// !\A[3]~input_o & ( (!\op[0]~input_o ) # ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((\ShiftRight2~0_combout )))) ) ) ) - .dataa(!\ShiftRight2~0_combout ), + .dataa(!\op[2]~input_o ), .datab(!\op[0]~input_o ), .datac(!\ShiftRight0~0_combout ), - .datad(!\op[2]~input_o ), + .datad(!\ShiftRight2~0_combout ), .datae(!\A[2]~input_o ), .dataf(!\A[3]~input_o ), .datag(gnd), @@ -814,20 +811,44 @@ cyclonev_lcell_comb \Mux1~1 ( .shareout()); // synopsys translate_off defparam \Mux1~1 .extended_lut = "off"; -defparam \Mux1~1 .lut_mask = 64'h0000CFDD3022FFFF; +defparam \Mux1~1 .lut_mask = 64'h0000CEDF3120FFFF; defparam \Mux1~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N51 +// Location: MLABCELL_X19_Y4_N54 +cyclonev_lcell_comb \ShiftRight0~2 ( +// Equation(s): +// \ShiftRight0~2_combout = ( \C[0]~input_o & ( (\A[3]~input_o & !\C[1]~input_o ) ) ) # ( !\C[0]~input_o & ( (!\C[1]~input_o & \A[2]~input_o ) ) ) + + .dataa(!\A[3]~input_o ), + .datab(gnd), + .datac(!\C[1]~input_o ), + .datad(!\A[2]~input_o ), + .datae(gnd), + .dataf(!\C[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight0~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight0~2 .extended_lut = "off"; +defparam \ShiftRight0~2 .lut_mask = 64'h00F000F050505050; +defparam \ShiftRight0~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X18_Y4_N57 cyclonev_lcell_comb \ShiftRight2~2 ( // Equation(s): -// \ShiftRight2~2_combout = ( \A[3]~input_o & ( \A[2]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & !\B[2]~input_o )) ) ) ) # ( !\A[3]~input_o & ( \A[2]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & (!\B[2]~input_o & !\B[0]~input_o ))) ) ) ) # -// ( \A[3]~input_o & ( !\A[2]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & (!\B[2]~input_o & \B[0]~input_o ))) ) ) ) +// \ShiftRight2~2_combout = ( \A[3]~input_o & ( \A[2]~input_o & ( (!\B[2]~input_o & (!\B[1]~input_o & !\B[3]~input_o )) ) ) ) # ( !\A[3]~input_o & ( \A[2]~input_o & ( (!\B[2]~input_o & (!\B[1]~input_o & (!\B[0]~input_o & !\B[3]~input_o ))) ) ) ) # +// ( \A[3]~input_o & ( !\A[2]~input_o & ( (!\B[2]~input_o & (!\B[1]~input_o & (\B[0]~input_o & !\B[3]~input_o ))) ) ) ) - .dataa(!\B[3]~input_o ), + .dataa(!\B[2]~input_o ), .datab(!\B[1]~input_o ), - .datac(!\B[2]~input_o ), - .datad(!\B[0]~input_o ), + .datac(!\B[0]~input_o ), + .datad(!\B[3]~input_o ), .datae(!\A[3]~input_o ), .dataf(!\A[2]~input_o ), .datag(gnd), @@ -839,47 +860,21 @@ cyclonev_lcell_comb \ShiftRight2~2 ( .shareout()); // synopsys translate_off defparam \ShiftRight2~2 .extended_lut = "off"; -defparam \ShiftRight2~2 .lut_mask = 64'h0000008080008080; +defparam \ShiftRight2~2 .lut_mask = 64'h0000080080008800; defparam \ShiftRight2~2 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N9 -cyclonev_lcell_comb \ShiftLeft0~1 ( -// Equation(s): -// \ShiftLeft0~1_combout = ( \A[2]~input_o & ( (!\C[0]~input_o & ((!\C[1]~input_o ) # ((\A[0]~input_o )))) # (\C[0]~input_o & (!\C[1]~input_o & (\A[1]~input_o ))) ) ) # ( !\A[2]~input_o & ( (!\C[0]~input_o & (\C[1]~input_o & ((\A[0]~input_o )))) # -// (\C[0]~input_o & (!\C[1]~input_o & (\A[1]~input_o ))) ) ) - - .dataa(!\C[0]~input_o ), - .datab(!\C[1]~input_o ), - .datac(!\A[1]~input_o ), - .datad(!\A[0]~input_o ), - .datae(gnd), - .dataf(!\A[2]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft0~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft0~1 .extended_lut = "off"; -defparam \ShiftLeft0~1 .lut_mask = 64'h042604268CAE8CAE; -defparam \ShiftLeft0~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X21_Y4_N18 +// Location: MLABCELL_X19_Y4_N30 cyclonev_lcell_comb \ShiftLeft1~2 ( // Equation(s): -// \ShiftLeft1~2_combout = ( \B[0]~input_o & ( \A[2]~input_o & ( (!\ShiftLeft1~0_combout & (!\B[1]~input_o & \A[1]~input_o )) ) ) ) # ( !\B[0]~input_o & ( \A[2]~input_o & ( (!\ShiftLeft1~0_combout & ((!\B[1]~input_o ) # (\A[0]~input_o ))) ) ) ) # ( -// \B[0]~input_o & ( !\A[2]~input_o & ( (!\ShiftLeft1~0_combout & (!\B[1]~input_o & \A[1]~input_o )) ) ) ) # ( !\B[0]~input_o & ( !\A[2]~input_o & ( (!\ShiftLeft1~0_combout & (\B[1]~input_o & \A[0]~input_o )) ) ) ) +// \ShiftLeft1~2_combout = ( !\ShiftLeft1~0_combout & ( \B[1]~input_o & ( (\A[0]~input_o & !\B[0]~input_o ) ) ) ) # ( !\ShiftLeft1~0_combout & ( !\B[1]~input_o & ( (!\B[0]~input_o & ((\A[2]~input_o ))) # (\B[0]~input_o & (\A[1]~input_o )) ) ) ) - .dataa(!\ShiftLeft1~0_combout ), - .datab(!\B[1]~input_o ), + .dataa(!\A[0]~input_o ), + .datab(!\B[0]~input_o ), .datac(!\A[1]~input_o ), - .datad(!\A[0]~input_o ), - .datae(!\B[0]~input_o ), - .dataf(!\A[2]~input_o ), + .datad(!\A[2]~input_o ), + .datae(!\ShiftLeft1~0_combout ), + .dataf(!\B[1]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -889,47 +884,48 @@ cyclonev_lcell_comb \ShiftLeft1~2 ( .shareout()); // synopsys translate_off defparam \ShiftLeft1~2 .extended_lut = "off"; -defparam \ShiftLeft1~2 .lut_mask = 64'h0022080888AA0808; +defparam \ShiftLeft1~2 .lut_mask = 64'h03CF000044440000; defparam \ShiftLeft1~2 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N45 -cyclonev_lcell_comb \ShiftRight0~2 ( +// Location: MLABCELL_X19_Y4_N39 +cyclonev_lcell_comb \ShiftLeft0~1 ( // Equation(s): -// \ShiftRight0~2_combout = ( \A[2]~input_o & ( (!\C[1]~input_o & ((!\C[0]~input_o ) # (\A[3]~input_o ))) ) ) # ( !\A[2]~input_o & ( (\A[3]~input_o & (!\C[1]~input_o & \C[0]~input_o )) ) ) +// \ShiftLeft0~1_combout = ( \A[1]~input_o & ( (!\C[1]~input_o & (((\A[2]~input_o )) # (\C[0]~input_o ))) # (\C[1]~input_o & (!\C[0]~input_o & ((\A[0]~input_o )))) ) ) # ( !\A[1]~input_o & ( (!\C[0]~input_o & ((!\C[1]~input_o & (\A[2]~input_o )) # +// (\C[1]~input_o & ((\A[0]~input_o ))))) ) ) - .dataa(gnd), - .datab(!\A[3]~input_o ), - .datac(!\C[1]~input_o ), - .datad(!\C[0]~input_o ), + .dataa(!\C[1]~input_o ), + .datab(!\C[0]~input_o ), + .datac(!\A[2]~input_o ), + .datad(!\A[0]~input_o ), .datae(gnd), - .dataf(!\A[2]~input_o ), + .dataf(!\A[1]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\ShiftRight0~2_combout ), + .combout(\ShiftLeft0~1_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \ShiftRight0~2 .extended_lut = "off"; -defparam \ShiftRight0~2 .lut_mask = 64'h00300030F030F030; -defparam \ShiftRight0~2 .shared_arith = "off"; +defparam \ShiftLeft0~1 .extended_lut = "off"; +defparam \ShiftLeft0~1 .lut_mask = 64'h084C084C2A6E2A6E; +defparam \ShiftLeft0~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N24 +// Location: MLABCELL_X19_Y4_N6 cyclonev_lcell_comb \Mux1~0 ( // Equation(s): -// \Mux1~0_combout = ( \ShiftRight0~2_combout & ( \op[2]~input_o & ( (!\op[0]~input_o & ((\ShiftLeft1~2_combout ))) # (\op[0]~input_o & (\ShiftRight2~2_combout )) ) ) ) # ( !\ShiftRight0~2_combout & ( \op[2]~input_o & ( (!\op[0]~input_o & -// ((\ShiftLeft1~2_combout ))) # (\op[0]~input_o & (\ShiftRight2~2_combout )) ) ) ) # ( \ShiftRight0~2_combout & ( !\op[2]~input_o & ( (\op[0]~input_o ) # (\ShiftLeft0~1_combout ) ) ) ) # ( !\ShiftRight0~2_combout & ( !\op[2]~input_o & ( -// (\ShiftLeft0~1_combout & !\op[0]~input_o ) ) ) ) +// \Mux1~0_combout = ( \op[2]~input_o & ( \ShiftLeft0~1_combout & ( (!\op[0]~input_o & ((\ShiftLeft1~2_combout ))) # (\op[0]~input_o & (\ShiftRight2~2_combout )) ) ) ) # ( !\op[2]~input_o & ( \ShiftLeft0~1_combout & ( (!\op[0]~input_o ) # +// (\ShiftRight0~2_combout ) ) ) ) # ( \op[2]~input_o & ( !\ShiftLeft0~1_combout & ( (!\op[0]~input_o & ((\ShiftLeft1~2_combout ))) # (\op[0]~input_o & (\ShiftRight2~2_combout )) ) ) ) # ( !\op[2]~input_o & ( !\ShiftLeft0~1_combout & ( +// (\ShiftRight0~2_combout & \op[0]~input_o ) ) ) ) - .dataa(!\ShiftRight2~2_combout ), - .datab(!\ShiftLeft0~1_combout ), - .datac(!\ShiftLeft1~2_combout ), - .datad(!\op[0]~input_o ), - .datae(!\ShiftRight0~2_combout ), - .dataf(!\op[2]~input_o ), + .dataa(!\ShiftRight0~2_combout ), + .datab(!\op[0]~input_o ), + .datac(!\ShiftRight2~2_combout ), + .datad(!\ShiftLeft1~2_combout ), + .datae(!\op[2]~input_o ), + .dataf(!\ShiftLeft0~1_combout ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -939,17 +935,17 @@ cyclonev_lcell_comb \Mux1~0 ( .shareout()); // synopsys translate_off defparam \Mux1~0 .extended_lut = "off"; -defparam \Mux1~0 .lut_mask = 64'h330033FF0F550F55; +defparam \Mux1~0 .lut_mask = 64'h111103CFDDDD03CF; defparam \Mux1~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N39 +// Location: MLABCELL_X19_Y4_N51 cyclonev_lcell_comb \Mux1~2 ( // Equation(s): // \Mux1~2_combout = ( \Mux1~0_combout & ( (!\op[1]~input_o ) # (\Mux1~1_combout ) ) ) # ( !\Mux1~0_combout & ( (\op[1]~input_o & \Mux1~1_combout ) ) ) - .dataa(!\op[1]~input_o ), - .datab(gnd), + .dataa(gnd), + .datab(!\op[1]~input_o ), .datac(!\Mux1~1_combout ), .datad(gnd), .datae(gnd), @@ -963,35 +959,36 @@ cyclonev_lcell_comb \Mux1~2 ( .shareout()); // synopsys translate_off defparam \Mux1~2 .extended_lut = "off"; -defparam \Mux1~2 .lut_mask = 64'h05050505AFAFAFAF; +defparam \Mux1~2 .lut_mask = 64'h03030303CFCFCFCF; defparam \Mux1~2 .shared_arith = "off"; // synopsys translate_on // Location: MLABCELL_X19_Y4_N27 -cyclonev_lcell_comb \ShiftRight0~3 ( +cyclonev_lcell_comb \ShiftLeft1~3 ( // Equation(s): -// \ShiftRight0~3_combout = ( \A[3]~input_o & ( (!\C[0]~input_o & !\C[1]~input_o ) ) ) +// \ShiftLeft1~3_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[2]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o & +// ( \A[3]~input_o ) ) ) - .dataa(!\C[0]~input_o ), - .datab(gnd), - .datac(!\C[1]~input_o ), - .datad(gnd), - .datae(gnd), - .dataf(!\A[3]~input_o ), + .dataa(!\A[1]~input_o ), + .datab(!\A[0]~input_o ), + .datac(!\A[2]~input_o ), + .datad(!\A[3]~input_o ), + .datae(!\B[1]~input_o ), + .dataf(!\B[0]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\ShiftRight0~3_combout ), + .combout(\ShiftLeft1~3_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \ShiftRight0~3 .extended_lut = "off"; -defparam \ShiftRight0~3 .lut_mask = 64'h00000000A0A0A0A0; -defparam \ShiftRight0~3 .shared_arith = "off"; +defparam \ShiftLeft1~3 .extended_lut = "off"; +defparam \ShiftLeft1~3 .lut_mask = 64'h00FF55550F0F3333; +defparam \ShiftLeft1~3 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X21_Y4_N42 +// Location: LABCELL_X18_Y4_N15 cyclonev_lcell_comb \ShiftRight2~3 ( // Equation(s): // \ShiftRight2~3_combout = ( !\B[3]~input_o & ( (!\B[2]~input_o & (\A[3]~input_o & (!\B[0]~input_o & !\B[1]~input_o ))) ) ) @@ -1015,41 +1012,40 @@ defparam \ShiftRight2~3 .lut_mask = 64'h2000200000000000; defparam \ShiftRight2~3 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X19_Y4_N51 -cyclonev_lcell_comb \ShiftLeft1~3 ( +// Location: MLABCELL_X19_Y4_N15 +cyclonev_lcell_comb \ShiftRight0~3 ( // Equation(s): -// \ShiftLeft1~3_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[2]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o & -// ( \A[3]~input_o ) ) ) +// \ShiftRight0~3_combout = ( \A[3]~input_o & ( (!\C[0]~input_o & !\C[1]~input_o ) ) ) - .dataa(!\A[0]~input_o ), - .datab(!\A[2]~input_o ), - .datac(!\A[1]~input_o ), - .datad(!\A[3]~input_o ), - .datae(!\B[1]~input_o ), - .dataf(!\B[0]~input_o ), + .dataa(!\C[0]~input_o ), + .datab(gnd), + .datac(gnd), + .datad(!\C[1]~input_o ), + .datae(gnd), + .dataf(!\A[3]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\ShiftLeft1~3_combout ), + .combout(\ShiftRight0~3_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \ShiftLeft1~3 .extended_lut = "off"; -defparam \ShiftLeft1~3 .lut_mask = 64'h00FF0F0F33335555; -defparam \ShiftLeft1~3 .shared_arith = "off"; +defparam \ShiftRight0~3 .extended_lut = "off"; +defparam \ShiftRight0~3 .lut_mask = 64'h00000000AA00AA00; +defparam \ShiftRight0~3 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X19_Y4_N48 +// Location: MLABCELL_X19_Y4_N24 cyclonev_lcell_comb \ShiftLeft0~2 ( // Equation(s): // \ShiftLeft0~2_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[2]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o & // ( \A[3]~input_o ) ) ) - .dataa(!\A[0]~input_o ), - .datab(!\A[2]~input_o ), + .dataa(!\A[1]~input_o ), + .datab(!\A[0]~input_o ), .datac(!\A[3]~input_o ), - .datad(!\A[1]~input_o ), + .datad(!\A[2]~input_o ), .datae(!\C[1]~input_o ), .dataf(!\C[0]~input_o ), .datag(gnd), @@ -1061,22 +1057,22 @@ cyclonev_lcell_comb \ShiftLeft0~2 ( .shareout()); // synopsys translate_off defparam \ShiftLeft0~2 .extended_lut = "off"; -defparam \ShiftLeft0~2 .lut_mask = 64'h0F0F00FF33335555; +defparam \ShiftLeft0~2 .lut_mask = 64'h0F0F555500FF3333; defparam \ShiftLeft0~2 .shared_arith = "off"; // synopsys translate_on // Location: MLABCELL_X19_Y4_N0 cyclonev_lcell_comb \Mux0~2 ( // Equation(s): -// \Mux0~2_combout = ( !\op[2]~input_o & ( (!\op[0]~input_o & (((\ShiftLeft0~2_combout )))) # (\op[0]~input_o & (\ShiftRight0~3_combout )) ) ) # ( \op[2]~input_o & ( ((!\op[0]~input_o & (!\ShiftLeft1~0_combout & ((\ShiftLeft1~3_combout )))) # -// (\op[0]~input_o & (((\ShiftRight2~3_combout ))))) ) ) +// \Mux0~2_combout = ( !\op[2]~input_o & ( ((!\op[0]~input_o & (\ShiftLeft0~2_combout )) # (\op[0]~input_o & (((\ShiftRight0~3_combout ))))) ) ) # ( \op[2]~input_o & ( (!\op[0]~input_o & (\ShiftLeft1~3_combout & (!\ShiftLeft1~0_combout ))) # +// (\op[0]~input_o & ((((\ShiftRight2~3_combout ))))) ) ) - .dataa(!\ShiftRight0~3_combout ), + .dataa(!\ShiftLeft1~3_combout ), .datab(!\op[0]~input_o ), .datac(!\ShiftLeft1~0_combout ), .datad(!\ShiftRight2~3_combout ), .datae(!\op[2]~input_o ), - .dataf(!\ShiftLeft1~3_combout ), + .dataf(!\ShiftRight0~3_combout ), .datag(!\ShiftLeft0~2_combout ), .cin(gnd), .sharein(gnd), @@ -1086,19 +1082,19 @@ cyclonev_lcell_comb \Mux0~2 ( .shareout()); // synopsys translate_off defparam \Mux0~2 .extended_lut = "on"; -defparam \Mux0~2 .lut_mask = 64'h1D1D00331D1DC0F3; +defparam \Mux0~2 .lut_mask = 64'h0C0C40733F3F4073; defparam \Mux0~2 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X19_Y4_N24 +// Location: MLABCELL_X19_Y4_N48 cyclonev_lcell_comb \Mux0~1 ( // Equation(s): -// \Mux0~1_combout = ( \A[3]~input_o & ( (\op[1]~input_o ) # (\Mux0~2_combout ) ) ) # ( !\A[3]~input_o & ( (\Mux0~2_combout & !\op[1]~input_o ) ) ) +// \Mux0~1_combout = ( \A[3]~input_o & ( (\Mux0~2_combout ) # (\op[1]~input_o ) ) ) # ( !\A[3]~input_o & ( (!\op[1]~input_o & \Mux0~2_combout ) ) ) .dataa(gnd), - .datab(gnd), + .datab(!\op[1]~input_o ), .datac(!\Mux0~2_combout ), - .datad(!\op[1]~input_o ), + .datad(gnd), .datae(gnd), .dataf(!\A[3]~input_o ), .datag(gnd), @@ -1110,11 +1106,11 @@ cyclonev_lcell_comb \Mux0~1 ( .shareout()); // synopsys translate_off defparam \Mux0~1 .extended_lut = "off"; -defparam \Mux0~1 .lut_mask = 64'h0F000F000FFF0FFF; +defparam \Mux0~1 .lut_mask = 64'h0C0C0C0C3F3F3F3F; defparam \Mux0~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X41_Y51_N0 +// Location: LABCELL_X43_Y60_N0 cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( // Equation(s): diff --git a/Quartus/A1_Q5/db/A1_Q5.quiproj.2570.rdr.flock b/Quartus/A1_Q6/db/A1_Q6.quiproj.2570.rdr.flock similarity index 100% rename from Quartus/A1_Q5/db/A1_Q5.quiproj.2570.rdr.flock rename to Quartus/A1_Q6/db/A1_Q6.quiproj.2570.rdr.flock diff --git a/Quartus/A1_Q6/db/instruction_classifier.asm.qmsg b/Quartus/A1_Q6/db/instruction_classifier.asm.qmsg index 9997d09..59e0b52 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.asm.qmsg +++ b/Quartus/A1_Q6/db/instruction_classifier.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431609040 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431609041 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:20:08 2026 " "Processing started: Tue Sep 15 10:20:08 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431609041 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789431609041 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789431609041 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789431609707 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789431614462 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "517 " "Peak virtual memory: 517 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431614674 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:14 2026 " "Processing ended: Tue Sep 15 10:20:14 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431614674 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431614674 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431614674 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789431614674 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789466242665 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789466242666 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:57:22 2026 " "Processing started: Tue Sep 15 19:57:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789466242666 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789466242666 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789466242666 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789466243313 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789466247576 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "513 " "Peak virtual memory: 513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466247773 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:57:27 2026 " "Processing ended: Tue Sep 15 19:57:27 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466247773 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466247773 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466247773 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789466247773 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.asm.rdb b/Quartus/A1_Q6/db/instruction_classifier.asm.rdb index 8d91463..d0055bb 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.asm.rdb and b/Quartus/A1_Q6/db/instruction_classifier.asm.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.bpm b/Quartus/A1_Q6/db/instruction_classifier.cmp.bpm index b01b807..fdc5f95 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.cmp.bpm and b/Quartus/A1_Q6/db/instruction_classifier.cmp.bpm differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.cdb b/Quartus/A1_Q6/db/instruction_classifier.cmp.cdb index 1022264..0b6a136 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.cmp.cdb and b/Quartus/A1_Q6/db/instruction_classifier.cmp.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.hdb b/Quartus/A1_Q6/db/instruction_classifier.cmp.hdb index 12ac6ff..392490c 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.cmp.hdb and b/Quartus/A1_Q6/db/instruction_classifier.cmp.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.idb b/Quartus/A1_Q6/db/instruction_classifier.cmp.idb index 8a5f867..d6e194f 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.cmp.idb and b/Quartus/A1_Q6/db/instruction_classifier.cmp.idb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.logdb b/Quartus/A1_Q6/db/instruction_classifier.cmp.logdb index 91492ef..481d072 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.cmp.logdb +++ b/Quartus/A1_Q6/db/instruction_classifier.cmp.logdb @@ -1,11 +1,11 @@ v1 IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, -IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, -IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, @@ -29,25 +29,25 @@ IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, -IO_RULES_MATRIX,Total Pass,0;0;0;0;0;13;0;0;0;0;0;0;0;7;0;0;0;0;7;0;0;0;0;7;0;13;13;0, +IO_RULES_MATRIX,Total Pass,0;13;13;0;0;13;13;0;0;0;0;0;0;7;0;0;0;0;7;0;0;0;0;7;0;13;13;0, IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,13;13;13;13;13;0;13;13;13;13;13;13;13;6;13;13;13;13;6;13;13;13;13;6;13;0;0;13, +IO_RULES_MATRIX,Total Inapplicable,13;0;0;13;13;0;0;13;13;13;13;13;13;6;13;13;13;13;6;13;13;13;13;6;13;0;0;13, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,R[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,J[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B2[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,I[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,F[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,M[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,R[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,J[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B2[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,I[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,F[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,M[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_SUMMARY,Total I/O Rules,28, -IO_RULES_SUMMARY,Number of I/O Rules Passed,6, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, IO_RULES_SUMMARY,Number of I/O Rules Failed,0, IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, -IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19, diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.rdb b/Quartus/A1_Q6/db/instruction_classifier.cmp.rdb index 4105755..67af058 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.cmp.rdb and b/Quartus/A1_Q6/db/instruction_classifier.cmp.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_0c_fast.hsd index b19b6d1..5b25938 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_0c_fast.hsd and b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_85c_slow.hsd index 118df22..0778662 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_85c_slow.hsd and b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.db_info b/Quartus/A1_Q6/db/instruction_classifier.db_info index 50b2afb..94c2229 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.db_info +++ b/Quartus/A1_Q6/db/instruction_classifier.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Tue Sep 15 10:09:43 2026 +Creation_Time = Tue Sep 15 19:51:34 2026 diff --git a/Quartus/A1_Q6/db/instruction_classifier.eda.qmsg b/Quartus/A1_Q6/db/instruction_classifier.eda.qmsg index 9ed811b..16dc494 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.eda.qmsg +++ b/Quartus/A1_Q6/db/instruction_classifier.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431623036 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431623037 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:20:22 2026 " "Processing started: Tue Sep 15 10:20:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431623037 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789431623037 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789431623037 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789431623815 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "instruction_classifier.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/ simulation " "Generated file instruction_classifier.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789431623880 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "659 " "Peak virtual memory: 659 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431623914 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:23 2026 " "Processing ended: Tue Sep 15 10:20:23 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431623914 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431623914 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431623914 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789431623914 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789466256073 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789466256073 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:57:35 2026 " "Processing started: Tue Sep 15 19:57:35 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789466256073 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789466256073 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789466256074 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789466256787 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "instruction_classifier.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/ simulation " "Generated file instruction_classifier.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789466256843 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466256879 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:57:36 2026 " "Processing ended: Tue Sep 15 19:57:36 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466256879 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466256879 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466256879 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789466256879 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.fit.qmsg b/Quartus/A1_Q6/db/instruction_classifier.fit.qmsg index ec2f020..db8df88 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.fit.qmsg +++ b/Quartus/A1_Q6/db/instruction_classifier.fit.qmsg @@ -1,44 +1,44 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789431575376 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789431575377 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "instruction_classifier 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"instruction_classifier\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789431575381 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789431575456 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789431575456 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789431575888 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789431575916 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789431575969 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "13 13 " "No exact pin location assignment(s) for 13 pins of 13 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789431576256 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789431583219 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431583296 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789431583298 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789431583299 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789431583299 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789431583299 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789431583299 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789431583299 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789431583299 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789431583300 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789431583300 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431583313 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789431589563 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789431589563 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789431589564 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789431589564 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789431589565 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789431589565 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789431589566 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789431589568 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789431589608 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:04 " "Fitter placement preparation operations ending: elapsed time is 00:00:04" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431593856 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789431595048 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789431595350 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431595351 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789431596250 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789431601801 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789431601801 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789431602005 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789431602005 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789431602005 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431602007 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789431602821 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789431602862 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789431603215 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789431603215 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789431603872 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431606547 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1369 " "Peak virtual memory: 1369 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431607368 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:07 2026 " "Processing ended: Tue Sep 15 10:20:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431607368 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:33 " "Elapsed time: 00:00:33" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431607368 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:49 " "Total CPU time (on all processors): 00:00:49" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431607368 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789431607368 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789466213525 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789466213525 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "instruction_classifier 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"instruction_classifier\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789466213530 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789466213605 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789466213605 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789466214029 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789466214056 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789466214110 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789466220964 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466220984 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789466220988 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789466220988 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789466220988 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789466220989 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789466220989 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789466220989 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789466220989 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789466220990 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789466220990 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466221008 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789466226868 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789466226868 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789466226869 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789466226869 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789466226870 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789466226870 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789466226870 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789466226873 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789466226960 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466227589 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789466227836 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789466228131 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466228132 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789466229079 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y49 X22_Y61 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y49 to location X22_Y61" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y49 to location X22_Y61"} { { 12 { 0 ""} 11 49 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789466235040 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789466235040 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789466235271 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789466235271 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789466235271 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466235273 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789466236216 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789466236248 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789466236603 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789466236603 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789466237318 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466239936 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789466240231 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1384 " "Peak virtual memory: 1384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466240779 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:57:20 2026 " "Processing ended: Tue Sep 15 19:57:20 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466240779 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466240779 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466240779 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789466240779 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.hier_info b/Quartus/A1_Q6/db/instruction_classifier.hier_info index bb9d567..5c26c86 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.hier_info +++ b/Quartus/A1_Q6/db/instruction_classifier.hier_info @@ -26,12 +26,12 @@ op[5] => Equal2.IN1 op[5] => Equal3.IN1 op[5] => Equal4.IN1 op[5] => Equal5.IN1 -R[0] <= Equal0.DB_MAX_OUTPUT_PORT_TYPE -B1[0] <= Equal1.DB_MAX_OUTPUT_PORT_TYPE -J[0] <= Equal2.DB_MAX_OUTPUT_PORT_TYPE -B2[0] <= Equal3.DB_MAX_OUTPUT_PORT_TYPE -I[0] <= Equal4.DB_MAX_OUTPUT_PORT_TYPE -F[0] <= Equal5.DB_MAX_OUTPUT_PORT_TYPE -M[0] <= op[5].DB_MAX_OUTPUT_PORT_TYPE +R[0] << Equal0.DB_MAX_OUTPUT_PORT_TYPE +B1[0] << Equal1.DB_MAX_OUTPUT_PORT_TYPE +J[0] << Equal2.DB_MAX_OUTPUT_PORT_TYPE +B2[0] << Equal3.DB_MAX_OUTPUT_PORT_TYPE +I[0] << Equal4.DB_MAX_OUTPUT_PORT_TYPE +F[0] << Equal5.DB_MAX_OUTPUT_PORT_TYPE +M[0] << op[5].DB_MAX_OUTPUT_PORT_TYPE diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.bpm b/Quartus/A1_Q6/db/instruction_classifier.map.bpm index 1c4ef86..d4fb2ab 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.map.bpm and b/Quartus/A1_Q6/db/instruction_classifier.map.bpm differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.cdb b/Quartus/A1_Q6/db/instruction_classifier.map.cdb index 4f16ef8..877d428 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.map.cdb and b/Quartus/A1_Q6/db/instruction_classifier.map.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.hdb b/Quartus/A1_Q6/db/instruction_classifier.map.hdb index 3fcbfd1..c67da46 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.map.hdb and b/Quartus/A1_Q6/db/instruction_classifier.map.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.qmsg b/Quartus/A1_Q6/db/instruction_classifier.map.qmsg index 96ef6d7..2b7f197 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.map.qmsg +++ b/Quartus/A1_Q6/db/instruction_classifier.map.qmsg @@ -1,11 +1,11 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431562372 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431562373 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:19:22 2026 " "Processing started: Tue Sep 15 10:19:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431562373 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431562373 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431562373 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789431562701 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789431562701 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" { { "Info" "ISGN_ENTITY_NAME" "1 instruction_classifier " "Found entity 1: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789431572260 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431572260 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "instruction_classifier " "Elaborating entity \"instruction_classifier\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789431572408 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789431573138 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789431573508 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789431573508 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789431573553 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789431573553 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789431573553 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789431573553 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431573561 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:19:33 2026 " "Processing ended: Tue Sep 15 10:19:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431573561 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431573561 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431573561 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431573561 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789466200354 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789466200355 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:56:40 2026 " "Processing started: Tue Sep 15 19:56:40 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789466200355 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789466200355 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789466200355 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789466200678 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789466200678 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" { { "Info" "ISGN_ENTITY_NAME" "1 instruction_classifier " "Found entity 1: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789466210547 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789466210547 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "instruction_classifier " "Elaborating entity \"instruction_classifier\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789466210684 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789466211393 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789466211748 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789466211748 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789466211776 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789466211776 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789466211776 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789466211776 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466211784 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:56:51 2026 " "Processing ended: Tue Sep 15 19:56:51 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466211784 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466211784 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466211784 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789466211784 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.rdb b/Quartus/A1_Q6/db/instruction_classifier.map.rdb index ab91854..5b9b05d 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.map.rdb and b/Quartus/A1_Q6/db/instruction_classifier.map.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map_bb.cdb b/Quartus/A1_Q6/db/instruction_classifier.map_bb.cdb index df60a63..5cdf517 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.map_bb.cdb and b/Quartus/A1_Q6/db/instruction_classifier.map_bb.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map_bb.hdb b/Quartus/A1_Q6/db/instruction_classifier.map_bb.hdb index 1342f1b..63ea78a 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.map_bb.hdb and b/Quartus/A1_Q6/db/instruction_classifier.map_bb.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.pplq.rdb b/Quartus/A1_Q6/db/instruction_classifier.pplq.rdb new file mode 100644 index 0000000..e1f255e Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.pplq.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.pre_map.hdb b/Quartus/A1_Q6/db/instruction_classifier.pre_map.hdb index 0f9207c..097a6d9 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.pre_map.hdb and b/Quartus/A1_Q6/db/instruction_classifier.pre_map.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.routing.rdb b/Quartus/A1_Q6/db/instruction_classifier.routing.rdb index 9d5ad3d..3fa1439 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.routing.rdb and b/Quartus/A1_Q6/db/instruction_classifier.routing.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.rtlv.hdb b/Quartus/A1_Q6/db/instruction_classifier.rtlv.hdb index 43e637e..e1fb835 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.rtlv.hdb and b/Quartus/A1_Q6/db/instruction_classifier.rtlv.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg.cdb b/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg.cdb index 269ceb8..5fd584e 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg.cdb and b/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.sta.qmsg b/Quartus/A1_Q6/db/instruction_classifier.sta.qmsg index 95a61a7..1d6d963 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.sta.qmsg +++ b/Quartus/A1_Q6/db/instruction_classifier.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431616218 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431616218 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:20:15 2026 " "Processing started: Tue Sep 15 10:20:15 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431616218 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789431616218 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q6 -c instruction_classifier " "Command: quartus_sta A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789431616219 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789431616277 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789431616764 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789431616764 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431616842 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431616842 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789431617439 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431617439 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431617440 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431617440 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789431617440 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431617440 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789431617441 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789431617448 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789431617448 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617450 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617453 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617454 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617455 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617456 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617457 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789431617459 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789431617506 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789431618682 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431618767 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431618767 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431618767 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431618767 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618768 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618769 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618770 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618771 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618772 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618773 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789431618774 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789431619046 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789431619708 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431619758 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431619758 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431619758 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431619758 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619759 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619760 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619761 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619762 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619763 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789431619765 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431619925 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431619926 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431619926 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431619927 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619929 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619931 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619932 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619934 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619935 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789431621439 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789431621440 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "785 " "Peak virtual memory: 785 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431621463 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:21 2026 " "Processing ended: Tue Sep 15 10:20:21 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431621463 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431621463 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431621463 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789431621463 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789466249262 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789466249262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:57:29 2026 " "Processing started: Tue Sep 15 19:57:29 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789466249262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789466249262 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q6 -c instruction_classifier " "Command: quartus_sta A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789466249263 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789466249320 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789466249788 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789466249788 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466249859 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466249859 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789466250424 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466250424 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789466250424 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789466250425 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789466250425 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789466250425 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789466250426 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789466250430 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789466250430 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250432 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250435 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250436 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250436 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250437 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250438 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789466250440 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789466250477 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789466251796 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466251871 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789466251871 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789466251872 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789466251872 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251873 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251874 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251875 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251876 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251877 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251877 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789466251879 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789466252142 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789466252856 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466252911 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789466252911 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789466252911 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789466252911 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252913 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252914 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252915 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252916 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252916 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789466252918 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466253066 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789466253066 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789466253066 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789466253067 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253068 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253069 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253070 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253071 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253072 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789466254483 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789466254483 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "776 " "Peak virtual memory: 776 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466254506 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:57:34 2026 " "Processing ended: Tue Sep 15 19:57:34 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466254506 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466254506 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466254506 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789466254506 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.sta.rdb b/Quartus/A1_Q6/db/instruction_classifier.sta.rdb index 9592128..f87d5db 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.sta.rdb and b/Quartus/A1_Q6/db/instruction_classifier.sta.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A1_Q6/db/instruction_classifier.sta_cmp.7_H6_slow_1100mv_85c.tdb index 19e7a2f..8346547 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.sta_cmp.7_H6_slow_1100mv_85c.tdb and b/Quartus/A1_Q6/db/instruction_classifier.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_0c.ddb index f957e24..cbde46e 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_85c.ddb index f1e526b..09de9e8 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_0c.ddb index d410261..a29d6b3 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_0c.ddb and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_85c.ddb index 7f340aa..de79e68 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_85c.ddb and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_0c.ddb index 74619ac..5052a14 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_85c.ddb index a6d3fc6..1274a74 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tmw_info b/Quartus/A1_Q6/db/instruction_classifier.tmw_info index 9930155..d42c07f 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.tmw_info +++ b/Quartus/A1_Q6/db/instruction_classifier.tmw_info @@ -1,7 +1,7 @@ -start_full_compilation:s:00:01:03 +start_full_compilation:s:00:00:58 start_analysis_synthesis:s:00:00:13-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:34-start_full_compilation +start_fitter:s:00:00:29-start_full_compilation start_assembler:s:00:00:07-start_full_compilation start_timing_analyzer:s:00:00:07-start_full_compilation start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/Quartus/A1_Q6/db/instruction_classifier.vpr.ammdb b/Quartus/A1_Q6/db/instruction_classifier.vpr.ammdb index 96bf786..92e9905 100644 Binary files a/Quartus/A1_Q6/db/instruction_classifier.vpr.ammdb and b/Quartus/A1_Q6/db/instruction_classifier.vpr.ammdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.ammdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.ammdb index 39dcaf2..bb3af5d 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.ammdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.ammdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.cdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.cdb index 48d808f..a87e48c 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.cdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.cdb index 34ff019..e36eeaa 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.hdb index d2a946b..41fdb92 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hdb index 30525f0..0bf7283 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.rcfdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.rcfdb index c2df523..876e5e4 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.rcfdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.rcfdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.cdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.cdb index 7cf41b5..f6ee2da 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.cdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.cdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.cdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.cdb index aa9528a..2e02448 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.cdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hdb index 9254a92..87c6df4 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hdb index 9a352eb..b2e2eca 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrp.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrp.hdb index ca88107..2ac6a75 100644 Binary files a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrp.hdb and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrp.hdb differ diff --git a/Quartus/A1_Q6/instruction_classifier.qsf b/Quartus/A1_Q6/instruction_classifier.qsf index 109b697..9c3c208 100644 --- a/Quartus/A1_Q6/instruction_classifier.qsf +++ b/Quartus/A1_Q6/instruction_classifier.qsf @@ -55,7 +55,27 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name IO_STANDARD "1.2 V" -to op[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to op[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to op[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to op[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to op[4] +set_instance_assignment -name IO_STANDARD "1.2 V" -to op[5] +set_instance_assignment -name IO_STANDARD "1.2 V" -to op +set_location_assignment PIN_AC9 -to op[0] +set_location_assignment PIN_AE10 -to op[1] +set_location_assignment PIN_AD13 -to op[2] +set_location_assignment PIN_AC8 -to op[3] +set_location_assignment PIN_W11 -to op[4] +set_location_assignment PIN_AB10 -to op[5] +set_location_assignment PIN_F7 -to M[0] +set_location_assignment PIN_F6 -to F[0] +set_location_assignment PIN_G6 -to I[0] +set_location_assignment PIN_G7 -to B2[0] +set_location_assignment PIN_J8 -to J[0] +set_location_assignment PIN_J7 -to B1[0] +set_location_assignment PIN_K10 -to R[0] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/A1_Q6/instruction_classifier.qws b/Quartus/A1_Q6/instruction_classifier.qws deleted file mode 100644 index af28712..0000000 Binary files a/Quartus/A1_Q6/instruction_classifier.qws and /dev/null differ diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.asm.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.asm.rpt index 3ac2359..da63109 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.asm.rpt +++ b/Quartus/A1_Q6/output_files/instruction_classifier.asm.rpt @@ -1,5 +1,5 @@ Assembler report for instruction_classifier -Tue Sep 15 10:20:14 2026 +Tue Sep 15 19:57:27 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Sep 15 10:20:14 2026 ; +; Assembler Status ; Successful - Tue Sep 15 19:57:27 2026 ; ; Revision Name ; instruction_classifier ; ; Top-level Entity Name ; instruction_classifier ; ; Family ; Cyclone V ; @@ -67,8 +67,8 @@ on the Quartus Prime software download page. +----------------+-------------------------------------+ ; Option ; Setting ; +----------------+-------------------------------------+ -; JTAG usercode ; 0x00780971 ; -; Checksum ; 0x00780971 ; +; JTAG usercode ; 0x0078176D ; +; Checksum ; 0x0078176D ; +----------------+-------------------------------------+ @@ -78,14 +78,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:20:08 2026 + Info: Processing started: Tue Sep 15 19:57:22 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 517 megabytes - Info: Processing ended: Tue Sep 15 10:20:14 2026 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 + Info: Peak virtual memory: 513 megabytes + Info: Processing ended: Tue Sep 15 19:57:27 2026 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.done b/Quartus/A1_Q6/output_files/instruction_classifier.done index 551cca3..8a11a2d 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.done +++ b/Quartus/A1_Q6/output_files/instruction_classifier.done @@ -1 +1 @@ -Tue Sep 15 10:20:24 2026 +Tue Sep 15 19:57:37 2026 diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.eda.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.eda.rpt index 158052b..72bca14 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.eda.rpt +++ b/Quartus/A1_Q6/output_files/instruction_classifier.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for instruction_classifier -Tue Sep 15 10:20:23 2026 +Tue Sep 15 19:57:36 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:20:23 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Sep 15 19:57:36 2026 ; ; Revision Name ; instruction_classifier ; ; Top-level Entity Name ; instruction_classifier ; ; Family ; Cyclone V ; @@ -81,13 +81,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:20:22 2026 + Info: Processing started: Tue Sep 15 19:57:35 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file instruction_classifier.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 659 megabytes - Info: Processing ended: Tue Sep 15 10:20:23 2026 + Info: Peak virtual memory: 658 megabytes + Info: Processing ended: Tue Sep 15 19:57:36 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.fit.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.fit.rpt index 2574dc1..7b12e89 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.fit.rpt +++ b/Quartus/A1_Q6/output_files/instruction_classifier.fit.rpt @@ -1,5 +1,5 @@ Fitter report for instruction_classifier -Tue Sep 15 10:20:06 2026 +Tue Sep 15 19:57:20 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -10,27 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 2. Fitter Summary 3. Fitter Settings 4. Parallel Compilation - 5. Incremental Compilation Preservation Summary - 6. Incremental Compilation Partition Settings - 7. Incremental Compilation Placement Preservation - 8. Pin-Out File - 9. Fitter Resource Usage Summary - 10. Fitter Partition Statistics - 11. Input Pins - 12. Output Pins - 13. I/O Bank Usage - 14. All Package Pins - 15. I/O Assignment Warnings - 16. Fitter Resource Utilization by Entity - 17. Delay Chain Summary - 18. Pad To Core Delay Chain Fanout - 19. Routing Usage Summary - 20. I/O Rules Summary - 21. I/O Rules Details - 22. I/O Rules Matrix - 23. Fitter Device Options - 24. Operating Settings and Conditions - 25. Fitter Messages + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. I/O Rules Summary + 22. I/O Rules Details + 23. I/O Rules Matrix + 24. Fitter Device Options + 25. Operating Settings and Conditions + 26. Fitter Messages @@ -57,7 +58,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Sep 15 10:20:06 2026 ; +; Fitter Status ; Successful - Tue Sep 15 19:57:20 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; instruction_classifier ; ; Top-level Entity Name ; instruction_classifier ; @@ -152,10 +153,19 @@ on the Quartus Prime software download page. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.1% ; +; Processor 2 ; 0.2% ; +----------------------------+-------------+ ++----------------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++--------------+------------------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++--------------+------------------------+--------------+------------+---------------+----------------+ +; I/O Standard ; instruction_classifier ; ; op ; 1.2 V ; QSF Assignment ; ++--------------+------------------------+--------------+------------+---------------+----------------+ + + +-------------------------------------------------------------------------------------------------+ ; Incremental Compilation Preservation Summary ; +---------------------+-------------------+----------------------------+--------------------------+ @@ -240,7 +250,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; ; ; ; ; Virtual pins ; 0 ; ; ; I/O pins ; 13 / 364 ; 4 % ; -; -- Clock pins ; 1 / 14 ; 7 % ; +; -- Clock pins ; 0 / 14 ; 0 % ; ; -- Dedicated input pins ; 0 / 23 ; 0 % ; ; ; ; ; ; M10K blocks ; 0 / 446 ; 0 % ; @@ -270,8 +280,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Channel PLLs ; 0 / 6 ; 0 % ; ; Impedance control blocks ; 0 / 3 ; 0 % ; ; Hard Memory Controllers ; 0 / 2 ; 0 % ; -; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; -; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; ; +; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.3% ; ; ; Maximum fan-out ; 7 ; ; ; Highest non-global fan-out ; 7 ; ; ; Total fan-out ; 46 ; ; @@ -370,12 +380,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ -; op[0] ; AB12 ; 3B ; 14 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[1] ; AB11 ; 3B ; 14 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[2] ; T9 ; 3B ; 10 ; 0 ; 74 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[3] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[4] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[5] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[0] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; op[1] ; AE10 ; 4A ; 36 ; 0 ; 51 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; op[2] ; AD13 ; 4A ; 34 ; 0 ; 34 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; op[3] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; op[4] ; W11 ; 3B ; 10 ; 0 ; 40 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; op[5] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ @@ -384,32 +394,32 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ -; B1[0] ; AC10 ; 3B ; 12 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; B2[0] ; T13 ; 3B ; 15 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; F[0] ; Y10 ; 3B ; 15 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; I[0] ; R11 ; 3B ; 12 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; J[0] ; T12 ; 3B ; 15 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; M[0] ; T11 ; 3B ; 12 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; R[0] ; W10 ; 3B ; 15 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; B1[0] ; J7 ; 8A ; 12 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; B2[0] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; F[0] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; I[0] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; J[0] ; J8 ; 8A ; 14 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; M[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; R[0] ; K10 ; 8A ; 12 ; 61 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +-------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ -+----------------------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+---------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; -+----------+------------------+---------------+--------------+---------------+ -; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 3B ; 13 / 32 ( 41 % ) ; 2.5V ; -- ; 2.5V ; -; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -+----------+------------------+---------------+--------------+---------------+ ++---------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+-----------------+---------------+--------------+---------------+ +; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 4 / 32 ( 13 % ) ; 1.2V ; -- ; 2.5V ; +; 4A ; 2 / 80 ( 3 % ) ; 1.2V ; -- ; 2.5V ; +; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 7 / 32 ( 22 % ) ; 2.5V ; -- ; 2.5V ; ++----------+-----------------+---------------+--------------+---------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -450,7 +460,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; -; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA10 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -460,7 +470,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA20 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; @@ -476,10 +486,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AB10 ; 61 ; 3B ; op[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB11 ; 63 ; 3B ; op[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB12 ; 65 ; 3B ; op[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB10 ; 61 ; 3B ; op[5] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -500,15 +510,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; -; AC8 ; 62 ; 3B ; op[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AC9 ; 64 ; 3B ; op[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AC10 ; 59 ; 3B ; B1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AC8 ; 62 ; 3B ; op[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; AC9 ; 64 ; 3B ; op[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; AC10 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; ; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC16 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -527,17 +537,17 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD9 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD13 ; 93 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD13 ; 93 ; 4A ; op[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AD15 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; ; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD19 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -554,9 +564,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE10 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; 94 ; 4A ; op[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE12 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -566,7 +576,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE22 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -584,7 +594,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF15 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -704,8 +714,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; F5 ; 398 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; F6 ; 360 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F7 ; 366 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F6 ; 360 ; 8A ; F[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F7 ; 366 ; 8A ; M[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; ; F8 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; ; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -730,8 +740,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; G3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; G4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; G5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; G6 ; 362 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G7 ; 364 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G6 ; 362 ; 8A ; I[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G7 ; 364 ; 8A ; B2[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; ; G8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; G9 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; G10 ; 357 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -783,8 +793,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; J5 ; 399 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; ; J6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J7 ; 370 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J8 ; 365 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J7 ; 370 ; 8A ; B1[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; J8 ; 365 ; 8A ; J[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; ; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; J10 ; 369 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; J11 ; 289 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -812,7 +822,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; K7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; K8 ; 363 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; K9 ; 361 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; K10 ; 367 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K10 ; 367 ; 8A ; R[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; ; K11 ; 305 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -943,7 +953,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; R8 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; R9 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; R10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R11 ; 60 ; 3B ; I[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R11 ; 60 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; R13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; R14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -967,11 +977,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; T6 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; ; T7 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; T8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T9 ; 56 ; 3B ; op[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T9 ; 56 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T11 ; 58 ; 3B ; M[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; T12 ; 66 ; 3B ; J[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; T13 ; 68 ; 3B ; B2[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T11 ; 58 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 66 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; 68 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; T14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; T16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; @@ -992,7 +1002,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; ; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U8 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1002,7 +1012,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U18 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -1021,7 +1031,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V11 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1046,11 +1056,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; W7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W10 ; 69 ; 3B ; R[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 57 ; 3B ; op[4] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W14 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1072,14 +1082,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Y7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y10 ; 67 ; 3B ; F[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1105,25 +1115,6 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; I[0] ; Incomplete set of assignments ; ; F[0] ; Incomplete set of assignments ; ; M[0] ; Incomplete set of assignments ; -; op[0] ; Incomplete set of assignments ; -; op[1] ; Incomplete set of assignments ; -; op[2] ; Incomplete set of assignments ; -; op[3] ; Incomplete set of assignments ; -; op[4] ; Incomplete set of assignments ; -; op[5] ; Incomplete set of assignments ; -; R[0] ; Missing location assignment ; -; B1[0] ; Missing location assignment ; -; J[0] ; Missing location assignment ; -; B2[0] ; Missing location assignment ; -; I[0] ; Missing location assignment ; -; F[0] ; Missing location assignment ; -; M[0] ; Missing location assignment ; -; op[0] ; Missing location assignment ; -; op[1] ; Missing location assignment ; -; op[2] ; Missing location assignment ; -; op[3] ; Missing location assignment ; -; op[4] ; Missing location assignment ; -; op[5] ; Missing location assignment ; +----------+-------------------------------+ @@ -1132,7 +1123,7 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------+------------------------+--------------+ ; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------+------------------------+--------------+ -; |instruction_classifier ; 5.0 (5.0) ; 5.0 (5.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 13 ; 0 ; |instruction_classifier ; instruction_classifier ; work ; +; |instruction_classifier ; 4.5 (4.5) ; 5.0 (5.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 13 ; 0 ; |instruction_classifier ; instruction_classifier ; work ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------+------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -1149,12 +1140,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; I[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; F[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; M[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; op[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; op[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; op[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; op[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; op[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[5] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +-------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ @@ -1164,17 +1155,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Source Pin / Fanout ; Pad To Core Index ; Setting ; +---------------------+-------------------+---------+ ; op[0] ; ; ; -; - Equal0~0 ; 0 ; 0 ; -; - Equal1~0 ; 0 ; 0 ; +; - Equal0~0 ; 1 ; 0 ; +; - Equal1~0 ; 1 ; 0 ; ; op[1] ; ; ; ; - Equal0~0 ; 1 ; 0 ; ; - Equal1~0 ; 1 ; 0 ; ; - Equal2~0 ; 1 ; 0 ; ; op[2] ; ; ; -; - Equal0~0 ; 1 ; 0 ; -; - Equal1~0 ; 1 ; 0 ; -; - Equal2~0 ; 1 ; 0 ; -; - Equal3~0 ; 1 ; 0 ; +; - Equal0~0 ; 0 ; 0 ; +; - Equal1~0 ; 0 ; 0 ; +; - Equal2~0 ; 0 ; 0 ; +; - Equal3~0 ; 0 ; 0 ; ; op[3] ; ; ; ; - Equal0~0 ; 1 ; 0 ; ; - Equal1~0 ; 1 ; 0 ; @@ -1189,13 +1180,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; - Equal4~0 ; 1 ; 0 ; ; - Equal5~0 ; 1 ; 0 ; ; op[5] ; ; ; -; - Equal0~0 ; 1 ; 0 ; -; - Equal1~0 ; 1 ; 0 ; -; - Equal2~0 ; 1 ; 0 ; -; - Equal3~0 ; 1 ; 0 ; -; - Equal4~0 ; 1 ; 0 ; -; - Equal5~0 ; 1 ; 0 ; -; - M[0]~output ; 1 ; 0 ; +; - Equal0~0 ; 0 ; 0 ; +; - Equal1~0 ; 0 ; 0 ; +; - Equal2~0 ; 0 ; 0 ; +; - Equal3~0 ; 0 ; 0 ; +; - Equal4~0 ; 0 ; 0 ; +; - Equal5~0 ; 0 ; 0 ; +; - M[0]~output ; 0 ; 0 ; +---------------------+-------------------+---------+ @@ -1205,8 +1196,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Routing Resource Type ; Usage ; +------------------------------+------------------------+ ; Block interconnects ; 13 / 217,884 ( < 1 % ) ; -; C12 interconnects ; 0 / 10,080 ( 0 % ) ; -; C2 interconnects ; 9 / 87,208 ( < 1 % ) ; +; C12 interconnects ; 31 / 10,080 ( < 1 % ) ; +; C2 interconnects ; 7 / 87,208 ( < 1 % ) ; ; C4 interconnects ; 4 / 41,360 ( < 1 % ) ; ; DQS bus muxes ; 0 / 21 ( 0 % ) ; ; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; @@ -1216,10 +1207,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; ; Local interconnects ; 0 / 58,160 ( 0 % ) ; ; Quadrant clocks ; 0 / 88 ( 0 % ) ; -; R14 interconnects ; 0 / 9,228 ( 0 % ) ; -; R14/C12 interconnect drivers ; 0 / 15,096 ( 0 % ) ; +; R14 interconnects ; 2 / 9,228 ( < 1 % ) ; +; R14/C12 interconnect drivers ; 27 / 15,096 ( < 1 % ) ; ; R3 interconnects ; 6 / 94,896 ( < 1 % ) ; -; R6 interconnects ; 2 / 194,640 ( < 1 % ) ; +; R6 interconnects ; 3 / 194,640 ( < 1 % ) ; ; Spine clocks ; 0 / 180 ( 0 % ) ; ; Wire stub REs ; 0 / 11,606 ( 0 % ) ; +------------------------------+------------------------+ @@ -1231,10 +1222,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; I/O Rules Statistic ; Total ; +----------------------------------+-------+ ; Total I/O Rules ; 28 ; -; Number of I/O Rules Passed ; 6 ; +; Number of I/O Rules Passed ; 9 ; ; Number of I/O Rules Failed ; 0 ; ; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 22 ; +; Number of I/O Rules Inapplicable ; 19 ; +----------------------------------+-------+ @@ -1244,12 +1235,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ ; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; -; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; -; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; ; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; ; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; ; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; ; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; ; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; ; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; @@ -1275,29 +1266,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Matrix ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ -; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ -; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 13 ; 13 ; 0 ; -; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 13 ; 13 ; 13 ; 13 ; 13 ; 0 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 0 ; 0 ; 13 ; -; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; R[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; J[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B2[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; I[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; F[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; M[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Total Pass ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 13 ; 13 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 0 ; 0 ; 13 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; R[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; J[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B2[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; I[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; F[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; M[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +------------------------------------------------------------------------------------------------+ @@ -1354,13 +1345,12 @@ Info (21077): High junction temperature is 85 degrees C Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Critical Warning (169085): No exact pin location assignment(s) for 13 pins of 13 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. Info (184020): Starting Fitter periphery placement operations Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks -Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08 +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07 Critical Warning (332012): Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. @@ -1370,27 +1360,28 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. Info (170189): Fitter placement preparation operations beginning Info (14951): The Fitter is using Advanced Physical Optimization. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:04 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources - Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11 + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y49 to location X22_Y61 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.08 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 1369 megabytes - Info: Processing ended: Tue Sep 15 10:20:07 2026 - Info: Elapsed time: 00:00:33 - Info: Total CPU time (on all processors): 00:00:49 + Info: Peak virtual memory: 1384 megabytes + Info: Processing ended: Tue Sep 15 19:57:20 2026 + Info: Elapsed time: 00:00:28 + Info: Total CPU time (on all processors): 00:00:39 diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.fit.summary b/Quartus/A1_Q6/output_files/instruction_classifier.fit.summary index 85e8078..293c745 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.fit.summary +++ b/Quartus/A1_Q6/output_files/instruction_classifier.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Sep 15 10:20:06 2026 +Fitter Status : Successful - Tue Sep 15 19:57:20 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : instruction_classifier Top-level Entity Name : instruction_classifier diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.flow.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.flow.rpt index a324f39..d9f9765 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.flow.rpt +++ b/Quartus/A1_Q6/output_files/instruction_classifier.flow.rpt @@ -1,5 +1,5 @@ Flow report for instruction_classifier -Tue Sep 15 10:20:23 2026 +Tue Sep 15 19:57:36 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,7 +41,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Sep 15 10:20:23 2026 ; +; Flow Status ; Successful - Tue Sep 15 19:57:36 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; instruction_classifier ; ; Top-level Entity Name ; instruction_classifier ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+------------------------+ ; Option ; Setting ; +-------------------+------------------------+ -; Start date & time ; 09/15/2026 10:19:22 ; +; Start date & time ; 09/15/2026 19:56:40 ; ; Main task ; Compilation ; ; Revision Name ; instruction_classifier ; +-------------------+------------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 253029099468756.178943156207722 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 268883478169649.178946620008468 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,12 +101,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 413 MB ; 00:00:26 ; -; Fitter ; 00:00:32 ; 1.0 ; 1369 MB ; 00:00:48 ; -; Assembler ; 00:00:06 ; 1.0 ; 517 MB ; 00:00:06 ; -; Timing Analyzer ; 00:00:06 ; 1.0 ; 785 MB ; 00:00:05 ; -; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 659 MB ; 00:00:01 ; -; Total ; 00:00:56 ; -- ; -- ; 00:01:26 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ; +; Fitter ; 00:00:28 ; 1.0 ; 1384 MB ; 00:00:39 ; +; Assembler ; 00:00:05 ; 1.0 ; 513 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:05 ; 1.0 ; 776 MB ; 00:00:05 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ; +; Total ; 00:00:50 ; -- ; -- ; 00:01:17 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.map.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.map.rpt index a54d795..6d96efe 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.map.rpt +++ b/Quartus/A1_Q6/output_files/instruction_classifier.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for instruction_classifier -Tue Sep 15 10:19:33 2026 +Tue Sep 15 19:56:51 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -43,7 +43,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:19:33 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:56:51 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; instruction_classifier ; ; Top-level Entity Name ; instruction_classifier ; @@ -261,7 +261,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:19:22 2026 + Info: Processing started: Tue Sep 15 19:56:40 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -276,9 +276,9 @@ Info (21057): Implemented 19 device resources after synthesis - the final resour Info (21059): Implemented 7 output pins Info (21061): Implemented 6 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning - Info: Peak virtual memory: 430 megabytes - Info: Processing ended: Tue Sep 15 10:19:33 2026 + Info: Peak virtual memory: 436 megabytes + Info: Processing ended: Tue Sep 15 19:56:51 2026 Info: Elapsed time: 00:00:11 - Info: Total CPU time (on all processors): 00:00:26 + Info: Total CPU time (on all processors): 00:00:27 diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.map.summary b/Quartus/A1_Q6/output_files/instruction_classifier.map.summary index 7748422..1787407 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.map.summary +++ b/Quartus/A1_Q6/output_files/instruction_classifier.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Tue Sep 15 10:19:33 2026 +Analysis & Synthesis Status : Successful - Tue Sep 15 19:56:51 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : instruction_classifier Top-level Entity Name : instruction_classifier diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.pin b/Quartus/A1_Q6/output_files/instruction_classifier.pin index b25b01e..e03722c 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.pin +++ b/Quartus/A1_Q6/output_files/instruction_classifier.pin @@ -29,8 +29,8 @@ -- VCCIO : Dedicated power pin, which MUST be connected to VCC -- of its bank. -- Bank 3A: 2.5V - -- Bank 3B: 2.5V - -- Bank 4A: 2.5V + -- Bank 3B: 1.2V + -- Bank 4A: 1.2V -- Bank 5A: 2.5V -- Bank 5B: 2.5V -- Bank 6A: 2.5V @@ -109,7 +109,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A : VCC_AUX : AA8 : power : : 2.5V : : VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : : -VCCIO3B : AA10 : power : : 2.5V : 3B : +VCCIO3B : AA10 : power : : 1.2V : 3B : VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A : NC : AA12 : : : : : VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A : @@ -119,7 +119,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A : -VCCIO4A : AA20 : power : : 2.5V : 4A : +VCCIO4A : AA20 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A : @@ -135,10 +135,10 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : NC : AB7 : : : : : GND : AB8 : gnd : : : : VCCPD3A : AB9 : power : : 2.5V : 3A : -op[5] : AB10 : input : 2.5 V : : 3B : N -op[1] : AB11 : input : 2.5 V : : 3B : N -op[0] : AB12 : input : 2.5 V : : 3B : N -VCCIO4A : AB13 : power : : 2.5V : 4A : +op[5] : AB10 : input : 1.2 V : : 3B : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B : +VCCIO4A : AB13 : power : : 1.2V : 4A : VCC_AUX : AB14 : power : : 2.5V : : RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A : @@ -159,15 +159,15 @@ GXB_NC : AC4 : : : GND : AC5 : gnd : : : : VCCIO3A : AC6 : power : : 2.5V : 3A : VREFB3AN0 : AC7 : power : : : 3A : -op[3] : AC8 : input : 2.5 V : : 3B : N -op[4] : AC9 : input : 2.5 V : : 3B : N -B1[0] : AC10 : output : 2.5 V : : 3B : N +op[3] : AC8 : input : 1.2 V : : 3B : Y +op[0] : AC9 : input : 1.2 V : : 3B : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B : GND : AC11 : gnd : : : : VREFB3BN0 : AC12 : power : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A : -VCCIO4A : AC16 : power : : 2.5V : 4A : +VCCIO4A : AC16 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A : @@ -186,17 +186,17 @@ AS_DATA1, DATA1 : AD5 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B : -VCCIO3B : AD9 : power : : 2.5V : 3B : +VCCIO3B : AD9 : power : : 1.2V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 4A : +op[2] : AD13 : input : 1.2 V : : 4A : Y GND : AD14 : gnd : : : : VREFB4AN0 : AD15 : power : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A : -VCCIO4A : AD19 : power : : 2.5V : 4A : +VCCIO4A : AD19 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A : @@ -213,9 +213,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : GND : AE7 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A : +op[1] : AE10 : input : 1.2 V : : 4A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A : -VCCIO4A : AE12 : power : : 2.5V : 4A : +VCCIO4A : AE12 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A : @@ -225,7 +225,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A : -VCCIO4A : AE22 : power : : 2.5V : 4A : +VCCIO4A : AE22 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A : @@ -243,7 +243,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A : -VCCIO4A : AF15 : power : : 2.5V : 4A : +VCCIO4A : AF15 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : @@ -363,8 +363,8 @@ NC : F2 : : : GND : F3 : gnd : : : : GND : F4 : gnd : : : : nCONFIG : F5 : : : : 9A : -RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A : -RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A : +F[0] : F6 : output : 2.5 V : : 8A : Y +M[0] : F7 : output : 2.5 V : : 8A : Y VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : : VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A : GND : F10 : gnd : : : : @@ -389,8 +389,8 @@ GND : G2 : gnd : : NC : G3 : : : : : NC : G4 : : : : : GND : G5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8A : -RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A : +I[0] : G6 : output : 2.5 V : : 8A : Y +B2[0] : G7 : output : 2.5 V : : 8A : Y VCCIO8A : G8 : power : : 2.5V : 8A : VCC_AUX : G9 : power : : 2.5V : : RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A : @@ -442,8 +442,8 @@ VCCL_GXBL : J3 : power : : 1.1V GND : J4 : gnd : : : : MSEL4 : J5 : : : : 9A : VCCA_FPLL : J6 : power : : 2.5V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A : -RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 8A : +B1[0] : J7 : output : 2.5 V : : 8A : Y +J[0] : J8 : output : 2.5 V : : 8A : Y GND : J9 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A : RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7A : @@ -471,7 +471,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : VCCIO8A : K7 : power : : 2.5V : 8A : RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A : RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 8A : -RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 8A : +R[0] : K10 : output : 2.5 V : : 8A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 7A : GND : K12 : gnd : : : : GND : K13 : gnd : : : : @@ -602,7 +602,7 @@ GND : R7 : gnd : : RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3A : -I[0] : R11 : output : 2.5 V : : 3B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3B : GND : R12 : gnd : : : : VCC : R13 : power : : 1.1V : : GND : R14 : gnd : : : : @@ -626,11 +626,11 @@ GND : T5 : gnd : : TDI : T6 : input : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A : -op[2] : T9 : input : 2.5 V : : 3B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3B : GND : T10 : gnd : : : : -M[0] : T11 : output : 2.5 V : : 3B : N -J[0] : T12 : output : 2.5 V : : 3B : N -B2[0] : T13 : output : 2.5 V : : 3B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B : VCC : T14 : power : : 1.1V : : GND : T15 : gnd : : : : VCC : T16 : power : : 1.1V : : @@ -651,7 +651,7 @@ GND : U4 : gnd : : VCCE_GXBL : U5 : power : : 1.1V : : AS_DATA3, DATA3 : U6 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A : -VCCIO3B : U8 : power : : 2.5V : 3B : +VCCIO3B : U8 : power : : 1.2V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B : @@ -661,7 +661,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A : -VCCIO4A : U18 : power : : 2.5V : 4A : +VCCIO4A : U18 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A : VCCPD5A : U21 : power : : 2.5V : 5A : @@ -680,7 +680,7 @@ TDO : V7 : output : : RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B : -VCCIO3B : V11 : power : : 2.5V : 3B : +VCCIO3B : V11 : power : : 1.2V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A : @@ -705,11 +705,11 @@ GND : W6 : : : VCCA_FPLL : W7 : power : : 2.5V : : RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A : GND : W9 : gnd : : : : -R[0] : W10 : output : 2.5 V : : 3B : N -RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B : +op[4] : W11 : input : 1.2 V : : 3B : Y RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A : -VCCIO4A : W14 : power : : 2.5V : 4A : +VCCIO4A : W14 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A : @@ -731,14 +731,14 @@ nCSO, DATA4 : Y6 : : : VCCIO3A : Y7 : power : : 2.5V : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A : -F[0] : Y10 : output : 2.5 V : : 3B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B : GND : Y12 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A : -VCCIO4A : Y17 : power : : 2.5V : 4A : +VCCIO4A : Y17 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A : diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.sof b/Quartus/A1_Q6/output_files/instruction_classifier.sof index bc6b1a2..10004ca 100644 Binary files a/Quartus/A1_Q6/output_files/instruction_classifier.sof and b/Quartus/A1_Q6/output_files/instruction_classifier.sof differ diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.sta.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.sta.rpt index 7a956ca..fa946e3 100644 --- a/Quartus/A1_Q6/output_files/instruction_classifier.sta.rpt +++ b/Quartus/A1_Q6/output_files/instruction_classifier.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for instruction_classifier -Tue Sep 15 10:20:21 2026 +Tue Sep 15 19:57:34 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -305,12 +305,12 @@ No synchronizer chains to report. +-------+--------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +-------+--------------+-----------------+-----------------+ -; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; op[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; op[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; op[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[0] ; 1.2 V ; 960 ps ; 960 ps ; +; op[1] ; 1.2 V ; 960 ps ; 960 ps ; +; op[2] ; 1.2 V ; 960 ps ; 960 ps ; +; op[3] ; 1.2 V ; 960 ps ; 960 ps ; +; op[4] ; 1.2 V ; 960 ps ; 960 ps ; +; op[5] ; 1.2 V ; 960 ps ; 960 ps ; +-------+--------------+-----------------+-----------------+ @@ -319,13 +319,13 @@ No synchronizer chains to report. +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; ; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; ; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; -; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; -; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; -; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; +; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -334,13 +334,13 @@ No synchronizer chains to report. +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; ; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; ; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; -; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; -; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; -; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; +; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -349,13 +349,13 @@ No synchronizer chains to report. +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; ; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; ; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; -; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; -; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; -; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -364,13 +364,13 @@ No synchronizer chains to report. +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; ; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; ; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; -; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; -; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; -; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; -; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -470,7 +470,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:20:15 2026 + Info: Processing started: Tue Sep 15 19:57:29 2026 Info: Command: quartus_sta A1_Q6 -c instruction_classifier Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -530,9 +530,9 @@ Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 785 megabytes - Info: Processing ended: Tue Sep 15 10:20:21 2026 - Info: Elapsed time: 00:00:06 + Info: Peak virtual memory: 776 megabytes + Info: Processing ended: Tue Sep 15 19:57:34 2026 + Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q6/simulation/questa/instruction_classifier.svo b/Quartus/A1_Q6/simulation/questa/instruction_classifier.svo index 3cdb032..89d21d3 100644 --- a/Quartus/A1_Q6/simulation/questa/instruction_classifier.svo +++ b/Quartus/A1_Q6/simulation/questa/instruction_classifier.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "09/15/2026 10:20:23" +// DATE "09/15/2026 19:57:36" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 @@ -38,29 +38,29 @@ module instruction_classifier ( I, F, M); -input logic [5:0] op ; -output logic [0:0] R ; -output logic [0:0] B1 ; -output logic [0:0] J ; -output logic [0:0] B2 ; -output logic [0:0] I ; -output logic [0:0] F ; -output logic [0:0] M ; +input [5:0] op; +output [0:0] R; +output [0:0] B1; +output [0:0] J; +output [0:0] B2; +output [0:0] I; +output [0:0] F; +output [0:0] M; // Design Ports Information -// R[0] => Location: PIN_W10, I/O Standard: 2.5 V, Current Strength: Default -// B1[0] => Location: PIN_AC10, I/O Standard: 2.5 V, Current Strength: Default -// J[0] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default -// B2[0] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default -// I[0] => Location: PIN_R11, I/O Standard: 2.5 V, Current Strength: Default -// F[0] => Location: PIN_Y10, I/O Standard: 2.5 V, Current Strength: Default -// M[0] => Location: PIN_T11, I/O Standard: 2.5 V, Current Strength: Default -// op[0] => Location: PIN_AB12, I/O Standard: 2.5 V, Current Strength: Default -// op[1] => Location: PIN_AB11, I/O Standard: 2.5 V, Current Strength: Default -// op[2] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default -// op[3] => Location: PIN_AC8, I/O Standard: 2.5 V, Current Strength: Default -// op[4] => Location: PIN_AC9, I/O Standard: 2.5 V, Current Strength: Default -// op[5] => Location: PIN_AB10, I/O Standard: 2.5 V, Current Strength: Default +// R[0] => Location: PIN_K10, I/O Standard: 2.5 V, Current Strength: Default +// B1[0] => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +// J[0] => Location: PIN_J8, I/O Standard: 2.5 V, Current Strength: Default +// B2[0] => Location: PIN_G7, I/O Standard: 2.5 V, Current Strength: Default +// I[0] => Location: PIN_G6, I/O Standard: 2.5 V, Current Strength: Default +// F[0] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// M[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// op[0] => Location: PIN_AC9, I/O Standard: 1.2 V, Current Strength: Default +// op[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default +// op[2] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default +// op[3] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default +// op[4] => Location: PIN_W11, I/O Standard: 1.2 V, Current Strength: Default +// op[5] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default wire gnd; @@ -75,12 +75,12 @@ tri1 devclrn; tri1 devpor; tri1 devoe; wire \~QUARTUS_CREATED_GND~I_combout ; -wire \op[5]~input_o ; -wire \op[0]~input_o ; -wire \op[2]~input_o ; -wire \op[1]~input_o ; -wire \op[4]~input_o ; wire \op[3]~input_o ; +wire \op[0]~input_o ; +wire \op[5]~input_o ; +wire \op[2]~input_o ; +wire \op[4]~input_o ; +wire \op[1]~input_o ; wire \Equal0~0_combout ; wire \Equal1~0_combout ; wire \Equal2~0_combout ; @@ -89,7 +89,7 @@ wire \Equal4~0_combout ; wire \Equal5~0_combout ; -// Location: IOOBUF_X15_Y0_N36 +// Location: IOOBUF_X12_Y61_N2 cyclonev_io_obuf \R[0]~output ( .i(\Equal0~0_combout ), .oe(vcc), @@ -105,7 +105,7 @@ defparam \R[0]~output .open_drain_output = "false"; defparam \R[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X12_Y0_N53 +// Location: IOOBUF_X12_Y61_N53 cyclonev_io_obuf \B1[0]~output ( .i(\Equal1~0_combout ), .oe(vcc), @@ -121,7 +121,7 @@ defparam \B1[0]~output .open_drain_output = "false"; defparam \B1[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X15_Y0_N19 +// Location: IOOBUF_X14_Y61_N19 cyclonev_io_obuf \J[0]~output ( .i(\Equal2~0_combout ), .oe(vcc), @@ -137,7 +137,7 @@ defparam \J[0]~output .open_drain_output = "false"; defparam \J[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X15_Y0_N2 +// Location: IOOBUF_X14_Y61_N36 cyclonev_io_obuf \B2[0]~output ( .i(\Equal3~0_combout ), .oe(vcc), @@ -153,7 +153,7 @@ defparam \B2[0]~output .open_drain_output = "false"; defparam \B2[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X12_Y0_N2 +// Location: IOOBUF_X15_Y61_N53 cyclonev_io_obuf \I[0]~output ( .i(\Equal4~0_combout ), .oe(vcc), @@ -169,7 +169,7 @@ defparam \I[0]~output .open_drain_output = "false"; defparam \I[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X15_Y0_N53 +// Location: IOOBUF_X15_Y61_N36 cyclonev_io_obuf \F[0]~output ( .i(\Equal5~0_combout ), .oe(vcc), @@ -185,7 +185,7 @@ defparam \F[0]~output .open_drain_output = "false"; defparam \F[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X12_Y0_N19 +// Location: IOOBUF_X14_Y61_N53 cyclonev_io_obuf \M[0]~output ( .i(\op[5]~input_o ), .oe(vcc), @@ -201,61 +201,6 @@ defparam \M[0]~output .open_drain_output = "false"; defparam \M[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOIBUF_X12_Y0_N35 -cyclonev_io_ibuf \op[5]~input ( - .i(op[5]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[5]~input_o )); -// synopsys translate_off -defparam \op[5]~input .bus_hold = "false"; -defparam \op[5]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X14_Y0_N1 -cyclonev_io_ibuf \op[0]~input ( - .i(op[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[0]~input_o )); -// synopsys translate_off -defparam \op[0]~input .bus_hold = "false"; -defparam \op[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X10_Y0_N75 -cyclonev_io_ibuf \op[2]~input ( - .i(op[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[2]~input_o )); -// synopsys translate_off -defparam \op[2]~input .bus_hold = "false"; -defparam \op[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X14_Y0_N18 -cyclonev_io_ibuf \op[1]~input ( - .i(op[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[1]~input_o )); -// synopsys translate_off -defparam \op[1]~input .bus_hold = "false"; -defparam \op[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X14_Y0_N35 -cyclonev_io_ibuf \op[4]~input ( - .i(op[4]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[4]~input_o )); -// synopsys translate_off -defparam \op[4]~input .bus_hold = "false"; -defparam \op[4]~input .simulate_z_as = "z"; -// synopsys translate_on - // Location: IOIBUF_X14_Y0_N52 cyclonev_io_ibuf \op[3]~input ( .i(op[3]), @@ -267,17 +212,72 @@ defparam \op[3]~input .bus_hold = "false"; defparam \op[3]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: MLABCELL_X14_Y1_N30 +// Location: IOIBUF_X14_Y0_N35 +cyclonev_io_ibuf \op[0]~input ( + .i(op[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[0]~input_o )); +// synopsys translate_off +defparam \op[0]~input .bus_hold = "false"; +defparam \op[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X12_Y0_N35 +cyclonev_io_ibuf \op[5]~input ( + .i(op[5]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[5]~input_o )); +// synopsys translate_off +defparam \op[5]~input .bus_hold = "false"; +defparam \op[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y0_N35 +cyclonev_io_ibuf \op[2]~input ( + .i(op[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[2]~input_o )); +// synopsys translate_off +defparam \op[2]~input .bus_hold = "false"; +defparam \op[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X10_Y0_N41 +cyclonev_io_ibuf \op[4]~input ( + .i(op[4]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[4]~input_o )); +// synopsys translate_off +defparam \op[4]~input .bus_hold = "false"; +defparam \op[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X36_Y0_N52 +cyclonev_io_ibuf \op[1]~input ( + .i(op[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[1]~input_o )); +// synopsys translate_off +defparam \op[1]~input .bus_hold = "false"; +defparam \op[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: MLABCELL_X14_Y60_N30 cyclonev_lcell_comb \Equal0~0 ( // Equation(s): -// \Equal0~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (!\op[0]~input_o & (!\op[2]~input_o & !\op[1]~input_o ))) ) ) ) +// \Equal0~0_combout = ( !\op[4]~input_o & ( !\op[1]~input_o & ( (!\op[3]~input_o & (!\op[0]~input_o & (!\op[5]~input_o & !\op[2]~input_o ))) ) ) ) - .dataa(!\op[5]~input_o ), + .dataa(!\op[3]~input_o ), .datab(!\op[0]~input_o ), - .datac(!\op[2]~input_o ), - .datad(!\op[1]~input_o ), + .datac(!\op[5]~input_o ), + .datad(!\op[2]~input_o ), .datae(!\op[4]~input_o ), - .dataf(!\op[3]~input_o ), + .dataf(!\op[1]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -291,17 +291,17 @@ defparam \Equal0~0 .lut_mask = 64'h8000000000000000; defparam \Equal0~0 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X14_Y1_N6 +// Location: MLABCELL_X14_Y60_N6 cyclonev_lcell_comb \Equal1~0 ( // Equation(s): -// \Equal1~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (\op[0]~input_o & (!\op[2]~input_o & !\op[1]~input_o ))) ) ) ) +// \Equal1~0_combout = ( !\op[4]~input_o & ( !\op[1]~input_o & ( (!\op[3]~input_o & (\op[0]~input_o & (!\op[5]~input_o & !\op[2]~input_o ))) ) ) ) - .dataa(!\op[5]~input_o ), + .dataa(!\op[3]~input_o ), .datab(!\op[0]~input_o ), - .datac(!\op[2]~input_o ), - .datad(!\op[1]~input_o ), + .datac(!\op[5]~input_o ), + .datad(!\op[2]~input_o ), .datae(!\op[4]~input_o ), - .dataf(!\op[3]~input_o ), + .dataf(!\op[1]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -315,17 +315,17 @@ defparam \Equal1~0 .lut_mask = 64'h2000000000000000; defparam \Equal1~0 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X14_Y1_N42 +// Location: MLABCELL_X14_Y60_N12 cyclonev_lcell_comb \Equal2~0 ( // Equation(s): -// \Equal2~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (\op[1]~input_o & !\op[2]~input_o )) ) ) ) +// \Equal2~0_combout = ( !\op[4]~input_o & ( \op[1]~input_o & ( (!\op[3]~input_o & (!\op[2]~input_o & !\op[5]~input_o )) ) ) ) - .dataa(!\op[5]~input_o ), - .datab(!\op[1]~input_o ), - .datac(!\op[2]~input_o ), + .dataa(!\op[3]~input_o ), + .datab(!\op[2]~input_o ), + .datac(!\op[5]~input_o ), .datad(gnd), .datae(!\op[4]~input_o ), - .dataf(!\op[3]~input_o ), + .dataf(!\op[1]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -335,21 +335,21 @@ cyclonev_lcell_comb \Equal2~0 ( .shareout()); // synopsys translate_off defparam \Equal2~0 .extended_lut = "off"; -defparam \Equal2~0 .lut_mask = 64'h2020000000000000; +defparam \Equal2~0 .lut_mask = 64'h0000000080800000; defparam \Equal2~0 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X14_Y1_N51 +// Location: MLABCELL_X14_Y60_N51 cyclonev_lcell_comb \Equal3~0 ( // Equation(s): -// \Equal3~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (\op[2]~input_o & !\op[5]~input_o ) ) ) ) +// \Equal3~0_combout = ( !\op[4]~input_o & ( \op[2]~input_o & ( (!\op[5]~input_o & !\op[3]~input_o ) ) ) ) - .dataa(!\op[2]~input_o ), + .dataa(!\op[5]~input_o ), .datab(gnd), .datac(gnd), - .datad(!\op[5]~input_o ), + .datad(!\op[3]~input_o ), .datae(!\op[4]~input_o ), - .dataf(!\op[3]~input_o ), + .dataf(!\op[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -359,11 +359,11 @@ cyclonev_lcell_comb \Equal3~0 ( .shareout()); // synopsys translate_off defparam \Equal3~0 .extended_lut = "off"; -defparam \Equal3~0 .lut_mask = 64'h5500000000000000; +defparam \Equal3~0 .lut_mask = 64'h00000000AA000000; defparam \Equal3~0 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X14_Y1_N24 +// Location: MLABCELL_X14_Y60_N54 cyclonev_lcell_comb \Equal4~0 ( // Equation(s): // \Equal4~0_combout = ( !\op[4]~input_o & ( \op[3]~input_o & ( !\op[5]~input_o ) ) ) @@ -387,17 +387,17 @@ defparam \Equal4~0 .lut_mask = 64'h00000000F0F00000; defparam \Equal4~0 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X14_Y1_N3 +// Location: MLABCELL_X14_Y60_N3 cyclonev_lcell_comb \Equal5~0 ( // Equation(s): // \Equal5~0_combout = ( \op[4]~input_o & ( !\op[5]~input_o ) ) - .dataa(!\op[5]~input_o ), + .dataa(gnd), .datab(gnd), .datac(gnd), .datad(gnd), .datae(!\op[4]~input_o ), - .dataf(gnd), + .dataf(!\op[5]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -407,11 +407,11 @@ cyclonev_lcell_comb \Equal5~0 ( .shareout()); // synopsys translate_off defparam \Equal5~0 .extended_lut = "off"; -defparam \Equal5~0 .lut_mask = 64'h0000AAAA0000AAAA; +defparam \Equal5~0 .lut_mask = 64'h0000FFFF00000000; defparam \Equal5~0 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X55_Y25_N3 +// Location: LABCELL_X27_Y9_N3 cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( // Equation(s): diff --git a/Sumbission/Q1.txt b/Sumbission/Q1.txt new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Sumbission/Q1.txt @@ -0,0 +1 @@ + diff --git a/Sumbission/Q2.txt b/Sumbission/Q2.txt new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Sumbission/Q2.txt @@ -0,0 +1 @@ + diff --git a/Sumbission/Q3.txt b/Sumbission/Q3.txt new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Sumbission/Q3.txt @@ -0,0 +1 @@ + diff --git a/Sumbission/Q4.txt b/Sumbission/Q4.txt new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Sumbission/Q4.txt @@ -0,0 +1 @@ + diff --git a/Sumbission/Q5.txt b/Sumbission/Q5.txt new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Sumbission/Q5.txt @@ -0,0 +1 @@ + diff --git a/Sumbission/Q6.txt b/Sumbission/Q6.txt new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Sumbission/Q6.txt @@ -0,0 +1 @@ +