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Implemented instruction classifier on board (Q6) and added blank submission files (for now)

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TroubleElectrical committed 2026-09-15 20:00:35 +10:00
1 parent 9583abd307
commit c27a04ef73
128 files changed
+1487 -1376
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Quartus/A1_Q6/db/A1_Q6.quiproj.2570.rdr.flock
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Quartus/A1_Q6/db/instruction_classifier.asm.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431609040 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431609041 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:20:08 2026 " "Processing started: Tue Sep 15 10:20:08 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431609041 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789431609041 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789431609041 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789431609707 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789431614462 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "517 " "Peak virtual memory: 517 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431614674 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:14 2026 " "Processing ended: Tue Sep 15 10:20:14 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431614674 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431614674 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431614674 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789431614674 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789466242665 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789466242666 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:57:22 2026 " "Processing started: Tue Sep 15 19:57:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789466242666 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789466242666 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789466242666 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789466243313 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789466247576 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "513 " "Peak virtual memory: 513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466247773 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:57:27 2026 " "Processing ended: Tue Sep 15 19:57:27 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466247773 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466247773 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466247773 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789466247773 ""}
Quartus/A1_Q6/db/instruction_classifier.asm.rdb
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Quartus/A1_Q6/db/instruction_classifier.cmp.bpm
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Quartus/A1_Q6/db/instruction_classifier.cmp.cdb
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Quartus/A1_Q6/db/instruction_classifier.cmp.hdb
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Quartus/A1_Q6/db/instruction_classifier.cmp.idb
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Quartus/A1_Q6/db/instruction_classifier.cmp.logdb
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v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
@@ -29,25 +29,25 @@ IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
IO_RULES_MATRIX,Total Pass,0;0;0;0;0;13;0;0;0;0;0;0;0;7;0;0;0;0;7;0;0;0;0;7;0;13;13;0,
IO_RULES_MATRIX,Total Pass,0;13;13;0;0;13;13;0;0;0;0;0;0;7;0;0;0;0;7;0;0;0;0;7;0;13;13;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,13;13;13;13;13;0;13;13;13;13;13;13;13;6;13;13;13;13;6;13;13;13;13;6;13;0;0;13,
IO_RULES_MATRIX,Total Inapplicable,13;0;0;13;13;0;0;13;13;13;13;13;13;6;13;13;13;13;6;13;13;13;13;6;13;0;0;13,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,R[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,J[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B2[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,I[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,F[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,M[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,R[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,J[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B2[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,I[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,F[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,M[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,28,
IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19,
Quartus/A1_Q6/db/instruction_classifier.cmp.rdb
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Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_0c_fast.hsd
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Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_85c_slow.hsd
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Quartus/A1_Q6/db/instruction_classifier.db_info
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Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Version_Index = 604268800
Creation_Time = Tue Sep 15 10:09:43 2026
Creation_Time = Tue Sep 15 19:51:34 2026
Quartus/A1_Q6/db/instruction_classifier.eda.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431623036 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431623037 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:20:22 2026 " "Processing started: Tue Sep 15 10:20:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431623037 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789431623037 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789431623037 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789431623815 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "instruction_classifier.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/ simulation " "Generated file instruction_classifier.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789431623880 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "659 " "Peak virtual memory: 659 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431623914 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:23 2026 " "Processing ended: Tue Sep 15 10:20:23 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431623914 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431623914 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431623914 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789431623914 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789466256073 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789466256073 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:57:35 2026 " "Processing started: Tue Sep 15 19:57:35 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789466256073 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789466256073 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789466256074 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789466256787 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "instruction_classifier.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/ simulation " "Generated file instruction_classifier.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789466256843 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466256879 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:57:36 2026 " "Processing ended: Tue Sep 15 19:57:36 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466256879 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466256879 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466256879 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789466256879 ""}
Quartus/A1_Q6/db/instruction_classifier.fit.qmsg
+44 -44
View File
@@ -1,44 +1,44 @@
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789431575376 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789431575377 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "instruction_classifier 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"instruction_classifier\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789431575381 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789431575456 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789431575456 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789431575888 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789431575916 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789431575969 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "13 13 " "No exact pin location assignment(s) for 13 pins of 13 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789431576256 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789431583219 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431583296 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789431583298 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789431583299 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789431583299 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789431583299 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789431583299 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789431583299 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789431583299 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789431583300 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789431583300 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431583313 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789431589563 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789431589563 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789431589564 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789431589564 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789431589565 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789431589565 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789431589566 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789431589568 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789431589608 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:04 " "Fitter placement preparation operations ending: elapsed time is 00:00:04" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431593856 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789431595048 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789431595350 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431595351 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789431596250 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789431601801 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789431601801 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789431602005 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789431602005 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789431602005 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431602007 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789431602821 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789431602862 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789431603215 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789431603215 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789431603872 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431606547 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1369 " "Peak virtual memory: 1369 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431607368 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:07 2026 " "Processing ended: Tue Sep 15 10:20:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431607368 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:33 " "Elapsed time: 00:00:33" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431607368 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:49 " "Total CPU time (on all processors): 00:00:49" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431607368 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789431607368 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789466213525 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789466213525 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "instruction_classifier 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"instruction_classifier\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789466213530 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789466213605 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789466213605 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789466214029 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789466214056 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789466214110 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789466220964 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466220984 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789466220988 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789466220988 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789466220988 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789466220989 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789466220989 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789466220989 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789466220989 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789466220990 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789466220990 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466221008 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789466226868 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789466226868 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789466226869 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789466226869 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789466226870 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789466226870 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789466226870 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789466226873 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789466226960 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466227589 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789466227836 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789466228131 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466228132 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789466229079 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y49 X22_Y61 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y49 to location X22_Y61" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y49 to location X22_Y61"} { { 12 { 0 ""} 11 49 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789466235040 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789466235040 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789466235271 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789466235271 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789466235271 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466235273 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789466236216 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789466236248 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789466236603 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789466236603 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789466237318 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789466239936 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789466240231 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1384 " "Peak virtual memory: 1384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466240779 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:57:20 2026 " "Processing ended: Tue Sep 15 19:57:20 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466240779 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466240779 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466240779 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789466240779 ""}
Quartus/A1_Q6/db/instruction_classifier.hier_info
+7 -7
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@@ -26,12 +26,12 @@ op[5] => Equal2.IN1
op[5] => Equal3.IN1
op[5] => Equal4.IN1
op[5] => Equal5.IN1
R[0] <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
B1[0] <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
J[0] <= Equal2.DB_MAX_OUTPUT_PORT_TYPE
B2[0] <= Equal3.DB_MAX_OUTPUT_PORT_TYPE
I[0] <= Equal4.DB_MAX_OUTPUT_PORT_TYPE
F[0] <= Equal5.DB_MAX_OUTPUT_PORT_TYPE
M[0] <= op[5].DB_MAX_OUTPUT_PORT_TYPE
R[0] << Equal0.DB_MAX_OUTPUT_PORT_TYPE
B1[0] << Equal1.DB_MAX_OUTPUT_PORT_TYPE
J[0] << Equal2.DB_MAX_OUTPUT_PORT_TYPE
B2[0] << Equal3.DB_MAX_OUTPUT_PORT_TYPE
I[0] << Equal4.DB_MAX_OUTPUT_PORT_TYPE
F[0] << Equal5.DB_MAX_OUTPUT_PORT_TYPE
M[0] << op[5].DB_MAX_OUTPUT_PORT_TYPE
Quartus/A1_Q6/db/instruction_classifier.map.bpm
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Quartus/A1_Q6/db/instruction_classifier.map.cdb
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Quartus/A1_Q6/db/instruction_classifier.map.qmsg
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@@ -1,11 +1,11 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431562372 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431562373 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:19:22 2026 " "Processing started: Tue Sep 15 10:19:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431562373 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431562373 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431562373 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789431562701 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789431562701 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" { { "Info" "ISGN_ENTITY_NAME" "1 instruction_classifier " "Found entity 1: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789431572260 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431572260 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "instruction_classifier " "Elaborating entity \"instruction_classifier\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789431572408 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789431573138 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789431573508 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789431573508 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789431573553 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789431573553 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789431573553 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789431573553 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431573561 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:19:33 2026 " "Processing ended: Tue Sep 15 10:19:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431573561 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431573561 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431573561 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431573561 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789466200354 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789466200355 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:56:40 2026 " "Processing started: Tue Sep 15 19:56:40 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789466200355 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789466200355 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789466200355 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789466200678 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789466200678 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" { { "Info" "ISGN_ENTITY_NAME" "1 instruction_classifier " "Found entity 1: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789466210547 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789466210547 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "instruction_classifier " "Elaborating entity \"instruction_classifier\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789466210684 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789466211393 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789466211748 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789466211748 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789466211776 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789466211776 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789466211776 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789466211776 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466211784 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:56:51 2026 " "Processing ended: Tue Sep 15 19:56:51 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466211784 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466211784 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466211784 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789466211784 ""}
Quartus/A1_Q6/db/instruction_classifier.map.rdb
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Quartus/A1_Q6/db/instruction_classifier.sta.qmsg
+61 -61
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@@ -1,61 +1,61 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431616218 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431616218 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:20:15 2026 " "Processing started: Tue Sep 15 10:20:15 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431616218 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789431616218 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q6 -c instruction_classifier " "Command: quartus_sta A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789431616219 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789431616277 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789431616764 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789431616764 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431616842 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431616842 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789431617439 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431617439 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431617440 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431617440 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789431617440 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431617440 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789431617441 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789431617448 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789431617448 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617450 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617453 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617454 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617455 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617456 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617457 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789431617459 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789431617506 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789431618682 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431618767 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431618767 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431618767 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431618767 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618768 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618769 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618770 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618771 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618772 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618773 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789431618774 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789431619046 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789431619708 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431619758 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431619758 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431619758 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431619758 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619759 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619760 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619761 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619762 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619763 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789431619765 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431619925 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431619926 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431619926 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431619927 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619929 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619931 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619932 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619934 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619935 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789431621439 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789431621440 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "785 " "Peak virtual memory: 785 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431621463 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:21 2026 " "Processing ended: Tue Sep 15 10:20:21 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431621463 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431621463 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431621463 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789431621463 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789466249262 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789466249262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:57:29 2026 " "Processing started: Tue Sep 15 19:57:29 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789466249262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789466249262 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q6 -c instruction_classifier " "Command: quartus_sta A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789466249263 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789466249320 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789466249788 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789466249788 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466249859 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466249859 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789466250424 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466250424 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789466250424 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789466250425 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789466250425 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789466250425 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789466250426 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789466250430 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789466250430 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250432 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250435 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250436 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250436 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250437 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466250438 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789466250440 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789466250477 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789466251796 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466251871 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789466251871 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789466251872 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789466251872 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251873 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251874 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251875 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251876 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251877 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466251877 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789466251879 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789466252142 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789466252856 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466252911 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789466252911 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789466252911 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789466252911 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252913 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252914 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252915 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252916 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466252916 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789466252918 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789466253066 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789466253066 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789466253066 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789466253067 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253068 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253069 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253070 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253071 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789466253072 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789466254483 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789466254483 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "776 " "Peak virtual memory: 776 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789466254506 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:57:34 2026 " "Processing ended: Tue Sep 15 19:57:34 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789466254506 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789466254506 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789466254506 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789466254506 ""}
Quartus/A1_Q6/db/instruction_classifier.sta.rdb
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Quartus/A1_Q6/db/instruction_classifier.sta_cmp.7_H6_slow_1100mv_85c.tdb
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Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_0c.ddb
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Quartus/A1_Q6/db/instruction_classifier.tmw_info
+2 -2
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@@ -1,7 +1,7 @@
start_full_compilation:s:00:01:03
start_full_compilation:s:00:00:58
start_analysis_synthesis:s:00:00:13-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:34-start_full_compilation
start_fitter:s:00:00:29-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:07-start_full_compilation
start_eda_netlist_writer:s:00:00:02-start_full_compilation
Quartus/A1_Q6/db/instruction_classifier.vpr.ammdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.ammdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.cdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.cdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.hdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.rcfdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.cdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.cdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hdb
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Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrp.hdb
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Quartus/A1_Q6/instruction_classifier.qsf
+22 -2
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@@ -55,7 +55,27 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op
set_location_assignment PIN_AC9 -to op[0]
set_location_assignment PIN_AE10 -to op[1]
set_location_assignment PIN_AD13 -to op[2]
set_location_assignment PIN_AC8 -to op[3]
set_location_assignment PIN_W11 -to op[4]
set_location_assignment PIN_AB10 -to op[5]
set_location_assignment PIN_F7 -to M[0]
set_location_assignment PIN_F6 -to F[0]
set_location_assignment PIN_G6 -to I[0]
set_location_assignment PIN_G7 -to B2[0]
set_location_assignment PIN_J8 -to J[0]
set_location_assignment PIN_J7 -to B1[0]
set_location_assignment PIN_K10 -to R[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Quartus/A1_Q6/instruction_classifier.qws
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Quartus/A1_Q6/output_files/instruction_classifier.asm.rpt
+9 -9
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@@ -1,5 +1,5 @@
Assembler report for instruction_classifier
Tue Sep 15 10:20:14 2026
Tue Sep 15 19:57:27 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Sep 15 10:20:14 2026 ;
; Assembler Status ; Successful - Tue Sep 15 19:57:27 2026 ;
; Revision Name ; instruction_classifier ;
; Top-level Entity Name ; instruction_classifier ;
; Family ; Cyclone V ;
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
+----------------+-------------------------------------+
; Option ; Setting ;
+----------------+-------------------------------------+
; JTAG usercode ; 0x00780971 ;
; Checksum ; 0x00780971 ;
; JTAG usercode ; 0x0078176D ;
; Checksum ; 0x0078176D ;
+----------------+-------------------------------------+
@@ -78,14 +78,14 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:20:08 2026
Info: Processing started: Tue Sep 15 19:57:22 2026
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 517 megabytes
Info: Processing ended: Tue Sep 15 10:20:14 2026
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:06
Info: Peak virtual memory: 513 megabytes
Info: Processing ended: Tue Sep 15 19:57:27 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
Quartus/A1_Q6/output_files/instruction_classifier.done
+1 -1
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@@ -1 +1 @@
Tue Sep 15 10:20:24 2026
Tue Sep 15 19:57:37 2026
Quartus/A1_Q6/output_files/instruction_classifier.eda.rpt
+5 -5
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@@ -1,5 +1,5 @@
EDA Netlist Writer report for instruction_classifier
Tue Sep 15 10:20:23 2026
Tue Sep 15 19:57:36 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:20:23 2026 ;
; EDA Netlist Writer Status ; Successful - Tue Sep 15 19:57:36 2026 ;
; Revision Name ; instruction_classifier ;
; Top-level Entity Name ; instruction_classifier ;
; Family ; Cyclone V ;
@@ -81,13 +81,13 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:20:22 2026
Info: Processing started: Tue Sep 15 19:57:35 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file instruction_classifier.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 659 megabytes
Info: Processing ended: Tue Sep 15 10:20:23 2026
Info: Peak virtual memory: 658 megabytes
Info: Processing ended: Tue Sep 15 19:57:36 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Quartus/A1_Q6/output_files/instruction_classifier.fit.rpt
+163 -172
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@@ -1,5 +1,5 @@
Fitter report for instruction_classifier
Tue Sep 15 10:20:06 2026
Tue Sep 15 19:57:20 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -10,27 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Incremental Compilation Preservation Summary
6. Incremental Compilation Partition Settings
7. Incremental Compilation Placement Preservation
8. Pin-Out File
9. Fitter Resource Usage Summary
10. Fitter Partition Statistics
11. Input Pins
12. Output Pins
13. I/O Bank Usage
14. All Package Pins
15. I/O Assignment Warnings
16. Fitter Resource Utilization by Entity
17. Delay Chain Summary
18. Pad To Core Delay Chain Fanout
19. Routing Usage Summary
20. I/O Rules Summary
21. I/O Rules Details
22. I/O Rules Matrix
23. Fitter Device Options
24. Operating Settings and Conditions
25. Fitter Messages
5. Ignored Assignments
6. Incremental Compilation Preservation Summary
7. Incremental Compilation Partition Settings
8. Incremental Compilation Placement Preservation
9. Pin-Out File
10. Fitter Resource Usage Summary
11. Fitter Partition Statistics
12. Input Pins
13. Output Pins
14. I/O Bank Usage
15. All Package Pins
16. I/O Assignment Warnings
17. Fitter Resource Utilization by Entity
18. Delay Chain Summary
19. Pad To Core Delay Chain Fanout
20. Routing Usage Summary
21. I/O Rules Summary
22. I/O Rules Details
23. I/O Rules Matrix
24. Fitter Device Options
25. Operating Settings and Conditions
26. Fitter Messages
@@ -57,7 +58,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Tue Sep 15 10:20:06 2026 ;
; Fitter Status ; Successful - Tue Sep 15 19:57:20 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; instruction_classifier ;
; Top-level Entity Name ; instruction_classifier ;
@@ -152,10 +153,19 @@ on the Quartus Prime software download page.
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.1% ;
; Processor 2 ; 0.2% ;
+----------------------------+-------------+
+----------------------------------------------------------------------------------------------------+
; Ignored Assignments ;
+--------------+------------------------+--------------+------------+---------------+----------------+
; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
+--------------+------------------------+--------------+------------+---------------+----------------+
; I/O Standard ; instruction_classifier ; ; op ; 1.2 V ; QSF Assignment ;
+--------------+------------------------+--------------+------------+---------------+----------------+
+-------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary ;
+---------------------+-------------------+----------------------------+--------------------------+
@@ -240,7 +250,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; ; ; ;
; Virtual pins ; 0 ; ;
; I/O pins ; 13 / 364 ; 4 % ;
; -- Clock pins ; 1 / 14 ; 7 % ;
; -- Clock pins ; 0 / 14 ; 0 % ;
; -- Dedicated input pins ; 0 / 23 ; 0 % ;
; ; ; ;
; M10K blocks ; 0 / 446 ; 0 % ;
@@ -270,8 +280,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; Channel PLLs ; 0 / 6 ; 0 % ;
; Impedance control blocks ; 0 / 3 ; 0 % ;
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ;
; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ;
; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; ;
; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.3% ; ;
; Maximum fan-out ; 7 ; ;
; Highest non-global fan-out ; 7 ; ;
; Total fan-out ; 46 ; ;
@@ -370,12 +380,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
; op[0] ; AB12 ; 3B ; 14 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
; op[1] ; AB11 ; 3B ; 14 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
; op[2] ; T9 ; 3B ; 10 ; 0 ; 74 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
; op[3] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
; op[4] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
; op[5] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
; op[0] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
; op[1] ; AE10 ; 4A ; 36 ; 0 ; 51 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
; op[2] ; AD13 ; 4A ; 34 ; 0 ; 34 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
; op[3] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
; op[4] ; W11 ; 3B ; 10 ; 0 ; 40 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
; op[5] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
@@ -384,32 +394,32 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
+-------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
; B1[0] ; AC10 ; 3B ; 12 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
; B2[0] ; T13 ; 3B ; 15 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
; F[0] ; Y10 ; 3B ; 15 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
; I[0] ; R11 ; 3B ; 12 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
; J[0] ; T12 ; 3B ; 15 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
; M[0] ; T11 ; 3B ; 12 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
; R[0] ; W10 ; 3B ; 15 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
; B1[0] ; J7 ; 8A ; 12 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; B2[0] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; F[0] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; I[0] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; J[0] ; J8 ; 8A ; 14 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; M[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; R[0] ; K10 ; 8A ; 12 ; 61 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+-------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+----------------------------------------------------------------------------+
; I/O Bank Usage ;
+----------+------------------+---------------+--------------+---------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
+----------+------------------+---------------+--------------+---------------+
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 3B ; 13 / 32 ( 41 % ) ; 2.5V ; -- ; 2.5V ;
; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+----------+------------------+---------------+--------------+---------------+
+---------------------------------------------------------------------------+
; I/O Bank Usage ;
+----------+-----------------+---------------+--------------+---------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
+----------+-----------------+---------------+--------------+---------------+
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 3B ; 4 / 32 ( 13 % ) ; 1.2V ; -- ; 2.5V ;
; 4A ; 2 / 80 ( 3 % ) ; 1.2V ; -- ; 2.5V ;
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 8A ; 7 / 32 ( 22 % ) ; 2.5V ; -- ; 2.5V ;
+----------+-----------------+---------------+--------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -450,7 +460,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA10 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
@@ -460,7 +470,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA20 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
@@ -476,10 +486,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AB10 ; 61 ; 3B ; op[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; AB11 ; 63 ; 3B ; op[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; AB12 ; 65 ; 3B ; op[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AB10 ; 61 ; 3B ; op[5] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AB13 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -500,15 +510,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
; AC8 ; 62 ; 3B ; op[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; AC9 ; 64 ; 3B ; op[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; AC10 ; 59 ; 3B ; B1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; AC8 ; 62 ; 3B ; op[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; AC9 ; 64 ; 3B ; op[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; AC10 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AC16 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -527,17 +537,17 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AD9 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD13 ; 93 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD13 ; 93 ; 4A ; op[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AD15 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AD19 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -554,9 +564,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE10 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE10 ; 94 ; 4A ; op[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AE12 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -566,7 +576,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AE22 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -584,7 +594,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AF15 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -704,8 +714,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; F5 ; 398 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; F6 ; 360 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; F7 ; 366 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; F6 ; 360 ; 8A ; F[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; F7 ; 366 ; 8A ; M[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; F8 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -730,8 +740,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; G3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; G4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
; G5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; G6 ; 362 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; G7 ; 364 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; G6 ; 362 ; 8A ; I[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; G7 ; 364 ; 8A ; B2[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; G8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; G9 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; G10 ; 357 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -783,8 +793,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; J5 ; 399 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
; J6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; J7 ; 370 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; J8 ; 365 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; J7 ; 370 ; 8A ; B1[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; J8 ; 365 ; 8A ; J[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; J10 ; 369 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; J11 ; 289 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -812,7 +822,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; K7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; K8 ; 363 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; K9 ; 361 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; K10 ; 367 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; K10 ; 367 ; 8A ; R[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; K11 ; 305 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -943,7 +953,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; R8 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; R9 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; R10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; R11 ; 60 ; 3B ; I[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; R11 ; 60 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; R13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
; R14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -967,11 +977,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; T6 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; T7 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; T8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; T9 ; 56 ; 3B ; op[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; T9 ; 56 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; T11 ; 58 ; 3B ; M[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; T12 ; 66 ; 3B ; J[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; T13 ; 68 ; 3B ; B2[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; T11 ; 58 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; T12 ; 66 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; T13 ; 68 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; T14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; T16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
@@ -992,7 +1002,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ;
; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; U8 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -1002,7 +1012,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; U18 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
@@ -1021,7 +1031,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; V11 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -1046,11 +1056,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; W7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; W10 ; 69 ; 3B ; R[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W11 ; 57 ; 3B ; op[4] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; W14 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -1072,14 +1082,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; Y7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y10 ; 67 ; 3B ; F[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -1105,25 +1115,6 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
; I[0] ; Incomplete set of assignments ;
; F[0] ; Incomplete set of assignments ;
; M[0] ; Incomplete set of assignments ;
; op[0] ; Incomplete set of assignments ;
; op[1] ; Incomplete set of assignments ;
; op[2] ; Incomplete set of assignments ;
; op[3] ; Incomplete set of assignments ;
; op[4] ; Incomplete set of assignments ;
; op[5] ; Incomplete set of assignments ;
; R[0] ; Missing location assignment ;
; B1[0] ; Missing location assignment ;
; J[0] ; Missing location assignment ;
; B2[0] ; Missing location assignment ;
; I[0] ; Missing location assignment ;
; F[0] ; Missing location assignment ;
; M[0] ; Missing location assignment ;
; op[0] ; Missing location assignment ;
; op[1] ; Missing location assignment ;
; op[2] ; Missing location assignment ;
; op[3] ; Missing location assignment ;
; op[4] ; Missing location assignment ;
; op[5] ; Missing location assignment ;
+----------+-------------------------------+
@@ -1132,7 +1123,7 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------+------------------------+--------------+
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------+------------------------+--------------+
; |instruction_classifier ; 5.0 (5.0) ; 5.0 (5.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 13 ; 0 ; |instruction_classifier ; instruction_classifier ; work ;
; |instruction_classifier ; 4.5 (4.5) ; 5.0 (5.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 13 ; 0 ; |instruction_classifier ; instruction_classifier ; work ;
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------+------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -1149,12 +1140,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; I[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; F[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; M[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; op[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; op[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; op[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; op[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; op[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; op[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; op[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; op[5] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+-------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
@@ -1164,17 +1155,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; op[0] ; ; ;
; - Equal0~0 ; 0 ; 0 ;
; - Equal1~0 ; 0 ; 0 ;
; - Equal0~0 ; 1 ; 0 ;
; - Equal1~0 ; 1 ; 0 ;
; op[1] ; ; ;
; - Equal0~0 ; 1 ; 0 ;
; - Equal1~0 ; 1 ; 0 ;
; - Equal2~0 ; 1 ; 0 ;
; op[2] ; ; ;
; - Equal0~0 ; 1 ; 0 ;
; - Equal1~0 ; 1 ; 0 ;
; - Equal2~0 ; 1 ; 0 ;
; - Equal3~0 ; 1 ; 0 ;
; - Equal0~0 ; 0 ; 0 ;
; - Equal1~0 ; 0 ; 0 ;
; - Equal2~0 ; 0 ; 0 ;
; - Equal3~0 ; 0 ; 0 ;
; op[3] ; ; ;
; - Equal0~0 ; 1 ; 0 ;
; - Equal1~0 ; 1 ; 0 ;
@@ -1189,13 +1180,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; - Equal4~0 ; 1 ; 0 ;
; - Equal5~0 ; 1 ; 0 ;
; op[5] ; ; ;
; - Equal0~0 ; 1 ; 0 ;
; - Equal1~0 ; 1 ; 0 ;
; - Equal2~0 ; 1 ; 0 ;
; - Equal3~0 ; 1 ; 0 ;
; - Equal4~0 ; 1 ; 0 ;
; - Equal5~0 ; 1 ; 0 ;
; - M[0]~output ; 1 ; 0 ;
; - Equal0~0 ; 0 ; 0 ;
; - Equal1~0 ; 0 ; 0 ;
; - Equal2~0 ; 0 ; 0 ;
; - Equal3~0 ; 0 ; 0 ;
; - Equal4~0 ; 0 ; 0 ;
; - Equal5~0 ; 0 ; 0 ;
; - M[0]~output ; 0 ; 0 ;
+---------------------+-------------------+---------+
@@ -1205,8 +1196,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Routing Resource Type ; Usage ;
+------------------------------+------------------------+
; Block interconnects ; 13 / 217,884 ( < 1 % ) ;
; C12 interconnects ; 0 / 10,080 ( 0 % ) ;
; C2 interconnects ; 9 / 87,208 ( < 1 % ) ;
; C12 interconnects ; 31 / 10,080 ( < 1 % ) ;
; C2 interconnects ; 7 / 87,208 ( < 1 % ) ;
; C4 interconnects ; 4 / 41,360 ( < 1 % ) ;
; DQS bus muxes ; 0 / 21 ( 0 % ) ;
; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ;
@@ -1216,10 +1207,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
; Local interconnects ; 0 / 58,160 ( 0 % ) ;
; Quadrant clocks ; 0 / 88 ( 0 % ) ;
; R14 interconnects ; 0 / 9,228 ( 0 % ) ;
; R14/C12 interconnect drivers ; 0 / 15,096 ( 0 % ) ;
; R14 interconnects ; 2 / 9,228 ( < 1 % ) ;
; R14/C12 interconnect drivers ; 27 / 15,096 ( < 1 % ) ;
; R3 interconnects ; 6 / 94,896 ( < 1 % ) ;
; R6 interconnects ; 2 / 194,640 ( < 1 % ) ;
; R6 interconnects ; 3 / 194,640 ( < 1 % ) ;
; Spine clocks ; 0 / 180 ( 0 % ) ;
; Wire stub REs ; 0 / 11,606 ( 0 % ) ;
+------------------------------+------------------------+
@@ -1231,10 +1222,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; I/O Rules Statistic ; Total ;
+----------------------------------+-------+
; Total I/O Rules ; 28 ;
; Number of I/O Rules Passed ; 6 ;
; Number of I/O Rules Passed ; 9 ;
; Number of I/O Rules Failed ; 0 ;
; Number of I/O Rules Unchecked ; 0 ;
; Number of I/O Rules Inapplicable ; 22 ;
; Number of I/O Rules Inapplicable ; 19 ;
+----------------------------------+-------+
@@ -1244,12 +1235,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
@@ -1275,29 +1266,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 13 ; 13 ; 0 ;
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Inapplicable ; 13 ; 13 ; 13 ; 13 ; 13 ; 0 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 0 ; 0 ; 13 ;
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; R[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; J[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B2[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; I[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; F[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; M[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix ;
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
; Total Pass ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 13 ; 13 ; 0 ;
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Inapplicable ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 0 ; 0 ; 13 ;
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; R[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; J[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B2[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; I[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; F[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; M[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+------------------------------------------------------------------------------------------------+
@@ -1354,13 +1345,12 @@ Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 13 pins of 13 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Info (184020): Starting Fitter periphery placement operations
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176219): No registers were packed into other blocks
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07
Critical Warning (332012): Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
@@ -1370,27 +1360,28 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (170189): Fitter placement preparation operations beginning
Info (14951): The Fitter is using Advanced Physical Optimization.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:04
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y49 to location X22_Y61
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.08 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 1369 megabytes
Info: Processing ended: Tue Sep 15 10:20:07 2026
Info: Elapsed time: 00:00:33
Info: Total CPU time (on all processors): 00:00:49
Info: Peak virtual memory: 1384 megabytes
Info: Processing ended: Tue Sep 15 19:57:20 2026
Info: Elapsed time: 00:00:28
Info: Total CPU time (on all processors): 00:00:39
Quartus/A1_Q6/output_files/instruction_classifier.fit.summary
+1 -1
View File
@@ -1,4 +1,4 @@
Fitter Status : Successful - Tue Sep 15 10:20:06 2026
Fitter Status : Successful - Tue Sep 15 19:57:20 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : instruction_classifier
Top-level Entity Name : instruction_classifier
Quartus/A1_Q6/output_files/instruction_classifier.flow.rpt
+10 -10
View File
@@ -1,5 +1,5 @@
Flow report for instruction_classifier
Tue Sep 15 10:20:23 2026
Tue Sep 15 19:57:36 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Sep 15 10:20:23 2026 ;
; Flow Status ; Successful - Tue Sep 15 19:57:36 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; instruction_classifier ;
; Top-level Entity Name ; instruction_classifier ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+------------------------+
; Option ; Setting ;
+-------------------+------------------------+
; Start date & time ; 09/15/2026 10:19:22 ;
; Start date & time ; 09/15/2026 19:56:40 ;
; Main task ; Compilation ;
; Revision Name ; instruction_classifier ;
+-------------------+------------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 253029099468756.178943156207722 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 268883478169649.178946620008468 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 413 MB ; 00:00:26 ;
; Fitter ; 00:00:32 ; 1.0 ; 1369 MB ; 00:00:48 ;
; Assembler ; 00:00:06 ; 1.0 ; 517 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 785 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 659 MB ; 00:00:01 ;
; Total ; 00:00:56 ; -- ; -- ; 00:01:26 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ;
; Fitter ; 00:00:28 ; 1.0 ; 1384 MB ; 00:00:39 ;
; Assembler ; 00:00:05 ; 1.0 ; 513 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 776 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:00:50 ; -- ; -- ; 00:01:17 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
Quartus/A1_Q6/output_files/instruction_classifier.map.rpt
+6 -6
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for instruction_classifier
Tue Sep 15 10:19:33 2026
Tue Sep 15 19:56:51 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -43,7 +43,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:19:33 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:56:51 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; instruction_classifier ;
; Top-level Entity Name ; instruction_classifier ;
@@ -261,7 +261,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:19:22 2026
Info: Processing started: Tue Sep 15 19:56:40 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
@@ -276,9 +276,9 @@ Info (21057): Implemented 19 device resources after synthesis - the final resour
Info (21059): Implemented 7 output pins
Info (21061): Implemented 6 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 430 megabytes
Info: Processing ended: Tue Sep 15 10:19:33 2026
Info: Peak virtual memory: 436 megabytes
Info: Processing ended: Tue Sep 15 19:56:51 2026
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:26
Info: Total CPU time (on all processors): 00:00:27
Quartus/A1_Q6/output_files/instruction_classifier.map.summary
+1 -1
View File
@@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Tue Sep 15 10:19:33 2026
Analysis & Synthesis Status : Successful - Tue Sep 15 19:56:51 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : instruction_classifier
Top-level Entity Name : instruction_classifier
Quartus/A1_Q6/output_files/instruction_classifier.pin
+39 -39
View File
@@ -29,8 +29,8 @@
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 3A: 2.5V
-- Bank 3B: 2.5V
-- Bank 4A: 2.5V
-- Bank 3B: 1.2V
-- Bank 4A: 1.2V
-- Bank 5A: 2.5V
-- Bank 5B: 2.5V
-- Bank 6A: 2.5V
@@ -109,7 +109,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A :
VCC_AUX : AA8 : power : : 2.5V : :
VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCIO3B : AA10 : power : : 2.5V : 3B :
VCCIO3B : AA10 : power : : 1.2V : 3B :
VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A :
NC : AA12 : : : : :
VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A :
@@ -119,7 +119,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : :
VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A :
VCCIO4A : AA20 : power : : 2.5V : 4A :
VCCIO4A : AA20 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A :
@@ -135,10 +135,10 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : :
NC : AB7 : : : : :
GND : AB8 : gnd : : : :
VCCPD3A : AB9 : power : : 2.5V : 3A :
op[5] : AB10 : input : 2.5 V : : 3B : N
op[1] : AB11 : input : 2.5 V : : 3B : N
op[0] : AB12 : input : 2.5 V : : 3B : N
VCCIO4A : AB13 : power : : 2.5V : 4A :
op[5] : AB10 : input : 1.2 V : : 3B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
VCCIO4A : AB13 : power : : 1.2V : 4A :
VCC_AUX : AB14 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A :
@@ -159,15 +159,15 @@ GXB_NC : AC4 : : :
GND : AC5 : gnd : : : :
VCCIO3A : AC6 : power : : 2.5V : 3A :
VREFB3AN0 : AC7 : power : : : 3A :
op[3] : AC8 : input : 2.5 V : : 3B : N
op[4] : AC9 : input : 2.5 V : : 3B : N
B1[0] : AC10 : output : 2.5 V : : 3B : N
op[3] : AC8 : input : 1.2 V : : 3B : Y
op[0] : AC9 : input : 1.2 V : : 3B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B :
GND : AC11 : gnd : : : :
VREFB3BN0 : AC12 : power : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A :
VCCIO4A : AC16 : power : : 2.5V : 4A :
VCCIO4A : AC16 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A :
@@ -186,17 +186,17 @@ AS_DATA1, DATA1 : AD5 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B :
VCCIO3B : AD9 : power : : 2.5V : 3B :
VCCIO3B : AD9 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 4A :
op[2] : AD13 : input : 1.2 V : : 4A : Y
GND : AD14 : gnd : : : :
VREFB4AN0 : AD15 : power : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A :
VCCIO4A : AD19 : power : : 2.5V : 4A :
VCCIO4A : AD19 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A :
@@ -213,9 +213,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : :
GND : AE7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A :
op[1] : AE10 : input : 1.2 V : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A :
VCCIO4A : AE12 : power : : 2.5V : 4A :
VCCIO4A : AE12 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A :
@@ -225,7 +225,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A :
VCCIO4A : AE22 : power : : 2.5V : 4A :
VCCIO4A : AE22 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A :
@@ -243,7 +243,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A :
VCCIO4A : AF15 : power : : 2.5V : 4A :
VCCIO4A : AF15 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
@@ -363,8 +363,8 @@ NC : F2 : : :
GND : F3 : gnd : : : :
GND : F4 : gnd : : : :
nCONFIG : F5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A :
F[0] : F6 : output : 2.5 V : : 8A : Y
M[0] : F7 : output : 2.5 V : : 8A : Y
VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A :
GND : F10 : gnd : : : :
@@ -389,8 +389,8 @@ GND : G2 : gnd : :
NC : G3 : : : : :
NC : G4 : : : : :
GND : G5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
I[0] : G6 : output : 2.5 V : : 8A : Y
B2[0] : G7 : output : 2.5 V : : 8A : Y
VCCIO8A : G8 : power : : 2.5V : 8A :
VCC_AUX : G9 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
@@ -442,8 +442,8 @@ VCCL_GXBL : J3 : power : : 1.1V
GND : J4 : gnd : : : :
MSEL4 : J5 : : : : 9A :
VCCA_FPLL : J6 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 8A :
B1[0] : J7 : output : 2.5 V : : 8A : Y
J[0] : J8 : output : 2.5 V : : 8A : Y
GND : J9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7A :
@@ -471,7 +471,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : :
VCCIO8A : K7 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 8A :
R[0] : K10 : output : 2.5 V : : 8A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 7A :
GND : K12 : gnd : : : :
GND : K13 : gnd : : : :
@@ -602,7 +602,7 @@ GND : R7 : gnd : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3A :
I[0] : R11 : output : 2.5 V : : 3B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3B :
GND : R12 : gnd : : : :
VCC : R13 : power : : 1.1V : :
GND : R14 : gnd : : : :
@@ -626,11 +626,11 @@ GND : T5 : gnd : :
TDI : T6 : input : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A :
op[2] : T9 : input : 2.5 V : : 3B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3B :
GND : T10 : gnd : : : :
M[0] : T11 : output : 2.5 V : : 3B : N
J[0] : T12 : output : 2.5 V : : 3B : N
B2[0] : T13 : output : 2.5 V : : 3B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B :
VCC : T14 : power : : 1.1V : :
GND : T15 : gnd : : : :
VCC : T16 : power : : 1.1V : :
@@ -651,7 +651,7 @@ GND : U4 : gnd : :
VCCE_GXBL : U5 : power : : 1.1V : :
AS_DATA3, DATA3 : U6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A :
VCCIO3B : U8 : power : : 2.5V : 3B :
VCCIO3B : U8 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
@@ -661,7 +661,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A :
VCCIO4A : U18 : power : : 2.5V : 4A :
VCCIO4A : U18 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A :
VCCPD5A : U21 : power : : 2.5V : 5A :
@@ -680,7 +680,7 @@ TDO : V7 : output : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B :
VCCIO3B : V11 : power : : 2.5V : 3B :
VCCIO3B : V11 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A :
@@ -705,11 +705,11 @@ GND : W6 : : :
VCCA_FPLL : W7 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
GND : W9 : gnd : : : :
R[0] : W10 : output : 2.5 V : : 3B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B :
op[4] : W11 : input : 1.2 V : : 3B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
VCCIO4A : W14 : power : : 2.5V : 4A :
VCCIO4A : W14 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
@@ -731,14 +731,14 @@ nCSO, DATA4 : Y6 : : :
VCCIO3A : Y7 : power : : 2.5V : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A :
F[0] : Y10 : output : 2.5 V : : 3B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B :
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A :
VCCIO4A : Y17 : power : : 2.5V : 4A :
VCCIO4A : Y17 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A :
Quartus/A1_Q6/output_files/instruction_classifier.sof
BIN
View File
Binary file not shown.
Quartus/A1_Q6/output_files/instruction_classifier.sta.rpt
+31 -31
View File
@@ -1,5 +1,5 @@
Timing Analyzer report for instruction_classifier
Tue Sep 15 10:20:21 2026
Tue Sep 15 19:57:34 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -305,12 +305,12 @@ No synchronizer chains to report.
+-------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------+--------------+-----------------+-----------------+
; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
; op[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
; op[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
; op[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
; op[0] ; 1.2 V ; 960 ps ; 960 ps ;
; op[1] ; 1.2 V ; 960 ps ; 960 ps ;
; op[2] ; 1.2 V ; 960 ps ; 960 ps ;
; op[3] ; 1.2 V ; 960 ps ; 960 ps ;
; op[4] ; 1.2 V ; 960 ps ; 960 ps ;
; op[5] ; 1.2 V ; 960 ps ; 960 ps ;
+-------+--------------+-----------------+-----------------+
@@ -319,13 +319,13 @@ No synchronizer chains to report.
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
@@ -334,13 +334,13 @@ No synchronizer chains to report.
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
@@ -349,13 +349,13 @@ No synchronizer chains to report.
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
@@ -364,13 +364,13 @@ No synchronizer chains to report.
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
+-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
@@ -470,7 +470,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:20:15 2026
Info: Processing started: Tue Sep 15 19:57:29 2026
Info: Command: quartus_sta A1_Q6 -c instruction_classifier
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -530,9 +530,9 @@ Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 785 megabytes
Info: Processing ended: Tue Sep 15 10:20:21 2026
Info: Elapsed time: 00:00:06
Info: Peak virtual memory: 776 megabytes
Info: Processing ended: Tue Sep 15 19:57:34 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
Quartus/A1_Q6/simulation/questa/instruction_classifier.svo
+120 -120
View File
@@ -17,7 +17,7 @@
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
// DATE "09/15/2026 10:20:23"
// DATE "09/15/2026 19:57:36"
//
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
@@ -38,29 +38,29 @@ module instruction_classifier (
I,
F,
M);
input logic [5:0] op ;
output logic [0:0] R ;
output logic [0:0] B1 ;
output logic [0:0] J ;
output logic [0:0] B2 ;
output logic [0:0] I ;
output logic [0:0] F ;
output logic [0:0] M ;
input [5:0] op;
output [0:0] R;
output [0:0] B1;
output [0:0] J;
output [0:0] B2;
output [0:0] I;
output [0:0] F;
output [0:0] M;
// Design Ports Information
// R[0] => Location: PIN_W10, I/O Standard: 2.5 V, Current Strength: Default
// B1[0] => Location: PIN_AC10, I/O Standard: 2.5 V, Current Strength: Default
// J[0] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default
// B2[0] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default
// I[0] => Location: PIN_R11, I/O Standard: 2.5 V, Current Strength: Default
// F[0] => Location: PIN_Y10, I/O Standard: 2.5 V, Current Strength: Default
// M[0] => Location: PIN_T11, I/O Standard: 2.5 V, Current Strength: Default
// op[0] => Location: PIN_AB12, I/O Standard: 2.5 V, Current Strength: Default
// op[1] => Location: PIN_AB11, I/O Standard: 2.5 V, Current Strength: Default
// op[2] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default
// op[3] => Location: PIN_AC8, I/O Standard: 2.5 V, Current Strength: Default
// op[4] => Location: PIN_AC9, I/O Standard: 2.5 V, Current Strength: Default
// op[5] => Location: PIN_AB10, I/O Standard: 2.5 V, Current Strength: Default
// R[0] => Location: PIN_K10, I/O Standard: 2.5 V, Current Strength: Default
// B1[0] => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default
// J[0] => Location: PIN_J8, I/O Standard: 2.5 V, Current Strength: Default
// B2[0] => Location: PIN_G7, I/O Standard: 2.5 V, Current Strength: Default
// I[0] => Location: PIN_G6, I/O Standard: 2.5 V, Current Strength: Default
// F[0] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default
// M[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default
// op[0] => Location: PIN_AC9, I/O Standard: 1.2 V, Current Strength: Default
// op[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default
// op[2] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default
// op[3] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default
// op[4] => Location: PIN_W11, I/O Standard: 1.2 V, Current Strength: Default
// op[5] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default
wire gnd;
@@ -75,12 +75,12 @@ tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \op[5]~input_o ;
wire \op[0]~input_o ;
wire \op[2]~input_o ;
wire \op[1]~input_o ;
wire \op[4]~input_o ;
wire \op[3]~input_o ;
wire \op[0]~input_o ;
wire \op[5]~input_o ;
wire \op[2]~input_o ;
wire \op[4]~input_o ;
wire \op[1]~input_o ;
wire \Equal0~0_combout ;
wire \Equal1~0_combout ;
wire \Equal2~0_combout ;
@@ -89,7 +89,7 @@ wire \Equal4~0_combout ;
wire \Equal5~0_combout ;
// Location: IOOBUF_X15_Y0_N36
// Location: IOOBUF_X12_Y61_N2
cyclonev_io_obuf \R[0]~output (
.i(\Equal0~0_combout ),
.oe(vcc),
@@ -105,7 +105,7 @@ defparam \R[0]~output .open_drain_output = "false";
defparam \R[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X12_Y0_N53
// Location: IOOBUF_X12_Y61_N53
cyclonev_io_obuf \B1[0]~output (
.i(\Equal1~0_combout ),
.oe(vcc),
@@ -121,7 +121,7 @@ defparam \B1[0]~output .open_drain_output = "false";
defparam \B1[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X15_Y0_N19
// Location: IOOBUF_X14_Y61_N19
cyclonev_io_obuf \J[0]~output (
.i(\Equal2~0_combout ),
.oe(vcc),
@@ -137,7 +137,7 @@ defparam \J[0]~output .open_drain_output = "false";
defparam \J[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X15_Y0_N2
// Location: IOOBUF_X14_Y61_N36
cyclonev_io_obuf \B2[0]~output (
.i(\Equal3~0_combout ),
.oe(vcc),
@@ -153,7 +153,7 @@ defparam \B2[0]~output .open_drain_output = "false";
defparam \B2[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X12_Y0_N2
// Location: IOOBUF_X15_Y61_N53
cyclonev_io_obuf \I[0]~output (
.i(\Equal4~0_combout ),
.oe(vcc),
@@ -169,7 +169,7 @@ defparam \I[0]~output .open_drain_output = "false";
defparam \I[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X15_Y0_N53
// Location: IOOBUF_X15_Y61_N36
cyclonev_io_obuf \F[0]~output (
.i(\Equal5~0_combout ),
.oe(vcc),
@@ -185,7 +185,7 @@ defparam \F[0]~output .open_drain_output = "false";
defparam \F[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X12_Y0_N19
// Location: IOOBUF_X14_Y61_N53
cyclonev_io_obuf \M[0]~output (
.i(\op[5]~input_o ),
.oe(vcc),
@@ -201,61 +201,6 @@ defparam \M[0]~output .open_drain_output = "false";
defparam \M[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOIBUF_X12_Y0_N35
cyclonev_io_ibuf \op[5]~input (
.i(op[5]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[5]~input_o ));
// synopsys translate_off
defparam \op[5]~input .bus_hold = "false";
defparam \op[5]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X14_Y0_N1
cyclonev_io_ibuf \op[0]~input (
.i(op[0]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[0]~input_o ));
// synopsys translate_off
defparam \op[0]~input .bus_hold = "false";
defparam \op[0]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X10_Y0_N75
cyclonev_io_ibuf \op[2]~input (
.i(op[2]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[2]~input_o ));
// synopsys translate_off
defparam \op[2]~input .bus_hold = "false";
defparam \op[2]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X14_Y0_N18
cyclonev_io_ibuf \op[1]~input (
.i(op[1]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[1]~input_o ));
// synopsys translate_off
defparam \op[1]~input .bus_hold = "false";
defparam \op[1]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X14_Y0_N35
cyclonev_io_ibuf \op[4]~input (
.i(op[4]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[4]~input_o ));
// synopsys translate_off
defparam \op[4]~input .bus_hold = "false";
defparam \op[4]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X14_Y0_N52
cyclonev_io_ibuf \op[3]~input (
.i(op[3]),
@@ -267,17 +212,72 @@ defparam \op[3]~input .bus_hold = "false";
defparam \op[3]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: MLABCELL_X14_Y1_N30
// Location: IOIBUF_X14_Y0_N35
cyclonev_io_ibuf \op[0]~input (
.i(op[0]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[0]~input_o ));
// synopsys translate_off
defparam \op[0]~input .bus_hold = "false";
defparam \op[0]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X12_Y0_N35
cyclonev_io_ibuf \op[5]~input (
.i(op[5]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[5]~input_o ));
// synopsys translate_off
defparam \op[5]~input .bus_hold = "false";
defparam \op[5]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X34_Y0_N35
cyclonev_io_ibuf \op[2]~input (
.i(op[2]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[2]~input_o ));
// synopsys translate_off
defparam \op[2]~input .bus_hold = "false";
defparam \op[2]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X10_Y0_N41
cyclonev_io_ibuf \op[4]~input (
.i(op[4]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[4]~input_o ));
// synopsys translate_off
defparam \op[4]~input .bus_hold = "false";
defparam \op[4]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X36_Y0_N52
cyclonev_io_ibuf \op[1]~input (
.i(op[1]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[1]~input_o ));
// synopsys translate_off
defparam \op[1]~input .bus_hold = "false";
defparam \op[1]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: MLABCELL_X14_Y60_N30
cyclonev_lcell_comb \Equal0~0 (
// Equation(s):
// \Equal0~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (!\op[0]~input_o & (!\op[2]~input_o & !\op[1]~input_o ))) ) ) )
// \Equal0~0_combout = ( !\op[4]~input_o & ( !\op[1]~input_o & ( (!\op[3]~input_o & (!\op[0]~input_o & (!\op[5]~input_o & !\op[2]~input_o ))) ) ) )
.dataa(!\op[5]~input_o ),
.dataa(!\op[3]~input_o ),
.datab(!\op[0]~input_o ),
.datac(!\op[2]~input_o ),
.datad(!\op[1]~input_o ),
.datac(!\op[5]~input_o ),
.datad(!\op[2]~input_o ),
.datae(!\op[4]~input_o ),
.dataf(!\op[3]~input_o ),
.dataf(!\op[1]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
@@ -291,17 +291,17 @@ defparam \Equal0~0 .lut_mask = 64'h8000000000000000;
defparam \Equal0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y1_N6
// Location: MLABCELL_X14_Y60_N6
cyclonev_lcell_comb \Equal1~0 (
// Equation(s):
// \Equal1~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (\op[0]~input_o & (!\op[2]~input_o & !\op[1]~input_o ))) ) ) )
// \Equal1~0_combout = ( !\op[4]~input_o & ( !\op[1]~input_o & ( (!\op[3]~input_o & (\op[0]~input_o & (!\op[5]~input_o & !\op[2]~input_o ))) ) ) )
.dataa(!\op[5]~input_o ),
.dataa(!\op[3]~input_o ),
.datab(!\op[0]~input_o ),
.datac(!\op[2]~input_o ),
.datad(!\op[1]~input_o ),
.datac(!\op[5]~input_o ),
.datad(!\op[2]~input_o ),
.datae(!\op[4]~input_o ),
.dataf(!\op[3]~input_o ),
.dataf(!\op[1]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
@@ -315,17 +315,17 @@ defparam \Equal1~0 .lut_mask = 64'h2000000000000000;
defparam \Equal1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y1_N42
// Location: MLABCELL_X14_Y60_N12
cyclonev_lcell_comb \Equal2~0 (
// Equation(s):
// \Equal2~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (\op[1]~input_o & !\op[2]~input_o )) ) ) )
// \Equal2~0_combout = ( !\op[4]~input_o & ( \op[1]~input_o & ( (!\op[3]~input_o & (!\op[2]~input_o & !\op[5]~input_o )) ) ) )
.dataa(!\op[5]~input_o ),
.datab(!\op[1]~input_o ),
.datac(!\op[2]~input_o ),
.dataa(!\op[3]~input_o ),
.datab(!\op[2]~input_o ),
.datac(!\op[5]~input_o ),
.datad(gnd),
.datae(!\op[4]~input_o ),
.dataf(!\op[3]~input_o ),
.dataf(!\op[1]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
@@ -335,21 +335,21 @@ cyclonev_lcell_comb \Equal2~0 (
.shareout());
// synopsys translate_off
defparam \Equal2~0 .extended_lut = "off";
defparam \Equal2~0 .lut_mask = 64'h2020000000000000;
defparam \Equal2~0 .lut_mask = 64'h0000000080800000;
defparam \Equal2~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y1_N51
// Location: MLABCELL_X14_Y60_N51
cyclonev_lcell_comb \Equal3~0 (
// Equation(s):
// \Equal3~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (\op[2]~input_o & !\op[5]~input_o ) ) ) )
// \Equal3~0_combout = ( !\op[4]~input_o & ( \op[2]~input_o & ( (!\op[5]~input_o & !\op[3]~input_o ) ) ) )
.dataa(!\op[2]~input_o ),
.dataa(!\op[5]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(!\op[5]~input_o ),
.datad(!\op[3]~input_o ),
.datae(!\op[4]~input_o ),
.dataf(!\op[3]~input_o ),
.dataf(!\op[2]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
@@ -359,11 +359,11 @@ cyclonev_lcell_comb \Equal3~0 (
.shareout());
// synopsys translate_off
defparam \Equal3~0 .extended_lut = "off";
defparam \Equal3~0 .lut_mask = 64'h5500000000000000;
defparam \Equal3~0 .lut_mask = 64'h00000000AA000000;
defparam \Equal3~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y1_N24
// Location: MLABCELL_X14_Y60_N54
cyclonev_lcell_comb \Equal4~0 (
// Equation(s):
// \Equal4~0_combout = ( !\op[4]~input_o & ( \op[3]~input_o & ( !\op[5]~input_o ) ) )
@@ -387,17 +387,17 @@ defparam \Equal4~0 .lut_mask = 64'h00000000F0F00000;
defparam \Equal4~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y1_N3
// Location: MLABCELL_X14_Y60_N3
cyclonev_lcell_comb \Equal5~0 (
// Equation(s):
// \Equal5~0_combout = ( \op[4]~input_o & ( !\op[5]~input_o ) )
.dataa(!\op[5]~input_o ),
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\op[4]~input_o ),
.dataf(gnd),
.dataf(!\op[5]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
@@ -407,11 +407,11 @@ cyclonev_lcell_comb \Equal5~0 (
.shareout());
// synopsys translate_off
defparam \Equal5~0 .extended_lut = "off";
defparam \Equal5~0 .lut_mask = 64'h0000AAAA0000AAAA;
defparam \Equal5~0 .lut_mask = 64'h0000FFFF00000000;
defparam \Equal5~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X55_Y25_N3
// Location: LABCELL_X27_Y9_N3
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):