Implemented instruction classifier on board (Q6) and added blank submission files (for now)
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@@ -1,5 +1,5 @@
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Assembler report for shifter
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Tue Sep 15 19:39:33 2026
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Tue Sep 15 19:49:30 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
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+---------------------------------------------------------------+
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; Assembler Summary ;
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+-----------------------+---------------------------------------+
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||||
; Assembler Status ; Successful - Tue Sep 15 19:39:33 2026 ;
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; Assembler Status ; Successful - Tue Sep 15 19:49:30 2026 ;
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; Revision Name ; shifter ;
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; Top-level Entity Name ; shifter ;
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; Family ; Cyclone V ;
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@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
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+----------------+----------------------+
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; Option ; Setting ;
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+----------------+----------------------+
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; JTAG usercode ; 0x007896D6 ;
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; Checksum ; 0x007896D6 ;
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; JTAG usercode ; 0x0078977F ;
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; Checksum ; 0x0078977F ;
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+----------------+----------------------+
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@@ -78,14 +78,14 @@ on the Quartus Prime software download page.
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Info: *******************************************************************
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Info: Running Quartus Prime Assembler
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||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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Info: Processing started: Tue Sep 15 19:39:27 2026
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Info: Processing started: Tue Sep 15 19:49:24 2026
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (115030): Assembler is generating device programming files
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Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 507 megabytes
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Info: Processing ended: Tue Sep 15 19:39:33 2026
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Info: Peak virtual memory: 518 megabytes
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Info: Processing ended: Tue Sep 15 19:49:30 2026
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Info: Elapsed time: 00:00:06
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Info: Total CPU time (on all processors): 00:00:06
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Info: Total CPU time (on all processors): 00:00:05
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@@ -1 +1 @@
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Tue Sep 15 19:39:44 2026
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Tue Sep 15 19:49:40 2026
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@@ -1,5 +1,5 @@
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EDA Netlist Writer report for shifter
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Tue Sep 15 19:39:43 2026
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Tue Sep 15 19:49:39 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Tue Sep 15 19:39:43 2026 ;
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; EDA Netlist Writer Status ; Successful - Tue Sep 15 19:49:39 2026 ;
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; Revision Name ; shifter ;
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; Top-level Entity Name ; shifter ;
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; Family ; Cyclone V ;
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@@ -81,14 +81,14 @@ on the Quartus Prime software download page.
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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Info: Processing started: Tue Sep 15 19:39:42 2026
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Info: Processing started: Tue Sep 15 19:49:38 2026
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (204019): Generated file shifter.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/" for EDA simulation tool
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Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 666 megabytes
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Info: Processing ended: Tue Sep 15 19:39:44 2026
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Info: Elapsed time: 00:00:02
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Info: Processing ended: Tue Sep 15 19:49:39 2026
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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@@ -1,5 +1,5 @@
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Fitter report for shifter
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Tue Sep 15 19:39:25 2026
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Tue Sep 15 19:49:22 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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@@ -58,7 +58,7 @@ on the Quartus Prime software download page.
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+-----------------------------------------------------------------------------------+
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; Fitter Summary ;
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+---------------------------------+-------------------------------------------------+
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; Fitter Status ; Successful - Tue Sep 15 19:39:25 2026 ;
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; Fitter Status ; Successful - Tue Sep 15 19:49:22 2026 ;
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; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
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; Revision Name ; shifter ;
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; Top-level Entity Name ; shifter ;
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@@ -390,8 +390,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; A[3] ; Y16 ; 4A ; 46 ; 0 ; 17 ; 15 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; B[0] ; AD13 ; 4A ; 34 ; 0 ; 34 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; B[1] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; B[2] ; AF6 ; 3B ; 21 ; 0 ; 51 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; Fitter ; no ;
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; B[3] ; AE6 ; 3B ; 21 ; 0 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; Fitter ; no ;
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; B[2] ; W11 ; 3B ; 10 ; 0 ; 40 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; B[3] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; C[0] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 10 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; C[1] ; AE10 ; 4A ; 36 ; 0 ; 51 ; 10 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; op[0] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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@@ -494,7 +494,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
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; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; AB10 ; 61 ; 3B ; B[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
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; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; AB13 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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@@ -568,7 +568,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
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; AE4 ; 23 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
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; AE5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; AE6 ; 85 ; 3B ; B[3] ; input ; 1.2 V ; ; Column I/O ; N ; no ; Off ;
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; AE6 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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@@ -593,7 +593,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; AF5 ; 37 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
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; AF6 ; 83 ; 3B ; B[2] ; input ; 1.2 V ; ; Column I/O ; N ; no ; Off ;
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; AF6 ; 83 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; AF7 ; 80 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; AF8 ; 78 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; AF9 ; 75 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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@@ -1065,7 +1065,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; W11 ; 57 ; 3B ; B[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
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; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; W14 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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@@ -1120,8 +1120,6 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
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; OUT_1[1] ; Incomplete set of assignments ;
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; OUT_1[2] ; Incomplete set of assignments ;
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; OUT_1[3] ; Incomplete set of assignments ;
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; B[2] ; Missing location assignment ;
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; B[3] ; Missing location assignment ;
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+----------+-------------------------------+
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@@ -1146,16 +1144,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
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; A[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
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; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
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; op[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
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; op[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
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; op[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
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; C[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
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; C[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
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; C[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
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; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
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; B[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
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; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
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; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
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; B[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
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; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
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; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
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; A[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
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; A[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
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+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
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@@ -1185,14 +1183,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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; - Mux1~0 ; 0 ; 0 ;
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; - Mux1~1 ; 0 ; 0 ;
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; op[2] ; ; ;
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; - Mux0~2 ; 1 ; 0 ;
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; - Mux3~0 ; 1 ; 0 ;
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; - Mux3~1 ; 1 ; 0 ;
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; - Mux2~0 ; 1 ; 0 ;
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; - Mux2~3 ; 1 ; 0 ;
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; - Mux2~4 ; 1 ; 0 ;
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; - Mux1~0 ; 1 ; 0 ;
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; - Mux1~1 ; 1 ; 0 ;
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; - Mux0~2 ; 0 ; 0 ;
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; - Mux3~0 ; 0 ; 0 ;
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; - Mux3~1 ; 0 ; 0 ;
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; - Mux2~0 ; 0 ; 0 ;
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; - Mux2~3 ; 0 ; 0 ;
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; - Mux2~4 ; 0 ; 0 ;
|
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; - Mux1~0 ; 0 ; 0 ;
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; - Mux1~1 ; 0 ; 0 ;
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; op[1] ; ; ;
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; - Mux3~0 ; 0 ; 0 ;
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; - Mux0~0 ; 0 ; 0 ;
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@@ -1200,16 +1198,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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; - Mux1~2 ; 0 ; 0 ;
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; - Mux0~1 ; 0 ; 0 ;
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; C[1] ; ; ;
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; - ShiftRight0~0 ; 0 ; 0 ;
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; - ShiftRight1~0 ; 0 ; 0 ;
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; - ShiftLeft0~0 ; 0 ; 0 ;
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; - ShiftRight0~1 ; 0 ; 0 ;
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; - Mux2~1 ; 0 ; 0 ;
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; - Mux2~4 ; 0 ; 0 ;
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; - ShiftLeft0~1 ; 0 ; 0 ;
|
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; - ShiftRight0~2 ; 0 ; 0 ;
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; - ShiftLeft0~2 ; 0 ; 0 ;
|
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; - ShiftRight0~3 ; 0 ; 0 ;
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; - ShiftRight0~0 ; 1 ; 0 ;
|
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; - ShiftRight1~0 ; 1 ; 0 ;
|
||||
; - ShiftLeft0~0 ; 1 ; 0 ;
|
||||
; - ShiftRight0~1 ; 1 ; 0 ;
|
||||
; - Mux2~1 ; 1 ; 0 ;
|
||||
; - Mux2~4 ; 1 ; 0 ;
|
||||
; - ShiftLeft0~1 ; 1 ; 0 ;
|
||||
; - ShiftRight0~2 ; 1 ; 0 ;
|
||||
; - ShiftLeft0~2 ; 1 ; 0 ;
|
||||
; - ShiftRight0~3 ; 1 ; 0 ;
|
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; C[0] ; ; ;
|
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; - ShiftRight0~0 ; 1 ; 0 ;
|
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; - ShiftRight1~0 ; 1 ; 0 ;
|
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@@ -1222,11 +1220,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
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; - ShiftLeft0~2 ; 1 ; 0 ;
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; - ShiftRight0~3 ; 1 ; 0 ;
|
||||
; B[2] ; ; ;
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; - ShiftRight2~0 ; 1 ; 0 ;
|
||||
; - ShiftLeft1~0 ; 1 ; 0 ;
|
||||
; - ShiftLeft1~1 ; 1 ; 0 ;
|
||||
; - ShiftRight2~2 ; 1 ; 0 ;
|
||||
; - ShiftRight2~3 ; 1 ; 0 ;
|
||||
; - ShiftRight2~0 ; 0 ; 0 ;
|
||||
; - ShiftLeft1~0 ; 0 ; 0 ;
|
||||
; - ShiftLeft1~1 ; 0 ; 0 ;
|
||||
; - ShiftRight2~2 ; 0 ; 0 ;
|
||||
; - ShiftRight2~3 ; 0 ; 0 ;
|
||||
; B[3] ; ; ;
|
||||
; - ShiftRight2~0 ; 1 ; 0 ;
|
||||
; - ShiftLeft1~0 ; 1 ; 0 ;
|
||||
@@ -1268,18 +1266,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; - ShiftLeft0~2 ; 1 ; 0 ;
|
||||
; - ShiftLeft1~3 ; 1 ; 0 ;
|
||||
; A[1] ; ; ;
|
||||
; - ShiftRight3~0 ; 1 ; 0 ;
|
||||
; - ShiftRight1~0 ; 1 ; 0 ;
|
||||
; - ShiftLeft0~0 ; 1 ; 0 ;
|
||||
; - ShiftRight0~1 ; 1 ; 0 ;
|
||||
; - ShiftLeft1~1 ; 1 ; 0 ;
|
||||
; - ShiftRight2~1 ; 1 ; 0 ;
|
||||
; - Mux2~2 ; 1 ; 0 ;
|
||||
; - Mux2~4 ; 1 ; 0 ;
|
||||
; - ShiftLeft0~1 ; 1 ; 0 ;
|
||||
; - ShiftLeft1~2 ; 1 ; 0 ;
|
||||
; - ShiftLeft0~2 ; 1 ; 0 ;
|
||||
; - ShiftLeft1~3 ; 1 ; 0 ;
|
||||
; - ShiftRight3~0 ; 0 ; 0 ;
|
||||
; - ShiftRight1~0 ; 0 ; 0 ;
|
||||
; - ShiftLeft0~0 ; 0 ; 0 ;
|
||||
; - ShiftRight0~1 ; 0 ; 0 ;
|
||||
; - ShiftLeft1~1 ; 0 ; 0 ;
|
||||
; - ShiftRight2~1 ; 0 ; 0 ;
|
||||
; - Mux2~2 ; 0 ; 0 ;
|
||||
; - Mux2~4 ; 0 ; 0 ;
|
||||
; - ShiftLeft0~1 ; 0 ; 0 ;
|
||||
; - ShiftLeft1~2 ; 0 ; 0 ;
|
||||
; - ShiftLeft0~2 ; 0 ; 0 ;
|
||||
; - ShiftLeft1~3 ; 0 ; 0 ;
|
||||
; A[3] ; ; ;
|
||||
; - ShiftRight3~0 ; 0 ; 0 ;
|
||||
; - ShiftRight1~0 ; 0 ; 0 ;
|
||||
@@ -1304,22 +1302,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+------------------------------+------------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+------------------------------+------------------------+
|
||||
; Block interconnects ; 42 / 217,884 ( < 1 % ) ;
|
||||
; C12 interconnects ; 8 / 10,080 ( < 1 % ) ;
|
||||
; Block interconnects ; 44 / 217,884 ( < 1 % ) ;
|
||||
; C12 interconnects ; 9 / 10,080 ( < 1 % ) ;
|
||||
; C2 interconnects ; 9 / 87,208 ( < 1 % ) ;
|
||||
; C4 interconnects ; 57 / 41,360 ( < 1 % ) ;
|
||||
; C4 interconnects ; 53 / 41,360 ( < 1 % ) ;
|
||||
; DQS bus muxes ; 0 / 21 ( 0 % ) ;
|
||||
; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||
; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||
; Direct links ; 0 / 217,884 ( 0 % ) ;
|
||||
; Direct links ; 8 / 217,884 ( < 1 % ) ;
|
||||
; Global clocks ; 0 / 16 ( 0 % ) ;
|
||||
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
||||
; Local interconnects ; 22 / 58,160 ( < 1 % ) ;
|
||||
; Local interconnects ; 19 / 58,160 ( < 1 % ) ;
|
||||
; Quadrant clocks ; 0 / 88 ( 0 % ) ;
|
||||
; R14 interconnects ; 10 / 9,228 ( < 1 % ) ;
|
||||
; R14/C12 interconnect drivers ; 15 / 15,096 ( < 1 % ) ;
|
||||
; R3 interconnects ; 24 / 94,896 ( < 1 % ) ;
|
||||
; R6 interconnects ; 23 / 194,640 ( < 1 % ) ;
|
||||
; R6 interconnects ; 20 / 194,640 ( < 1 % ) ;
|
||||
; Spine clocks ; 0 / 180 ( 0 % ) ;
|
||||
; Wire stub REs ; 0 / 11,606 ( 0 % ) ;
|
||||
+------------------------------+------------------------+
|
||||
@@ -1375,33 +1373,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; I/O Rules Matrix ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Total Pass ; 0 ; 15 ; 15 ; 0 ; 0 ; 17 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 17 ; 17 ; 0 ;
|
||||
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; Total Inapplicable ; 17 ; 2 ; 2 ; 17 ; 17 ; 0 ; 2 ; 17 ; 17 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 0 ; 0 ; 17 ;
|
||||
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; C[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; C[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; I/O Rules Matrix ;
|
||||
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
||||
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Total Pass ; 0 ; 17 ; 17 ; 0 ; 0 ; 17 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 17 ; 17 ; 0 ;
|
||||
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; Total Inapplicable ; 17 ; 0 ; 0 ; 17 ; 17 ; 0 ; 0 ; 17 ; 17 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 0 ; 0 ; 17 ;
|
||||
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; C[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; C[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------+
|
||||
@@ -1458,13 +1456,12 @@ Info (21077): High junction temperature is 85 degrees C
|
||||
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
||||
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
|
||||
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
||||
Critical Warning (169085): No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
|
||||
Info (184020): Starting Fitter periphery placement operations
|
||||
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
|
||||
Info (176233): Starting register packing
|
||||
Info (176235): Finished register packing
|
||||
Extra Info (176219): No registers were packed into other blocks
|
||||
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08
|
||||
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07
|
||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||||
Info (332144): No user constrained base clocks found in the design
|
||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||||
@@ -1474,7 +1471,7 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai
|
||||
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (14951): The Fitter is using Advanced Physical Optimization.
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
|
||||
Info (170191): Fitter placement operations beginning
|
||||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
|
||||
@@ -1485,17 +1482,17 @@ Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170200): Optimizations that may affect the design's timing were skipped
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds.
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds.
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
|
||||
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings
|
||||
Info: Peak virtual memory: 1379 megabytes
|
||||
Info: Processing ended: Tue Sep 15 19:39:25 2026
|
||||
Info: Elapsed time: 00:00:36
|
||||
Info: Total CPU time (on all processors): 00:00:50
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
|
||||
Info: Peak virtual memory: 1382 megabytes
|
||||
Info: Processing ended: Tue Sep 15 19:49:23 2026
|
||||
Info: Elapsed time: 00:00:29
|
||||
Info: Total CPU time (on all processors): 00:00:41
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
Fitter Status : Successful - Tue Sep 15 19:39:25 2026
|
||||
Fitter Status : Successful - Tue Sep 15 19:49:22 2026
|
||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Revision Name : shifter
|
||||
Top-level Entity Name : shifter
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Flow report for shifter
|
||||
Tue Sep 15 19:39:43 2026
|
||||
Tue Sep 15 19:49:39 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+---------------------------------+-------------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Sep 15 19:39:43 2026 ;
|
||||
; Flow Status ; Successful - Tue Sep 15 19:49:39 2026 ;
|
||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||
; Revision Name ; shifter ;
|
||||
; Top-level Entity Name ; shifter ;
|
||||
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 09/15/2026 19:38:37 ;
|
||||
; Start date & time ; 09/15/2026 19:48:42 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; shifter ;
|
||||
+-------------------+---------------------+
|
||||
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; COMPILER_SIGNATURE_ID ; 268883478169649.178946511707335 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 268883478169649.178946572208013 ; -- ; -- ; -- ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
||||
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ;
|
||||
; Fitter ; 00:00:36 ; 1.0 ; 1379 MB ; 00:00:50 ;
|
||||
; Assembler ; 00:00:06 ; 1.0 ; 507 MB ; 00:00:06 ;
|
||||
; Timing Analyzer ; 00:00:06 ; 1.0 ; 777 MB ; 00:00:06 ;
|
||||
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:25 ;
|
||||
; Fitter ; 00:00:28 ; 1.0 ; 1382 MB ; 00:00:41 ;
|
||||
; Assembler ; 00:00:06 ; 1.0 ; 518 MB ; 00:00:05 ;
|
||||
; Timing Analyzer ; 00:00:05 ; 1.0 ; 773 MB ; 00:00:06 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ;
|
||||
; Total ; 00:01:00 ; -- ; -- ; 00:01:27 ;
|
||||
; Total ; 00:00:51 ; -- ; -- ; 00:01:18 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis report for shifter
|
||||
Tue Sep 15 19:38:48 2026
|
||||
Tue Sep 15 19:48:53 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -44,7 +44,7 @@ on the Quartus Prime software download page.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+---------------------------------+-------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:38:48 2026 ;
|
||||
; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:48:53 2026 ;
|
||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||
; Revision Name ; shifter ;
|
||||
; Top-level Entity Name ; shifter ;
|
||||
@@ -274,7 +274,7 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Tue Sep 15 19:38:37 2026
|
||||
Info: Processing started: Tue Sep 15 19:48:42 2026
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
||||
@@ -290,8 +290,8 @@ Info (21057): Implemented 49 device resources after synthesis - the final resour
|
||||
Info (21061): Implemented 32 logic cells
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 433 megabytes
|
||||
Info: Processing ended: Tue Sep 15 19:38:48 2026
|
||||
Info: Processing ended: Tue Sep 15 19:48:53 2026
|
||||
Info: Elapsed time: 00:00:11
|
||||
Info: Total CPU time (on all processors): 00:00:24
|
||||
Info: Total CPU time (on all processors): 00:00:25
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
Analysis & Synthesis Status : Successful - Tue Sep 15 19:38:48 2026
|
||||
Analysis & Synthesis Status : Successful - Tue Sep 15 19:48:53 2026
|
||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Revision Name : shifter
|
||||
Top-level Entity Name : shifter
|
||||
|
||||
@@ -135,7 +135,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : :
|
||||
NC : AB7 : : : : :
|
||||
GND : AB8 : gnd : : : :
|
||||
VCCPD3A : AB9 : power : : 2.5V : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B :
|
||||
B[3] : AB10 : input : 1.2 V : : 3B : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
|
||||
VCCIO4A : AB13 : power : : 1.2V : 4A :
|
||||
@@ -209,7 +209,7 @@ GND : AE2 : gnd : :
|
||||
GXB_NC : AE3 : : : : B0L :
|
||||
GXB_NC : AE4 : : : : B0L :
|
||||
GND : AE5 : gnd : : : :
|
||||
B[3] : AE6 : input : 1.2 V : : 3B : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3B :
|
||||
GND : AE7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
|
||||
@@ -234,7 +234,7 @@ GND : AF2 : gnd : :
|
||||
GND : AF3 : gnd : : : :
|
||||
GND : AF4 : gnd : : : :
|
||||
AS_DATA0, ASDO, DATA0 : AF5 : : : : 3A :
|
||||
B[2] : AF6 : input : 1.2 V : : 3B : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B :
|
||||
@@ -706,7 +706,7 @@ VCCA_FPLL : W7 : power : : 2.5V
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
|
||||
GND : W9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B :
|
||||
B[2] : W11 : input : 1.2 V : : 3B : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
|
||||
VCCIO4A : W14 : power : : 1.2V : 4A :
|
||||
|
||||
Binary file not shown.
@@ -1,5 +1,5 @@
|
||||
Timing Analyzer report for shifter
|
||||
Tue Sep 15 19:39:40 2026
|
||||
Tue Sep 15 19:49:36 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -103,7 +103,7 @@ on the Quartus Prime software download page.
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 3.0% ;
|
||||
; Processor 2 ; 2.8% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@@ -470,7 +470,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Tue Sep 15 19:39:34 2026
|
||||
Info: Processing started: Tue Sep 15 19:49:31 2026
|
||||
Info: Command: quartus_sta A1_Q5 -c shifter
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
@@ -530,9 +530,9 @@ Info (332140): No Minimum Pulse Width paths to report
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
|
||||
Info: Peak virtual memory: 777 megabytes
|
||||
Info: Processing ended: Tue Sep 15 19:39:40 2026
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Peak virtual memory: 773 megabytes
|
||||
Info: Processing ended: Tue Sep 15 19:49:36 2026
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:06
|
||||
|
||||
|
||||
Reference in new issue
Block a user