Created register for gating pipeline stage results

modules/gatereg.sv

@@ -0,0 +1,16 @@
+module gatereg #(width)(
+    input logic [0:0] clk, input logic [0:0] rst, input logic en[0:0],
+    input logic [2**width-1:0] in, output logic [2**width-1:0] out
+);
+    logic [2**width-1:0] hold_value;
+
+    assign out = hold_value;
+    always_ff @( posedge clk ) begin
+        if (rst) begin
+            hold_value <= {(2**width){0}};
+        end else if (en) begin
+            hold_value <= in;
+        end
+    end
+
+endmodule