From b046ad7db0b09bd11513f9995255017155baf55d Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Thu, 29 Oct 2026 15:27:05 +1100
Subject: [PATCH] Created register for gating pipeline stage results

---
 modules/gatereg.sv | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 modules/gatereg.sv

diff --git a/modules/gatereg.sv b/modules/gatereg.sv
new file mode 100644
index 0000000..d9fdb24
--- /dev/null
+++ b/modules/gatereg.sv
@@ -0,0 +1,16 @@
+module gatereg #(width)(
+    input logic [0:0] clk, input logic [0:0] rst, input logic en[0:0],
+    input logic [2**width-1:0] in, output logic [2**width-1:0] out
+);
+    logic [2**width-1:0] hold_value;
+
+    assign out = hold_value;
+    always_ff @( posedge clk ) begin
+        if (rst) begin
+            hold_value <= {(2**width){0}};
+        end else if (en) begin
+            hold_value <= in;
+        end
+    end
+
+endmodule
\ No newline at end of file