Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

tests/tests.sv

@@ -1,3 +1,3 @@
-`include "tests/seven_seg_tb.v"
-`include "tests/lu_tb.v"
-`include "tests/asu_tb.v"
+`include "tests/seven_seg_tb.sv"
+`include "tests/lu_tb.sv"
+`include "tests/asu_tb.sv"