From a89a66d34dde647e9f5ef754f3c0e2a299400470 Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Thu, 3 Sep 2026 16:32:56 +1000
Subject: [PATCH] Fixed bug where includes still refered to verilog rather than
 systemverilog. Inverted test cases in seven segment test bench to reflect
 changes made to module. There is still a bug with the module where it outputs
 garbage

---
 run.bat                            |  2 +-
 tests/alu_tb.sv                    |  2 +-
 tests/asu_tb.sv                    |  2 +-
 tests/instruction_classifier_tb.sv |  2 +-
 tests/lu_tb.sv                     |  2 +-
 tests/seven_seg_tb.sv              | 36 +++++++++++++++---------------
 tests/shifter_tb.sv                |  2 +-
 tests/tests.sv                     |  6 ++---
 8 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/run.bat b/run.bat
index c7f9c83..ebfbca3 100644
--- a/run.bat
+++ b/run.bat
@@ -1,4 +1,4 @@
 @echo off
 cls
-iverilog -g2012 -o testbench.vvp -I"./modules" -I"./tests" tests/tests.v
+iverilog -g2012 -o testbench.vvp -I"./modules" -I"./tests" tests/tests.sv
 vvp testbench.vvp
diff --git a/tests/alu_tb.sv b/tests/alu_tb.sv
index 1631e29..282d5c9 100644
--- a/tests/alu_tb.sv
+++ b/tests/alu_tb.sv
@@ -1,5 +1,5 @@
 // TODO: Both the ALU and this test bench is incomplete
-`#include "alu.v"
+`#include "alu.sv"
 
 module alu_tb #(width=8)();
 
diff --git a/tests/asu_tb.sv b/tests/asu_tb.sv
index 61e5a2f..9029b30 100644
--- a/tests/asu_tb.sv
+++ b/tests/asu_tb.sv
@@ -1,4 +1,4 @@
-`include "asu.v"
+`include "asu.sv"
 
 module asu_tb #(width=8)();
     logic [0:0] op;
diff --git a/tests/instruction_classifier_tb.sv b/tests/instruction_classifier_tb.sv
index 1575d2a..4d54943 100644
--- a/tests/instruction_classifier_tb.sv
+++ b/tests/instruction_classifier_tb.sv
@@ -1 +1 @@
-`#include "instruction_classifier.v"
+`#include "instruction_classifier.sv"
diff --git a/tests/lu_tb.sv b/tests/lu_tb.sv
index d0f478d..821081e 100644
--- a/tests/lu_tb.sv
+++ b/tests/lu_tb.sv
@@ -1,4 +1,4 @@
-`include "lu.v"
+`include "lu.sv"
 
 module lu_tb #(W=8)();
     logic [1:0] op;
diff --git a/tests/seven_seg_tb.sv b/tests/seven_seg_tb.sv
index f165509..ce2bf6b 100644
--- a/tests/seven_seg_tb.sv
+++ b/tests/seven_seg_tb.sv
@@ -1,4 +1,4 @@
-`include "seven_seg.v"
+`include "seven_seg.sv"
 
 module seven_seg_tb();
     logic [3:0] in_num;
@@ -14,23 +14,23 @@ module seven_seg_tb();
     initial begin
 
         // Initialise truth table
-        true_segments[0 ] = 8'b11111101;
-        true_segments[1 ] = 8'b01100001;
-        true_segments[2 ] = 8'b11011011;
-        true_segments[3 ] = 8'b11110011;
-        true_segments[4 ] = 8'b01100111;
-        true_segments[5 ] = 8'b10110111;
-        true_segments[6 ] = 8'b10111111;
-        true_segments[7 ] = 8'b11100001;
-        true_segments[8 ] = 8'b11111111;
-        true_segments[9 ] = 8'b11100111;
-        true_segments[10] = 8'b11101111;
-        true_segments[11] = 8'b00111111;
-        true_segments[12] = 8'b10011101;
-        true_segments[13] = 8'b01111011;
-        true_segments[14] = 8'b10011111;
-        true_segments[15] = 8'b10001111;
-        true_segments[16] = 8'b00000000;
+        true_segments[0 ] = ~(8'b11111101);
+        true_segments[1 ] = ~(8'b01100001);
+        true_segments[2 ] = ~(8'b11011011);
+        true_segments[3 ] = ~(8'b11110011);
+        true_segments[4 ] = ~(8'b01100111);
+        true_segments[5 ] = ~(8'b10110111);
+        true_segments[6 ] = ~(8'b10111111);
+        true_segments[7 ] = ~(8'b11100001);
+        true_segments[8 ] = ~(8'b11111111);
+        true_segments[9 ] = ~(8'b11100111);
+        true_segments[10] = ~(8'b11101111);
+        true_segments[11] = ~(8'b00111111);
+        true_segments[12] = ~(8'b10011101);
+        true_segments[13] = ~(8'b01111011);
+        true_segments[14] = ~(8'b10011111);
+        true_segments[15] = ~(8'b10001111);
+        true_segments[16] = ~(8'b00000000);
         
         $display("Beginning seven-segment tests");
 
diff --git a/tests/shifter_tb.sv b/tests/shifter_tb.sv
index ae75c7b..24c7945 100644
--- a/tests/shifter_tb.sv
+++ b/tests/shifter_tb.sv
@@ -1,4 +1,4 @@
-`#include "shifter.v"
+`#include "shifter.sv"
 
 module shifter_tb #(width=8)();
 
diff --git a/tests/tests.sv b/tests/tests.sv
index 033b5fd..892382c 100644
--- a/tests/tests.sv
+++ b/tests/tests.sv
@@ -1,3 +1,3 @@
-`include "tests/seven_seg_tb.v"
-`include "tests/lu_tb.v"
-`include "tests/asu_tb.v"
\ No newline at end of file
+`include "tests/seven_seg_tb.sv"
+`include "tests/lu_tb.sv"
+`include "tests/asu_tb.sv"
\ No newline at end of file