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Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

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riley committed 2026-09-03 16:32:56 +10:00
1 parent f881a4126b
commit a89a66d34d
8 files changed
+27 -27
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tests/seven_seg_tb.sv
+18 -18
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@@ -1,4 +1,4 @@
`include "seven_seg.v"
`include "seven_seg.sv"
module seven_seg_tb();
logic [3:0] in_num;
@@ -14,23 +14,23 @@ module seven_seg_tb();
initial begin
// Initialise truth table
true_segments[0 ] = 8'b11111101;
true_segments[1 ] = 8'b01100001;
true_segments[2 ] = 8'b11011011;
true_segments[3 ] = 8'b11110011;
true_segments[4 ] = 8'b01100111;
true_segments[5 ] = 8'b10110111;
true_segments[6 ] = 8'b10111111;
true_segments[7 ] = 8'b11100001;
true_segments[8 ] = 8'b11111111;
true_segments[9 ] = 8'b11100111;
true_segments[10] = 8'b11101111;
true_segments[11] = 8'b00111111;
true_segments[12] = 8'b10011101;
true_segments[13] = 8'b01111011;
true_segments[14] = 8'b10011111;
true_segments[15] = 8'b10001111;
true_segments[16] = 8'b00000000;
true_segments[0 ] = ~(8'b11111101);
true_segments[1 ] = ~(8'b01100001);
true_segments[2 ] = ~(8'b11011011);
true_segments[3 ] = ~(8'b11110011);
true_segments[4 ] = ~(8'b01100111);
true_segments[5 ] = ~(8'b10110111);
true_segments[6 ] = ~(8'b10111111);
true_segments[7 ] = ~(8'b11100001);
true_segments[8 ] = ~(8'b11111111);
true_segments[9 ] = ~(8'b11100111);
true_segments[10] = ~(8'b11101111);
true_segments[11] = ~(8'b00111111);
true_segments[12] = ~(8'b10011101);
true_segments[13] = ~(8'b01111011);
true_segments[14] = ~(8'b10011111);
true_segments[15] = ~(8'b10001111);
true_segments[16] = ~(8'b00000000);
$display("Beginning seven-segment tests");