Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

tests/asu_tb.sv

@@ -1,4 +1,4 @@
-`include "asu.v"
+`include "asu.sv"
 
 module asu_tb #(width=8)();
     logic [0:0] op;