Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

tests/alu_tb.sv

@@ -1,5 +1,5 @@
 // TODO: Both the ALU and this test bench is incomplete
-`#include "alu.v"
+`#include "alu.sv"
 
 module alu_tb #(width=8)();