TroubleElectrical/FPGA_Uni
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Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)

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TroubleElectrical committed 2026-09-10 15:24:44 +10:00
1 parent dc32347c9b
commit a73990b242
64 files changed
+1046 -230
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Quartus/A1_Q4/db/alu.tmw_info
+4 -7
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@@ -1,7 +1,4 @@
start_full_compilation:s:00:00:55
start_analysis_synthesis:s:00:00:12-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:28-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:06-start_full_compilation
start_eda_netlist_writer:s:00:00:02-start_full_compilation
start_full_compilation:s
start_assembler:s-start_full_compilation
start_timing_analyzer:s-start_full_compilation
start_eda_netlist_writer:s-start_full_compilation