diff --git a/ModelSim/Assignment_1_Q2.mpf b/ModelSim/Assignment_1_Q2.mpf index d71bc5b..ff2872f 100644 --- a/ModelSim/Assignment_1_Q2.mpf +++ b/ModelSim/Assignment_1_Q2.mpf @@ -412,9 +412,9 @@ Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 2 Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv -Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1788845636 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788845636 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv -Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/ModelSim/Assignment_1_Q3.cr.mti b/ModelSim/Assignment_1_Q3.cr.mti new file mode 100644 index 0000000..b325a48 --- /dev/null +++ b/ModelSim/Assignment_1_Q3.cr.mti @@ -0,0 +1,16 @@ +/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module asu + +Top level modules: + asu + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module asu +-- Compiling module asu_tb + +Top level modules: + asu_tb + +} {} {}} diff --git a/ModelSim/Assignment_1_Q3.mpf b/ModelSim/Assignment_1_Q3.mpf new file mode 100644 index 0000000..f9d4fc6 --- /dev/null +++ b/ModelSim/Assignment_1_Q3.mpf @@ -0,0 +1,466 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +maxii = $MODEL_TECH/../altera/vhdl/maxii +maxv = $MODEL_TECH/../altera/vhdl/maxv +fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm +sgate = $MODEL_TECH/../altera/vhdl/sgate +arriaii = $MODEL_TECH/../altera/vhdl/arriaii +arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi +arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip +arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz +arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi +arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip +stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv +stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi +stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip +cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv +cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi +cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip +cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive +stratixv = $MODEL_TECH/../altera/vhdl/stratixv +stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi +stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip +arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz +arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi +arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip +arriav = $MODEL_TECH/../altera/vhdl/arriav +cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev +twentynm = $MODEL_TECH/../altera/vhdl/twentynm +twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi +twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip +cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp +; +; Verilog Section +; +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +maxv_ver = $MODEL_TECH/../altera/verilog/maxv +fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii +arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi +arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip +arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz +arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi +arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip +stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv +stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi +stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip +stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv +stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi +stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip +arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz +arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi +arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip +arriav_ver = $MODEL_TECH/../altera/verilog/arriav +arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi +arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip +cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev +cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi +cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip +cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv +cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi +cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip +cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive +twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm +twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi +twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip +cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 ps + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 2 +Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1789017573 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2020 +Project_Minor_Version = 1 diff --git a/ModelSim/asu.sv b/ModelSim/asu.sv new file mode 100644 index 0000000..498faad --- /dev/null +++ b/ModelSim/asu.sv @@ -0,0 +1,17 @@ +module asu #(parameter width = 2)( + input logic [0:0] op, + input logic[2**width-1:0] A, input logic[2**width-1:0] B, + output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN); + + logic [2**width-1:0] operand; + always_comb begin + // A + (sub) ? B : -B + // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis + operand = (B ^ {(2**width){op}}); + {COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op}; + end + + // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported? + // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture + assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1]; +endmodule diff --git a/ModelSim/asu_tb.sv b/ModelSim/asu_tb.sv new file mode 100644 index 0000000..63069d5 --- /dev/null +++ b/ModelSim/asu_tb.sv @@ -0,0 +1,122 @@ +`include "asu.sv" + +module asu_tb #(width=4)(); + logic [0:0] op; + logic [width-1:0] A; + logic [width-1:0] B; + logic [width-1:0] C; + logic [0:0] Cout; + logic [0:0] Cin; + logic [width-1:0] C_exp; + logic [0:0] Cout_exp; + logic [0:0] Cin_exp; // TODO + + asu #($clog2(width)) dut(op, A, B, C, Cout, Cin); + + integer error_count; + initial begin + error_count = 0; + $display("Beginning ASU tests"); + + // Test basic addition of 0+1 = 1 + op = 1'b0; + A = {width{1'b0}}; + B = { {(width-1){1'b0}}, 1'b1}; + C_exp = { {(width-1){1'b0}}, 1'b1}; + Cout_exp = 1'b0; + Cin_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + // Test underflow from 0-1 = UINTMAX + op = 1'b1; + C_exp = {(width){1'b1}}; + Cout_exp = 1'b0; + Cin_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + // Test carry addition of 1+1 = 2 + op = 1'b0; + A = { {(width-1){1'b0}}, 1'b1}; + B = { {(width-1){1'b0}}, 1'b1}; + C_exp = { {(width-2){1'b0}}, 2'b10}; + Cout_exp = 1'b0; + Cin_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + // Test overflow from UINTMAX+1 = 0 + A = {(width){1'b1}}; // UINTMAX + B = { {(width-1){1'b0}}, 1'b1}; // 1 + C_exp = {(width){1'b0}}; + Cout_exp = 1'b1; + Cin_exp = 1'b1; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + // Tests INTMAX+1 + op = 1'b0; + A = {1'b0, {(width-1){1'b1}}}; // INTMAX + B = {{(width-1){1'b0}}, 1'b1}; // 1 + C_exp = {1'b1, {(width-1){1'b0}}}; // -INTMAX + Cin_exp = 1'b1; + Cout_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + op = 1'b0; + A = {1'b1, {(width-1){1'b0}}}; // -INTMAX + B = {1'b1, {(width-1){1'b0}}}; // -INTMAX + C_exp = {width{1'b0}}; // 0 + Cin_exp = 1'b0; + Cout_exp = 1'b1; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + op = 1'b1; + A = {1'b0, {(width-1){1'b1}}}; // INTMAX + B = {1'b1, {(width-1){1'b0}}}; // -INTMAX + C_exp = {width{1'b1}}; // -1 + Cin_exp = 1'b1; + Cout_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + op = 1'b1; + A = {1'b1, {(width-1){1'b0}}}; // -INTMAX + B = {{(width-1){1'b0}}, 1'b1}; // 1 + C_exp = {1'b0, {(width-1){1'b1}}}; // INTMAX + Cin_exp = 1'b0; + Cout_exp = 1'b1; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + if (error_count == 0) $display("\x1b[38;5;10mAll ASU tests passing\x1b[m"); + else $display("\x1b[38;5;9m%0d ASU test(s) failing\x1b[m", error_count); + end +endmodule \ No newline at end of file diff --git a/ModelSim/asu_tb.sv.bak b/ModelSim/asu_tb.sv.bak new file mode 100644 index 0000000..e0285fb --- /dev/null +++ b/ModelSim/asu_tb.sv.bak @@ -0,0 +1,122 @@ +`include "asu.sv" + +module asu_tb #(width=8)(); + logic [0:0] op; + logic [width-1:0] A; + logic [width-1:0] B; + logic [width-1:0] C; + logic [0:0] Cout; + logic [0:0] Cin; + logic [width-1:0] C_exp; + logic [0:0] Cout_exp; + logic [0:0] Cin_exp; // TODO + + asu #($clog2(width)) dut(op, A, B, C, Cout, Cin); + + integer error_count; + initial begin + error_count = 0; + $display("Beginning ASU tests"); + + // Test basic addition of 0+1 = 1 + op = 1'b0; + A = {width{1'b0}}; + B = { {(width-1){1'b0}}, 1'b1}; + C_exp = { {(width-1){1'b0}}, 1'b1}; + Cout_exp = 1'b0; + Cin_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + // Test underflow from 0-1 = UINTMAX + op = 1'b1; + C_exp = {(width){1'b1}}; + Cout_exp = 1'b0; + Cin_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + // Test carry addition of 1+1 = 2 + op = 1'b0; + A = { {(width-1){1'b0}}, 1'b1}; + B = { {(width-1){1'b0}}, 1'b1}; + C_exp = { {(width-2){1'b0}}, 2'b10}; + Cout_exp = 1'b0; + Cin_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + // Test overflow from UINTMAX+1 = 0 + A = {(width){1'b1}}; // UINTMAX + B = { {(width-1){1'b0}}, 1'b1}; // 1 + C_exp = {(width){1'b0}}; + Cout_exp = 1'b1; + Cin_exp = 1'b1; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + // Tests INTMAX+1 + op = 1'b0; + A = {1'b0, {(width-1){1'b1}}}; // INTMAX + B = {{(width-1){1'b0}}, 1'b1}; // 1 + C_exp = {1'b1, {(width-1){1'b0}}}; // -INTMAX + Cin_exp = 1'b1; + Cout_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + op = 1'b0; + A = {1'b1, {(width-1){1'b0}}}; // -INTMAX + B = {1'b1, {(width-1){1'b0}}}; // -INTMAX + C_exp = {width{1'b0}}; // 0 + Cin_exp = 1'b0; + Cout_exp = 1'b1; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + op = 1'b1; + A = {1'b0, {(width-1){1'b1}}}; // INTMAX + B = {1'b1, {(width-1){1'b0}}}; // -INTMAX + C_exp = {width{1'b1}}; // -1 + Cin_exp = 1'b1; + Cout_exp = 1'b0; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + op = 1'b1; + A = {1'b1, {(width-1){1'b0}}}; // -INTMAX + B = {{(width-1){1'b0}}, 1'b1}; // 1 + C_exp = {1'b0, {(width-1){1'b1}}}; // INTMAX + Cin_exp = 1'b0; + Cout_exp = 1'b1; + #1; + if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin + $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp); + error_count = error_count + 1; + end + + if (error_count == 0) $display("\x1b[38;5;10mAll ASU tests passing\x1b[m"); + else $display("\x1b[38;5;9m%0d ASU test(s) failing\x1b[m", error_count); + end +endmodule \ No newline at end of file diff --git a/ModelSim/transcript b/ModelSim/transcript index dc52352..f93b766 100644 --- a/ModelSim/transcript +++ b/ModelSim/transcript @@ -1,19 +1,45 @@ # Loading project Assignment_1_Q2 -# Compile of lu.sv was successful. -# Compile of lu_tb.sv was successful. +# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini +# Loading project Assignment_1_Q3 +# Compile of asu.sv was successful. +# Compile of asu_tb.sv was successful. # 2 compiles, 0 failed with no errors. -vsim work.lu_tb -# vsim work.lu_tb -# Start time: 13:56:39 on Sep 09,2026 +vsim work.asu_tb +# vsim work.asu_tb +# Start time: 15:16:49 on Sep 10,2026 # Loading sv_std.std -# Loading work.lu_tb -# Loading work.lu -add wave -position end sim:/lu_tb/op -add wave -position end sim:/lu_tb/A -add wave -position end sim:/lu_tb/B -add wave -position end sim:/lu_tb/C -restart -f -# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'. +# Loading work.asu_tb +# Loading work.asu +add wave -position end sim:/asu_tb/A +add wave -position end sim:/asu_tb/B +add wave -position end sim:/asu_tb/C +add wave -position end sim:/asu_tb/Cout +add wave -position end sim:/asu_tb/Cin +run +# Beginning ASU tests +# All ASU tests passing +add wave -position end sim:/asu_tb/op +run quit -sim -# End time: 13:59:50 on Sep 09,2026, Elapsed time: 0:03:11 -# Errors: 0, Warnings: 1 +# End time: 15:19:15 on Sep 10,2026, Elapsed time: 0:02:26 +# Errors: 0, Warnings: 5 +# Compile of asu.sv was successful. +# Compile of asu_tb.sv was successful. +# 2 compiles, 0 failed with no errors. +vsim work.asu_tb +# vsim work.asu_tb +# Start time: 15:20:10 on Sep 10,2026 +# Loading sv_std.std +# Loading work.asu_tb +# Loading work.asu +add wave -position end sim:/asu_tb/A +add wave -position end sim:/asu_tb/B +add wave -position end sim:/asu_tb/C +add wave -position end sim:/asu_tb/Cout +add wave -position end sim:/asu_tb/Cin +add wave -position end sim:/asu_tb/op +run +# Beginning ASU tests +# All ASU tests passing +# End time: 15:24:25 on Sep 10,2026, Elapsed time: 0:04:15 +# Errors: 0, Warnings: 2 diff --git a/ModelSim/vsim.wlf b/ModelSim/vsim.wlf index 809373e..aa35809 100644 Binary files a/ModelSim/vsim.wlf and b/ModelSim/vsim.wlf differ diff --git a/ModelSim/work/_info b/ModelSim/work/_info index 58301bf..d252026 100644 --- a/ModelSim/work/_info +++ b/ModelSim/work/_info @@ -9,53 +9,103 @@ z2 !i10f 100 cModel Technology d/home/oliver/intelFPGA/20.1/modelsim_ase/bin -vlu +vasu Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3 -Z1 !s110 1788926178 +Z1 !s110 1789017577 !i10b 1 -!s100 nmDP9zlMCJDa@W3_FY5m[2 +!s100 7ffgJO49=l5BT:aebMX3F1 Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1 -Il^hWCV0VAo9mz6NG=G9=51 +IM`6LR=<^Jm_aekUe6^m;b0 Z3 VDg1SIo80bB@j0V0VzS_@n1 S1 Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim -w1788845636 -8lu.sv -Flu.sv -!i122 8 -L0 1 16 -Z5 OV;L;2020.1;71 +Z5 w1788926090 +8asu.sv +Fasu.sv +!i122 14 +L0 1 17 +Z6 OV;L;2020.1;71 r1 !s85 0 31 -Z6 !s108 1788926178.000000 -!s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| -Z7 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| +Z7 !s108 1789017577.000000 +!s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv| +Z8 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv| !i113 1 -Z8 o-work work -sv -Z9 tCvgOpt 0 -vlu_tb +Z9 o-work work -sv +Z10 tCvgOpt 0 +vasu_tb R0 R1 !i10b 1 +!s100 ?AMT1ejDgW=83T_P=nh4G1 +R2 +IcS>Hk9oO:RGFmfdUY9[i90 +R3 +S1 +R4 +w1789017573 +8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv +F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv +!i122 14 +L0 3 120 +R6 +r1 +!s85 0 +31 +R7 +Z11 !s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv| +R8 +!i113 1 +R9 +R10 +vlu +R0 +Z12 !s110 1789014325 +!i10b 1 +!s100 nmDP9zlMCJDa@W3_FY5m[2 +R2 +Il^hWCV0VAo9mz6NG=G9=51 +R3 +S1 +R4 +w1788845636 +8lu.sv +Flu.sv +!i122 10 +L0 1 16 +R6 +r1 +!s85 0 +31 +Z13 !s108 1789014325.000000 +Z14 !s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| +Z15 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| +!i113 1 +R9 +R10 +vlu_tb +R0 +R12 +!i10b 1 !s100 AE_liX6DCD[3>b;K6Wgf72 R2 IC?h=m;SY77_D:GA0FR