TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)

Browse Source
This commit is contained in:
TroubleElectrical committed 2026-09-10 15:24:44 +10:00
1 parent dc32347c9b
commit a73990b242
64 files changed
+1046 -230
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Quartus/A1_Q4/db/A1_Q4.quiproj.3289.rdr.flock
View File
Whitespace-only changes.
Quartus/A1_Q4/db/alu.db_info
+1 -1
View File
@@ -1,3 +1,3 @@
Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Version_Index = 604268800
Creation_Time = Wed Sep 9 14:17:10 2026
Creation_Time = Thu Sep 10 14:53:57 2026
Quartus/A1_Q4/db/alu.tmw_info
+4 -7
View File
@@ -1,7 +1,4 @@
start_full_compilation:s:00:00:55
start_analysis_synthesis:s:00:00:12-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:28-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:06-start_full_compilation
start_eda_netlist_writer:s:00:00:02-start_full_compilation
start_full_compilation:s
start_assembler:s-start_full_compilation
start_timing_analyzer:s-start_full_compilation
start_eda_netlist_writer:s-start_full_compilation