Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
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@@ -9,53 +9,103 @@ z2
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!i10f 100
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cModel Technology
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d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
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vlu
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vasu
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Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
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Z1 !s110 1788926178
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Z1 !s110 1789017577
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!i10b 1
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!s100 nmDP9zlMCJDa@W3_FY5m[2
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!s100 7ffgJO49=l5BT:aebMX3F1
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Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
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Il^hWCV0VAo9mz6NG=G9=51
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IM`6LR=<^Jm_aekUe6^m;b0
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Z3 VDg1SIo80bB@j0V0VzS_@n1
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S1
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Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
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w1788845636
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8lu.sv
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Flu.sv
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!i122 8
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L0 1 16
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Z5 OV;L;2020.1;71
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Z5 w1788926090
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8asu.sv
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Fasu.sv
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!i122 14
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L0 1 17
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Z6 OV;L;2020.1;71
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r1
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!s85 0
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31
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Z6 !s108 1788926178.000000
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!s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
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Z7 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
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Z7 !s108 1789017577.000000
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!s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
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Z8 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
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!i113 1
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Z8 o-work work -sv
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Z9 tCvgOpt 0
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vlu_tb
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Z9 o-work work -sv
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Z10 tCvgOpt 0
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vasu_tb
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R0
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R1
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!i10b 1
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!s100 ?AMT1ejDgW=83T_P=nh4G1
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R2
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IcS>Hk9oO:RGFmfdUY9[i90
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R3
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S1
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R4
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w1789017573
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8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
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F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
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!i122 14
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L0 3 120
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R6
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r1
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!s85 0
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31
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R7
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Z11 !s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
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R8
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!i113 1
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R9
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R10
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vlu
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R0
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Z12 !s110 1789014325
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!i10b 1
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!s100 nmDP9zlMCJDa@W3_FY5m[2
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R2
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Il^hWCV0VAo9mz6NG=G9=51
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R3
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S1
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R4
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w1788845636
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8lu.sv
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Flu.sv
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!i122 10
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L0 1 16
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R6
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r1
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!s85 0
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31
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Z13 !s108 1789014325.000000
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Z14 !s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
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Z15 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
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!i113 1
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R9
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R10
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vlu_tb
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R0
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R12
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!i10b 1
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!s100 AE_liX6DCD[3>b;K6Wgf72
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R2
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IC?h=m;SY77_D:GA0FR<P^2
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R3
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S1
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R4
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w1788926090
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R5
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8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
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F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
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!i122 8
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!i122 10
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L0 3 58
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R5
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R6
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r1
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!s85 0
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31
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R6
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Z10 !s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
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R7
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R13
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R14
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R15
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!i113 1
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R8
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R9
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R10
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