diff --git a/ModelSim/Assignment_1_Q2.mpf b/ModelSim/Assignment_1_Q2.mpf index 5fed1bb..3023a36 100644 --- a/ModelSim/Assignment_1_Q2.mpf +++ b/ModelSim/Assignment_1_Q2.mpf @@ -220,7 +220,7 @@ Resolution = ps UserTimeUnit = default ; Default run length -RunLength = 100 ps +RunLength = 0 ps ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 @@ -412,9 +412,9 @@ Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 2 Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv -Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv -Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/ModelSim/transcript b/ModelSim/transcript index 815c8aa..16838a3 100644 --- a/ModelSim/transcript +++ b/ModelSim/transcript @@ -1,131 +1,7 @@ -# Loading project Assignment_1_Q3 -# Compile of asu.sv was successful. -# Compile of asu_tb.sv was successful. -# 2 compiles, 0 failed with no errors. -vsim work.asu_tb -# vsim work.asu_tb -# Start time: 15:01:26 on Sep 15,2026 -# Loading sv_std.std -# Loading work.asu_tb -# Loading work.asu -add wave -position end sim:/asu_tb/op -add wave -position end sim:/asu_tb/A -add wave -position end sim:/asu_tb/B -add wave -position end sim:/asu_tb/C -add wave -position end sim:/asu_tb/Cout -add wave -position end sim:/asu_tb/Cin -run -# Beginning ASU tests -# All ASU tests passing -quit -sim -# End time: 15:03:03 on Sep 15,2026, Elapsed time: 0:01:37 -# Errors: 0, Warnings: 2 -# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini -# Loading project Assignment_1_Q4 -# Compile of alu.sv was successful. -# Compile of alu_tb.sv was successful. -# 2 compiles, 0 failed with no errors. -vsim work.alu_tb -# vsim work.alu_tb -# Start time: 15:04:11 on Sep 15,2026 -# Loading sv_std.std -# Loading work.alu_tb -# Loading work.alu -# Loading work.asu -# Loading work.lu -add wave -position end sim:/alu_tb/op_in -add wave -position end sim:/alu_tb/A_in -add wave -position end sim:/alu_tb/B_in -add wave -position end sim:/alu_tb/Y_out -add wave -position end sim:/alu_tb/flags_out -add wave -position end sim:/alu_tb/ops -run -# Beginning ALU tests -# All ALU tests passing -add wave -position end sim:/alu_tb/error_count -run -quit -sim -# End time: 15:05:53 on Sep 15,2026, Elapsed time: 0:01:42 -# Errors: 0, Warnings: 5 -# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini -# Loading project Assignment_1_Q5 -# Compile of shifter.sv was successful. -# Compile of shifter_tb.sv was successful. -# 2 compiles, 0 failed with no errors. -vsim work.shifter_tb -# vsim work.shifter_tb -# Start time: 15:06:46 on Sep 15,2026 -# Loading sv_std.std -# Loading work.shifter_tb -# Loading work.shifter -add wave -position end sim:/shifter_tb/op -add wave -position end sim:/shifter_tb/Y -add wave -position end sim:/shifter_tb/A_in -add wave -position end sim:/shifter_tb/B_in -add wave -position end sim:/shifter_tb/C_in -add wave -position end sim:/shifter_tb/A -add wave -position end sim:/shifter_tb/B -add wave -position end sim:/shifter_tb/C -add wave -position end sim:/shifter_tb/Y -add wave -position end sim:/shifter_tb/op -run -# Beginning Shifter tests -# All Shifter tests passing -quit -sim -# End time: 15:07:54 on Sep 15,2026, Elapsed time: 0:01:08 -# Errors: 0, Warnings: 5 -# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini -# Loading project Assignment_1_Q6 -# Compile of instruction_classifier.sv was successful. -# Compile of instruction_classifier_tb.sv was successful. -# 2 compiles, 0 failed with no errors. -vsim work.instruction_classifier_tb -# vsim work.instruction_classifier_tb -# Start time: 15:08:34 on Sep 15,2026 -# Loading sv_std.std -# Loading work.instruction_classifier_tb -# Loading work.instruction_classifier -add wave -position end sim:/instruction_classifier_tb/op -add wave -position end sim:/instruction_classifier_tb/C -add wave -position end sim:/instruction_classifier_tb/ops -run -# Beginning Instruction Classifier tests -# All Instruction Classifier tests passing -quit -sim -# End time: 15:09:45 on Sep 15,2026, Elapsed time: 0:01:11 -# Errors: 0, Warnings: 5 -# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini -# Loading project Assignment_1_Q1 -# Compile of seven_seg.sv was successful. -# Compile of seven_seg_tb.sv was successful. -# 2 compiles, 0 failed with no errors. -vsim work.seven_seg_tb -# vsim work.seven_seg_tb -# Start time: 15:10:28 on Sep 15,2026 -# Loading sv_std.std -# Loading work.seven_seg_tb -# Loading work.seven_seg -add wave -position end sim:/seven_seg_tb/in_rbi_inv -add wave -position end sim:/seven_seg_tb/out_segments -add wave -position end sim:/seven_seg_tb/true_segments -add wave -position end sim:/seven_seg_tb/N -add wave -position end sim:/seven_seg_tb/i -add wave -position 1 sim:/seven_seg_tb/in_num -run -# Beginning seven-segment tests -# All seven-segment tests passing -quit -sim -# End time: 15:12:28 on Sep 15,2026, Elapsed time: 0:02:00 -# Errors: 0, Warnings: 5 -project open /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/Assignment_1_Q2 -# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini # Loading project Assignment_1_Q2 -# Compile of lu.sv was successful. -# Compile of lu_tb.sv was successful. -# 2 compiles, 0 failed with no errors. vsim work.lu_tb # vsim work.lu_tb -# Start time: 15:13:40 on Sep 15,2026 +# Start time: 16:47:26 on Sep 15,2026 # Loading sv_std.std # Loading work.lu_tb # Loading work.lu @@ -133,9 +9,13 @@ add wave -position end sim:/lu_tb/op add wave -position end sim:/lu_tb/A add wave -position end sim:/lu_tb/B add wave -position end sim:/lu_tb/C +add wave -position end sim:/lu_tb/C_exp run # Beginning LU tests +run +run +run +run -all # All LU tests passing -quit -sim -# End time: 15:14:33 on Sep 15,2026, Elapsed time: 0:00:53 -# Errors: 0, Warnings: 3 +# End time: 16:52:34 on Sep 15,2026, Elapsed time: 0:05:08 +# Errors: 0, Warnings: 1 diff --git a/ModelSim/vsim.wlf b/ModelSim/vsim.wlf index 2ca9e22..f25da77 100644 Binary files a/ModelSim/vsim.wlf and b/ModelSim/vsim.wlf differ diff --git a/Quartus/A1_Q1/db/seven_seg.(0).cnf.hdb b/Quartus/A1_Q1/db/seven_seg.(0).cnf.hdb index d2e5801..4ef3092 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.(0).cnf.hdb and b/Quartus/A1_Q1/db/seven_seg.(0).cnf.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.asm.qmsg b/Quartus/A1_Q1/db/seven_seg.asm.qmsg index 2719942..2a548f5 100644 --- a/Quartus/A1_Q1/db/seven_seg.asm.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418657395 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418657395 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:57:37 2026 " "Processing started: Thu Sep 3 16:57:37 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418657395 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788418657395 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788418657395 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788418658046 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788418662314 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418662476 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:42 2026 " "Processing ended: Thu Sep 3 16:57:42 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418662476 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418662476 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418662476 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788418662476 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452617233 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452617233 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:10:17 2026 " "Processing started: Tue Sep 15 16:10:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452617233 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789452617233 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789452617233 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789452617910 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789452622452 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452622665 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:10:22 2026 " "Processing ended: Tue Sep 15 16:10:22 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452622665 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452622665 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452622665 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789452622665 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.asm.rdb b/Quartus/A1_Q1/db/seven_seg.asm.rdb index 6ea3680..83fba2f 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.asm.rdb and b/Quartus/A1_Q1/db/seven_seg.asm.rdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.cmp.bpm b/Quartus/A1_Q1/db/seven_seg.cmp.bpm index 82a5011..112955a 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cmp.bpm and b/Quartus/A1_Q1/db/seven_seg.cmp.bpm differ diff --git a/Quartus/A1_Q1/db/seven_seg.cmp.cdb b/Quartus/A1_Q1/db/seven_seg.cmp.cdb index 3d63b43..9aa07e5 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cmp.cdb and b/Quartus/A1_Q1/db/seven_seg.cmp.cdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.cmp.hdb b/Quartus/A1_Q1/db/seven_seg.cmp.hdb index f2a262e..76540d7 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cmp.hdb and b/Quartus/A1_Q1/db/seven_seg.cmp.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.cmp.rdb b/Quartus/A1_Q1/db/seven_seg.cmp.rdb index 742cedc..97ceb01 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cmp.rdb and b/Quartus/A1_Q1/db/seven_seg.cmp.rdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A1_Q1/db/seven_seg.cyclonev_io_sim_cache.ff_0c_fast.hsd index b19b6d1..5b25938 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cyclonev_io_sim_cache.ff_0c_fast.hsd and b/Quartus/A1_Q1/db/seven_seg.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A1_Q1/db/seven_seg.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A1_Q1/db/seven_seg.cyclonev_io_sim_cache.ii_85c_slow.hsd index 118df22..0778662 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cyclonev_io_sim_cache.ii_85c_slow.hsd and b/Quartus/A1_Q1/db/seven_seg.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A1_Q1/db/seven_seg.db_info b/Quartus/A1_Q1/db/seven_seg.db_info index 29cc534..3f93553 100644 --- a/Quartus/A1_Q1/db/seven_seg.db_info +++ b/Quartus/A1_Q1/db/seven_seg.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Thu Sep 3 19:21:31 2026 +Creation_Time = Tue Sep 15 16:32:16 2026 diff --git a/Quartus/A1_Q1/db/seven_seg.eda.qmsg b/Quartus/A1_Q1/db/seven_seg.eda.qmsg index 6108a84..a9f02e0 100644 --- a/Quartus/A1_Q1/db/seven_seg.eda.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418670701 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418670701 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:57:50 2026 " "Processing started: Thu Sep 3 16:57:50 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418670701 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418670701 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418670702 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788418671436 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788418671488 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418671527 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:51 2026 " "Processing ended: Thu Sep 3 16:57:51 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418671527 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418671527 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418671527 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418671527 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452631501 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452631502 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:10:31 2026 " "Processing started: Tue Sep 15 16:10:31 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452631502 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789452631502 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789452631502 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789452632297 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789452632380 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452632427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:10:32 2026 " "Processing ended: Tue Sep 15 16:10:32 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452632427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452632427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452632427 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789452632427 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.fit.qmsg b/Quartus/A1_Q1/db/seven_seg.fit.qmsg index c41a542..3e2a6ef 100644 --- a/Quartus/A1_Q1/db/seven_seg.fit.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.fit.qmsg @@ -1,43 +1,43 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788418628799 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788418628800 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788418628804 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418628870 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418628870 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788418629270 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788418629302 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788418629350 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788418636105 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418636123 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788418636125 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418636125 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418636126 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788418636126 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788418636126 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788418636126 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788418636126 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788418636126 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788418636126 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418636143 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788418642018 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788418642018 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788418642019 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788418642019 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788418642020 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788418642020 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788418642021 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788418642023 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788418642102 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418642704 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788418643216 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788418643462 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418643462 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788418644424 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X46_Y0 X56_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11"} { { 12 { 0 ""} 46 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788418649870 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788418649870 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788418650096 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788418650096 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788418650096 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418650098 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788418651194 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418651229 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418651579 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418651580 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418652299 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418655001 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1384 " "Peak virtual memory: 1384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418655800 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:35 2026 " "Processing ended: Thu Sep 3 16:57:35 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418655800 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418655800 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418655800 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788418655800 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789452587402 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789452587402 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789452587408 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789452587480 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789452587480 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789452587910 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789452587965 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789452588119 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789452595068 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452595089 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789452595108 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789452595108 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789452595109 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789452595109 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789452595109 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789452595109 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789452595109 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789452595109 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789452595109 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452595128 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789452601222 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789452601223 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789452601223 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789452601224 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789452601226 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789452601226 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789452601226 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789452601230 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789452601322 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452602021 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789452602296 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789452602604 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452602604 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789452603604 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X46_Y0 X56_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11"} { { 12 { 0 ""} 46 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789452609205 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789452609205 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789452609431 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789452609431 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789452609431 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452609434 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789452610686 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789452610723 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789452611103 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789452611104 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789452611860 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452614550 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1384 " "Peak virtual memory: 1384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452615386 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:10:15 2026 " "Processing ended: Tue Sep 15 16:10:15 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452615386 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452615386 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452615386 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789452615386 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.hif b/Quartus/A1_Q1/db/seven_seg.hif index a0766cd..c0c918d 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.hif and b/Quartus/A1_Q1/db/seven_seg.hif differ diff --git a/Quartus/A1_Q1/db/seven_seg.map.bpm b/Quartus/A1_Q1/db/seven_seg.map.bpm index 66b6e2b..9d07cfb 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map.bpm and b/Quartus/A1_Q1/db/seven_seg.map.bpm differ diff --git a/Quartus/A1_Q1/db/seven_seg.map.cdb b/Quartus/A1_Q1/db/seven_seg.map.cdb index 58f3103..6ef1ee6 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map.cdb and b/Quartus/A1_Q1/db/seven_seg.map.cdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.map.hdb b/Quartus/A1_Q1/db/seven_seg.map.hdb index 21f45f2..e10cf28 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map.hdb and b/Quartus/A1_Q1/db/seven_seg.map.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.map.qmsg b/Quartus/A1_Q1/db/seven_seg.map.qmsg index 4493d3b..8894ad2 100644 --- a/Quartus/A1_Q1/db/seven_seg.map.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.map.qmsg @@ -1,11 +1,11 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418615772 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418615772 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:56:55 2026 " "Processing started: Thu Sep 3 16:56:55 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418615772 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418615772 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418615773 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788418616096 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788418616097 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788418625920 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418625920 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788418626051 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788418626737 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788418627068 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788418627068 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788418627106 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788418627106 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788418627106 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788418627106 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418627114 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:07 2026 " "Processing ended: Thu Sep 3 16:57:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418627114 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418627114 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418627114 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418627114 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452574038 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452574039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:09:33 2026 " "Processing started: Tue Sep 15 16:09:33 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452574039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452574039 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452574039 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789452574410 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789452574410 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789452583455 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452583455 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789452583612 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789452584489 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789452584916 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789452584916 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789452585041 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789452585041 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789452585041 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789452585041 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452585047 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:09:45 2026 " "Processing ended: Tue Sep 15 16:09:45 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452585047 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452585047 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452585047 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452585047 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.map.rdb b/Quartus/A1_Q1/db/seven_seg.map.rdb index c479cbe..eb0a833 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map.rdb and b/Quartus/A1_Q1/db/seven_seg.map.rdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.map_bb.cdb b/Quartus/A1_Q1/db/seven_seg.map_bb.cdb index a7702af..391a286 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map_bb.cdb and b/Quartus/A1_Q1/db/seven_seg.map_bb.cdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.map_bb.hdb b/Quartus/A1_Q1/db/seven_seg.map_bb.hdb index bc3c454..b500f8d 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map_bb.hdb and b/Quartus/A1_Q1/db/seven_seg.map_bb.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.pre_map.hdb b/Quartus/A1_Q1/db/seven_seg.pre_map.hdb index eeae3d2..5bb30e2 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.pre_map.hdb and b/Quartus/A1_Q1/db/seven_seg.pre_map.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.rtlv.hdb b/Quartus/A1_Q1/db/seven_seg.rtlv.hdb index 6849aa1..c48a6dc 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.rtlv.hdb and b/Quartus/A1_Q1/db/seven_seg.rtlv.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.sta.qmsg b/Quartus/A1_Q1/db/seven_seg.sta.qmsg index cb3222b..83624f2 100644 --- a/Quartus/A1_Q1/db/seven_seg.sta.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418663922 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418663923 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:57:43 2026 " "Processing started: Thu Sep 3 16:57:43 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418663923 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418663923 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418663923 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788418663978 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788418664459 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788418664459 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418664532 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418664532 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788418665100 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418665100 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418665101 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418665101 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418665101 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418665101 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788418665102 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788418665106 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418665107 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665108 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665111 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665112 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665113 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665114 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665114 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418665117 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418665154 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418666438 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418666534 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418666534 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418666534 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418666535 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666535 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666537 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666538 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666539 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666539 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666540 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418666542 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418666803 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418667501 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418667545 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418667546 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418667546 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418667546 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667547 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667548 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667549 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667550 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667550 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418667552 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418667701 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418667702 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418667702 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418667702 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667703 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667704 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667705 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667705 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667706 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418669108 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418669108 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "780 " "Peak virtual memory: 780 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418669130 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:49 2026 " "Processing ended: Thu Sep 3 16:57:49 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418669130 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418669130 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418669130 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788418669130 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452624355 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452624356 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:10:24 2026 " "Processing started: Tue Sep 15 16:10:24 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452624356 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789452624356 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789452624356 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789452624432 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789452624945 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789452624945 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452625018 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452625018 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789452625598 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452625599 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452625599 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452625600 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789452625600 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452625600 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789452625601 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789452625605 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789452625605 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625607 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625618 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625619 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625620 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625620 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625621 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789452625623 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789452625661 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789452627007 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452627088 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452627088 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452627088 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452627089 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627089 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627091 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627092 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627093 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627094 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627094 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789452627096 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789452627365 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789452628090 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452628130 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452628130 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452628130 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452628130 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628132 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628133 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628133 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628134 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628135 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789452628136 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452628295 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452628295 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452628295 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452628296 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628297 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628298 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628299 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628299 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628300 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789452629766 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789452629766 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "788 " "Peak virtual memory: 788 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452629798 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:10:29 2026 " "Processing ended: Tue Sep 15 16:10:29 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452629798 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452629798 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452629798 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789452629798 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.sta.rdb b/Quartus/A1_Q1/db/seven_seg.sta.rdb index 0a2eaa9..7d47495 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.sta.rdb and b/Quartus/A1_Q1/db/seven_seg.sta.rdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_0c.ddb index 5aec916..85548fc 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_85c.ddb index 7703ee2..cb5c259 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_0c.ddb index d24c30c..f93e175 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_85c.ddb index db35da7..a01de83 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.cdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.cdb index dfaed70..f2f2f3d 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.cdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.cdb index da5f897..40c331f 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.hdb index db5650c..47693da 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hdb index d7b6841..2beb9e1 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.cdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.cdb index fb0de4d..3bb2ca0 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.cdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.cdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.dpi b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.dpi index 2e48f00..ce61807 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.dpi and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.dpi differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.cdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.cdb index 368fd17..ac28d97 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.cdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.hdb index f64424f..393b7d7 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hdb index 3d67a7d..915edc1 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.rrp.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.rrp.hdb index 71f0934..b91fa42 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.rrp.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.rrp.hdb differ diff --git a/Quartus/A1_Q1/output_files/seven_seg.asm.rpt b/Quartus/A1_Q1/output_files/seven_seg.asm.rpt index 7a7edcc..e877ece 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.asm.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.asm.rpt @@ -1,5 +1,5 @@ Assembler report for seven_seg -Thu Sep 3 16:57:42 2026 +Tue Sep 15 16:10:22 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Sep 3 16:57:42 2026 ; +; Assembler Status ; Successful - Tue Sep 15 16:10:22 2026 ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; ; Family ; Cyclone V ; @@ -78,13 +78,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 3 16:57:37 2026 + Info: Processing started: Tue Sep 15 16:10:17 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 525 megabytes - Info: Processing ended: Thu Sep 3 16:57:42 2026 + Info: Peak virtual memory: 521 megabytes + Info: Processing ended: Tue Sep 15 16:10:22 2026 Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q1/output_files/seven_seg.done b/Quartus/A1_Q1/output_files/seven_seg.done index 69bf9c6..547c0ff 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.done +++ b/Quartus/A1_Q1/output_files/seven_seg.done @@ -1 +1 @@ -Thu Sep 3 16:57:52 2026 +Tue Sep 15 16:10:33 2026 diff --git a/Quartus/A1_Q1/output_files/seven_seg.eda.rpt b/Quartus/A1_Q1/output_files/seven_seg.eda.rpt index fe6fc98..5d24436 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.eda.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for seven_seg -Thu Sep 3 16:57:51 2026 +Tue Sep 15 16:10:32 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Thu Sep 3 16:57:51 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Sep 15 16:10:32 2026 ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; ; Family ; Cyclone V ; @@ -81,13 +81,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 3 16:57:50 2026 + Info: Processing started: Tue Sep 15 16:10:31 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file seven_seg.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 658 megabytes - Info: Processing ended: Thu Sep 3 16:57:51 2026 + Info: Processing ended: Tue Sep 15 16:10:32 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A1_Q1/output_files/seven_seg.fit.rpt b/Quartus/A1_Q1/output_files/seven_seg.fit.rpt index 95e9a7e..49e7f60 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.fit.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.fit.rpt @@ -1,5 +1,5 @@ Fitter report for seven_seg -Thu Sep 3 16:57:35 2026 +Tue Sep 15 16:10:14 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -57,7 +57,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Thu Sep 3 16:57:35 2026 ; +; Fitter Status ; Successful - Tue Sep 15 16:10:14 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; @@ -152,7 +152,7 @@ on the Quartus Prime software download page. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.2% ; +; Processor 2 ; 0.3% ; +----------------------------+-------------+ @@ -1386,8 +1386,8 @@ Info (334004): Delay annotation completed successfully Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings Info: Peak virtual memory: 1384 megabytes - Info: Processing ended: Thu Sep 3 16:57:35 2026 - Info: Elapsed time: 00:00:27 - Info: Total CPU time (on all processors): 00:00:39 + Info: Processing ended: Tue Sep 15 16:10:15 2026 + Info: Elapsed time: 00:00:29 + Info: Total CPU time (on all processors): 00:00:40 diff --git a/Quartus/A1_Q1/output_files/seven_seg.fit.summary b/Quartus/A1_Q1/output_files/seven_seg.fit.summary index 43a8a6e..2fecfe9 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.fit.summary +++ b/Quartus/A1_Q1/output_files/seven_seg.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Thu Sep 3 16:57:35 2026 +Fitter Status : Successful - Tue Sep 15 16:10:14 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : seven_seg Top-level Entity Name : seven_seg diff --git a/Quartus/A1_Q1/output_files/seven_seg.flow.rpt b/Quartus/A1_Q1/output_files/seven_seg.flow.rpt index 1c1558d..1ec5212 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.flow.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.flow.rpt @@ -1,5 +1,5 @@ Flow report for seven_seg -Thu Sep 3 16:57:51 2026 +Tue Sep 15 16:10:32 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,7 +41,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Thu Sep 3 16:57:51 2026 ; +; Flow Status ; Successful - Tue Sep 15 16:10:32 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/03/2026 16:56:55 ; +; Start date & time ; 09/15/2026 16:09:34 ; ; Main task ; Compilation ; ; Revision Name ; seven_seg ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 55629860311554.178841861509729 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 268883478169649.178945257408043 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,10 +101,10 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ; -; Fitter ; 00:00:27 ; 1.0 ; 1384 MB ; 00:00:38 ; -; Assembler ; 00:00:05 ; 1.0 ; 525 MB ; 00:00:05 ; -; Timing Analyzer ; 00:00:06 ; 1.0 ; 780 MB ; 00:00:05 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ; +; Fitter ; 00:00:28 ; 1.0 ; 1384 MB ; 00:00:40 ; +; Assembler ; 00:00:05 ; 1.0 ; 521 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:05 ; 1.0 ; 788 MB ; 00:00:06 ; ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ; ; Total ; 00:00:50 ; -- ; -- ; 00:01:16 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A1_Q1/output_files/seven_seg.map.rpt b/Quartus/A1_Q1/output_files/seven_seg.map.rpt index b10d946..1ae0db0 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.map.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for seven_seg -Thu Sep 3 16:57:07 2026 +Tue Sep 15 16:09:45 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -44,7 +44,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Sep 3 16:57:07 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Sep 15 16:09:45 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; @@ -269,12 +269,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 3 16:56:55 2026 + Info: Processing started: Tue Sep 15 16:09:33 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file seven_seg.sv - Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 1 + Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 3 Info (12127): Elaborating entity "seven_seg" for the top level hierarchy Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" @@ -285,8 +285,8 @@ Info (21057): Implemented 21 device resources after synthesis - the final resour Info (21061): Implemented 8 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning Info: Peak virtual memory: 436 megabytes - Info: Processing ended: Thu Sep 3 16:57:07 2026 + Info: Processing ended: Tue Sep 15 16:09:45 2026 Info: Elapsed time: 00:00:12 - Info: Total CPU time (on all processors): 00:00:27 + Info: Total CPU time (on all processors): 00:00:24 diff --git a/Quartus/A1_Q1/output_files/seven_seg.map.summary b/Quartus/A1_Q1/output_files/seven_seg.map.summary index 8165f2a..bb9a42f 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.map.summary +++ b/Quartus/A1_Q1/output_files/seven_seg.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Thu Sep 3 16:57:07 2026 +Analysis & Synthesis Status : Successful - Tue Sep 15 16:09:45 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : seven_seg Top-level Entity Name : seven_seg diff --git a/Quartus/A1_Q1/output_files/seven_seg.sof b/Quartus/A1_Q1/output_files/seven_seg.sof index 2c3ddcd..10167c6 100644 Binary files a/Quartus/A1_Q1/output_files/seven_seg.sof and b/Quartus/A1_Q1/output_files/seven_seg.sof differ diff --git a/Quartus/A1_Q1/output_files/seven_seg.sta.rpt b/Quartus/A1_Q1/output_files/seven_seg.sta.rpt index d1e38f0..a7ae99f 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.sta.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for seven_seg -Thu Sep 3 16:57:49 2026 +Tue Sep 15 16:10:29 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -103,7 +103,7 @@ on the Quartus Prime software download page. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 2.1% ; +; Processor 2 ; 2.0% ; +----------------------------+-------------+ @@ -474,7 +474,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 3 16:57:43 2026 + Info: Processing started: Tue Sep 15 16:10:24 2026 Info: Command: quartus_sta q1 -c seven_seg Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -534,9 +534,9 @@ Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 780 megabytes - Info: Processing ended: Thu Sep 3 16:57:49 2026 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:05 + Info: Peak virtual memory: 788 megabytes + Info: Processing ended: Tue Sep 15 16:10:29 2026 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:06 diff --git a/Quartus/A1_Q1/seven_seg.qws b/Quartus/A1_Q1/seven_seg.qws index 0ccf1da..63563b7 100644 Binary files a/Quartus/A1_Q1/seven_seg.qws and b/Quartus/A1_Q1/seven_seg.qws differ diff --git a/Quartus/A1_Q1/seven_seg.sv b/Quartus/A1_Q1/seven_seg.sv index 6f19c81..675f354 100644 --- a/Quartus/A1_Q1/seven_seg.sv +++ b/Quartus/A1_Q1/seven_seg.sv @@ -1,3 +1,5 @@ +`ifndef SEVEN_SEG_H_SV +`define SEVEN_SEG_H_SV module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments); always_comb begin case (num) @@ -21,3 +23,4 @@ module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic endcase end endmodule +`endif \ No newline at end of file diff --git a/Quartus/A1_Q1/simulation/questa/seven_seg.svo b/Quartus/A1_Q1/simulation/questa/seven_seg.svo index b554d3a..fad5287 100644 --- a/Quartus/A1_Q1/simulation/questa/seven_seg.svo +++ b/Quartus/A1_Q1/simulation/questa/seven_seg.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "09/03/2026 16:57:51" +// DATE "09/15/2026 16:10:32" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 diff --git a/Quartus/A1_Q2/db/lu.(0).cnf.hdb b/Quartus/A1_Q2/db/lu.(0).cnf.hdb index 9f264f1..a8400ed 100644 Binary files a/Quartus/A1_Q2/db/lu.(0).cnf.hdb and b/Quartus/A1_Q2/db/lu.(0).cnf.hdb differ diff --git a/Quartus/A1_Q2/db/lu.asm.qmsg b/Quartus/A1_Q2/db/lu.asm.qmsg index 6d743ae..7f2a5df 100644 --- a/Quartus/A1_Q2/db/lu.asm.qmsg +++ b/Quartus/A1_Q2/db/lu.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788846115934 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788846115934 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:41:55 2026 " "Processing started: Tue Sep 8 15:41:55 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788846115934 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788846115934 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788846115934 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788846116615 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788846121685 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "513 " "Peak virtual memory: 513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846121865 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:42:01 2026 " "Processing ended: Tue Sep 8 15:42:01 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846121865 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846121865 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846121865 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788846121865 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452825148 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452825149 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:13:44 2026 " "Processing started: Tue Sep 15 16:13:44 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452825149 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789452825149 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789452825149 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789452825810 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789452830226 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "513 " "Peak virtual memory: 513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452830418 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:13:50 2026 " "Processing ended: Tue Sep 15 16:13:50 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452830418 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452830418 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452830418 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789452830418 ""} diff --git a/Quartus/A1_Q2/db/lu.asm.rdb b/Quartus/A1_Q2/db/lu.asm.rdb index e2648f3..5edad52 100644 Binary files a/Quartus/A1_Q2/db/lu.asm.rdb and b/Quartus/A1_Q2/db/lu.asm.rdb differ diff --git a/Quartus/A1_Q2/db/lu.cmp.cdb b/Quartus/A1_Q2/db/lu.cmp.cdb index 2bd58dd..39592c3 100644 Binary files a/Quartus/A1_Q2/db/lu.cmp.cdb and b/Quartus/A1_Q2/db/lu.cmp.cdb differ diff --git a/Quartus/A1_Q2/db/lu.cmp.hdb b/Quartus/A1_Q2/db/lu.cmp.hdb index f90f7a2..afcc516 100644 Binary files a/Quartus/A1_Q2/db/lu.cmp.hdb and b/Quartus/A1_Q2/db/lu.cmp.hdb differ diff --git a/Quartus/A1_Q2/db/lu.cmp.rdb b/Quartus/A1_Q2/db/lu.cmp.rdb index a807890..a4697e5 100644 Binary files a/Quartus/A1_Q2/db/lu.cmp.rdb and b/Quartus/A1_Q2/db/lu.cmp.rdb differ diff --git a/Quartus/A1_Q2/db/lu.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A1_Q2/db/lu.cyclonev_io_sim_cache.ff_0c_fast.hsd index b19b6d1..5b25938 100644 Binary files a/Quartus/A1_Q2/db/lu.cyclonev_io_sim_cache.ff_0c_fast.hsd and b/Quartus/A1_Q2/db/lu.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A1_Q2/db/lu.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A1_Q2/db/lu.cyclonev_io_sim_cache.ii_85c_slow.hsd index 118df22..0778662 100644 Binary files a/Quartus/A1_Q2/db/lu.cyclonev_io_sim_cache.ii_85c_slow.hsd and b/Quartus/A1_Q2/db/lu.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A1_Q2/db/lu.db_info b/Quartus/A1_Q2/db/lu.db_info index 0ee4455..bc41629 100644 --- a/Quartus/A1_Q2/db/lu.db_info +++ b/Quartus/A1_Q2/db/lu.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Tue Sep 8 14:59:42 2026 +Creation_Time = Tue Sep 15 16:12:28 2026 diff --git a/Quartus/A1_Q2/db/lu.eda.qmsg b/Quartus/A1_Q2/db/lu.eda.qmsg index a961234..9fbb094 100644 --- a/Quartus/A1_Q2/db/lu.eda.qmsg +++ b/Quartus/A1_Q2/db/lu.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788846130996 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788846130997 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:42:10 2026 " "Processing started: Tue Sep 8 15:42:10 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788846130997 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788846130997 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788846130997 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788846131765 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "lu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/ simulation " "Generated file lu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788846131827 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846131859 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:42:11 2026 " "Processing ended: Tue Sep 8 15:42:11 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846131859 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846131859 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846131859 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788846131859 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452838178 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452838178 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:13:58 2026 " "Processing started: Tue Sep 15 16:13:58 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452838178 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789452838178 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789452838178 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789452838942 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "lu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/ simulation " "Generated file lu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789452838999 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452839034 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:13:59 2026 " "Processing ended: Tue Sep 15 16:13:59 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452839034 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452839034 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452839034 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789452839034 ""} diff --git a/Quartus/A1_Q2/db/lu.fit.qmsg b/Quartus/A1_Q2/db/lu.fit.qmsg index e349d54..648b700 100644 --- a/Quartus/A1_Q2/db/lu.fit.qmsg +++ b/Quartus/A1_Q2/db/lu.fit.qmsg @@ -1,44 +1,44 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788846086718 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788846086718 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "lu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"lu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788846086722 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788846086797 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788846086797 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788846087212 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788846087239 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788846087300 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788846094476 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846094496 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788846094498 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788846094498 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788846094498 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788846094498 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788846094499 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788846094499 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788846094499 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788846094499 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788846094499 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846094517 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788846100702 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788846100702 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788846100703 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788846100703 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788846100704 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788846100704 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788846100705 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788846100707 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788846100789 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846101473 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788846101809 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788846102125 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846102125 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788846102702 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788846108403 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788846108403 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788846108640 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788846108640 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788846108640 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846108642 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788846109774 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788846109810 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788846110179 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788846110179 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788846110711 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788846113447 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1788846113739 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1336 " "Peak virtual memory: 1336 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846114319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:41:54 2026 " "Processing ended: Tue Sep 8 15:41:54 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846114319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846114319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846114319 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788846114319 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789452796592 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789452796592 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "lu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"lu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789452796597 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789452796664 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789452796664 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789452797107 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789452797134 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789452797188 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789452803962 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452803987 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789452803989 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789452803989 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789452803990 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789452803990 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789452803990 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789452803991 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789452803992 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789452803993 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789452803993 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452804013 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789452809939 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789452809940 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789452809940 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789452809941 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789452809941 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789452809942 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789452809942 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789452809944 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789452810035 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452810664 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789452811274 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789452811530 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452811531 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789452812106 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789452817659 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789452817659 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789452817908 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789452817908 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789452817908 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452817911 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789452819010 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789452819043 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789452819403 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789452819403 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789452819988 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452822690 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789452822961 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1337 " "Peak virtual memory: 1337 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452823523 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:13:43 2026 " "Processing ended: Tue Sep 15 16:13:43 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452823523 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452823523 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452823523 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789452823523 ""} diff --git a/Quartus/A1_Q2/db/lu.hif b/Quartus/A1_Q2/db/lu.hif index 53eb7ad..f736546 100644 Binary files a/Quartus/A1_Q2/db/lu.hif and b/Quartus/A1_Q2/db/lu.hif differ diff --git a/Quartus/A1_Q2/db/lu.map.bpm b/Quartus/A1_Q2/db/lu.map.bpm index 810d5d8..968973f 100644 Binary files a/Quartus/A1_Q2/db/lu.map.bpm and b/Quartus/A1_Q2/db/lu.map.bpm differ diff --git a/Quartus/A1_Q2/db/lu.map.cdb b/Quartus/A1_Q2/db/lu.map.cdb index aef8254..5449ca0 100644 Binary files a/Quartus/A1_Q2/db/lu.map.cdb and b/Quartus/A1_Q2/db/lu.map.cdb differ diff --git a/Quartus/A1_Q2/db/lu.map.hdb b/Quartus/A1_Q2/db/lu.map.hdb index eccd8b0..8f4d177 100644 Binary files a/Quartus/A1_Q2/db/lu.map.hdb and b/Quartus/A1_Q2/db/lu.map.hdb differ diff --git a/Quartus/A1_Q2/db/lu.map.qmsg b/Quartus/A1_Q2/db/lu.map.qmsg index 845f873..fac8677 100644 --- a/Quartus/A1_Q2/db/lu.map.qmsg +++ b/Quartus/A1_Q2/db/lu.map.qmsg @@ -1,11 +1,11 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788846074109 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788846074109 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:41:13 2026 " "Processing started: Tue Sep 8 15:41:13 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788846074109 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788846074109 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788846074109 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788846074444 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788846074444 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 lu " "Found entity 1: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788846083748 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788846083748 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "lu " "Elaborating entity \"lu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788846083888 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788846084609 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788846084962 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788846084962 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788846085010 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788846085010 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788846085010 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788846085010 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846085017 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:41:25 2026 " "Processing ended: Tue Sep 8 15:41:25 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846085017 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846085017 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846085017 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788846085017 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452783794 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452783794 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:13:03 2026 " "Processing started: Tue Sep 15 16:13:03 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452783794 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452783794 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452783794 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789452784121 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789452784121 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 lu " "Found entity 1: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789452793572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452793572 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "lu " "Elaborating entity \"lu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789452793711 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789452794436 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789452794789 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789452794789 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789452794823 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789452794823 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789452794823 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789452794823 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452794829 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:13:14 2026 " "Processing ended: Tue Sep 15 16:13:14 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452794829 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452794829 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452794829 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452794829 ""} diff --git a/Quartus/A1_Q2/db/lu.map.rdb b/Quartus/A1_Q2/db/lu.map.rdb index e86e77a..5939074 100644 Binary files a/Quartus/A1_Q2/db/lu.map.rdb and b/Quartus/A1_Q2/db/lu.map.rdb differ diff --git a/Quartus/A1_Q2/db/lu.map_bb.cdb b/Quartus/A1_Q2/db/lu.map_bb.cdb index 08ce60e..ed2634b 100644 Binary files a/Quartus/A1_Q2/db/lu.map_bb.cdb and b/Quartus/A1_Q2/db/lu.map_bb.cdb differ diff --git a/Quartus/A1_Q2/db/lu.map_bb.hdb b/Quartus/A1_Q2/db/lu.map_bb.hdb index e65ee0b..4a01980 100644 Binary files a/Quartus/A1_Q2/db/lu.map_bb.hdb and b/Quartus/A1_Q2/db/lu.map_bb.hdb differ diff --git a/Quartus/A1_Q2/db/lu.pre_map.hdb b/Quartus/A1_Q2/db/lu.pre_map.hdb index 9f7c5ec..63f5573 100644 Binary files a/Quartus/A1_Q2/db/lu.pre_map.hdb and b/Quartus/A1_Q2/db/lu.pre_map.hdb differ diff --git a/Quartus/A1_Q2/db/lu.rtlv.hdb b/Quartus/A1_Q2/db/lu.rtlv.hdb index a2c08d0..e464287 100644 Binary files a/Quartus/A1_Q2/db/lu.rtlv.hdb and b/Quartus/A1_Q2/db/lu.rtlv.hdb differ diff --git a/Quartus/A1_Q2/db/lu.sta.qmsg b/Quartus/A1_Q2/db/lu.sta.qmsg index d31f13b..5dcbf4b 100644 --- a/Quartus/A1_Q2/db/lu.sta.qmsg +++ b/Quartus/A1_Q2/db/lu.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788846123810 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788846123811 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 8 15:42:03 2026 " "Processing started: Tue Sep 8 15:42:03 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788846123811 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788846123811 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q2 -c lu " "Command: quartus_sta A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788846123811 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788846123898 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788846124685 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788846124686 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846124781 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846124781 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788846125575 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846125575 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788846125576 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788846125576 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788846125577 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788846125577 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788846125578 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788846125584 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788846125584 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125585 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125589 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125590 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125591 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125592 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846125593 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788846125596 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788846125648 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788846126673 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846126766 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788846126766 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788846126766 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788846126767 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126767 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126769 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126770 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126771 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126771 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846126772 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788846126773 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788846127036 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788846127620 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846127689 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788846127690 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788846127690 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788846127690 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127692 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127692 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127693 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127694 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127694 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788846127696 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788846127873 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788846127873 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788846127874 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788846127874 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127875 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127878 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127880 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127881 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788846127883 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788846129404 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788846129405 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "756 " "Peak virtual memory: 756 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788846129429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 8 15:42:09 2026 " "Processing ended: Tue Sep 8 15:42:09 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788846129429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788846129429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788846129429 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788846129429 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452831888 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452831888 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:13:51 2026 " "Processing started: Tue Sep 15 16:13:51 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452831888 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789452831888 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q2 -c lu " "Command: quartus_sta A1_Q2 -c lu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789452831888 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789452831959 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789452832420 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789452832420 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452832492 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452832492 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lu.sdc " "Synopsys Design Constraints File file not found: 'lu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789452833073 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452833075 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452833075 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452833076 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789452833077 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452833077 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789452833078 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789452833082 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789452833083 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452833084 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452833088 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452833089 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452833089 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452833090 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452833091 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789452833095 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789452833139 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789452834027 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452834117 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452834117 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452834118 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452834118 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834118 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834120 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834121 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834122 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834122 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834123 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789452834125 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789452834376 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789452834931 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452834969 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452834969 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452834969 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452834969 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834970 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834971 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834972 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834973 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452834974 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789452834977 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452835123 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452835123 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452835124 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452835124 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452835125 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452835126 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452835127 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452835127 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452835128 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789452836521 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789452836522 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "760 " "Peak virtual memory: 760 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452836544 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:13:56 2026 " "Processing ended: Tue Sep 15 16:13:56 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452836544 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452836544 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452836544 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789452836544 ""} diff --git a/Quartus/A1_Q2/db/lu.sta.rdb b/Quartus/A1_Q2/db/lu.sta.rdb index 3a11f39..193f8de 100644 Binary files a/Quartus/A1_Q2/db/lu.sta.rdb and b/Quartus/A1_Q2/db/lu.sta.rdb differ diff --git a/Quartus/A1_Q2/db/lu.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q2/db/lu.tiscmp.fast_1100mv_0c.ddb index 8cebf9f..4de474d 100644 Binary files a/Quartus/A1_Q2/db/lu.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q2/db/lu.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q2/db/lu.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q2/db/lu.tiscmp.fast_1100mv_85c.ddb index ba6448f..f41cccf 100644 Binary files a/Quartus/A1_Q2/db/lu.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q2/db/lu.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q2/db/lu.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q2/db/lu.tiscmp.slow_1100mv_0c.ddb index 5cca6bc..e1e8d69 100644 Binary files a/Quartus/A1_Q2/db/lu.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q2/db/lu.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q2/db/lu.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q2/db/lu.tiscmp.slow_1100mv_85c.ddb index 285c481..3ba2ca0 100644 Binary files a/Quartus/A1_Q2/db/lu.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q2/db/lu.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q2/db/lu.tmw_info b/Quartus/A1_Q2/db/lu.tmw_info index 7f49395..788c795 100644 --- a/Quartus/A1_Q2/db/lu.tmw_info +++ b/Quartus/A1_Q2/db/lu.tmw_info @@ -1,7 +1,7 @@ -start_full_compilation:s:00:00:59 -start_analysis_synthesis:s:00:00:12-start_full_compilation +start_full_compilation:s:00:00:57 +start_analysis_synthesis:s:00:00:13-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:30-start_full_compilation +start_fitter:s:00:00:29-start_full_compilation start_assembler:s:00:00:07-start_full_compilation -start_timing_analyzer:s:00:00:08-start_full_compilation +start_timing_analyzer:s:00:00:06-start_full_compilation start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.cdb b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.cdb index 827c6a7..e1820f0 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.cdb and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hbdb.cdb index 3d4da00..c1afa44 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hbdb.hdb index 6d505da..5f1a7da 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hdb b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hdb index d049aba..28085cc 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hdb and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.cdb b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.cdb index ba0caf6..5ff48c3 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.cdb and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.cdb differ diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.dpi b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.dpi index 1be12d4..a17af85 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.dpi and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.dpi differ diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hbdb.cdb b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hbdb.cdb index 5a82f25..2c0d90d 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hbdb.cdb and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hbdb.hdb b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hbdb.hdb index b1861f8..02b4444 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hbdb.hdb and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hdb b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hdb index 527ca56..1872c58 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hdb and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.root_partition.map.hdb differ diff --git a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.rrp.hdb b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.rrp.hdb index 2f23fa1..e454ef4 100644 Binary files a/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.rrp.hdb and b/Quartus/A1_Q2/incremental_db/compiled_partitions/lu.rrp.hdb differ diff --git a/Quartus/A1_Q2/lu.qws b/Quartus/A1_Q2/lu.qws index fbc79a3..cefa2eb 100644 Binary files a/Quartus/A1_Q2/lu.qws and b/Quartus/A1_Q2/lu.qws differ diff --git a/Quartus/A1_Q2/output_files/lu.asm.rpt b/Quartus/A1_Q2/output_files/lu.asm.rpt index f09f3b8..deba87d 100644 --- a/Quartus/A1_Q2/output_files/lu.asm.rpt +++ b/Quartus/A1_Q2/output_files/lu.asm.rpt @@ -1,5 +1,5 @@ Assembler report for lu -Tue Sep 8 15:42:01 2026 +Tue Sep 15 16:13:50 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Sep 8 15:42:01 2026 ; +; Assembler Status ; Successful - Tue Sep 15 16:13:50 2026 ; ; Revision Name ; lu ; ; Top-level Entity Name ; lu ; ; Family ; Cyclone V ; @@ -78,14 +78,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 8 15:41:55 2026 + Info: Processing started: Tue Sep 15 16:13:44 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q2 -c lu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 513 megabytes - Info: Processing ended: Tue Sep 8 15:42:01 2026 + Info: Processing ended: Tue Sep 15 16:13:50 2026 Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q2/output_files/lu.done b/Quartus/A1_Q2/output_files/lu.done index b36464f..ab3ebb0 100644 --- a/Quartus/A1_Q2/output_files/lu.done +++ b/Quartus/A1_Q2/output_files/lu.done @@ -1 +1 @@ -Tue Sep 8 15:42:12 2026 +Tue Sep 15 16:13:59 2026 diff --git a/Quartus/A1_Q2/output_files/lu.eda.rpt b/Quartus/A1_Q2/output_files/lu.eda.rpt index 52f34a9..56135b8 100644 --- a/Quartus/A1_Q2/output_files/lu.eda.rpt +++ b/Quartus/A1_Q2/output_files/lu.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for lu -Tue Sep 8 15:42:11 2026 +Tue Sep 15 16:13:59 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Sep 8 15:42:11 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Sep 15 16:13:59 2026 ; ; Revision Name ; lu ; ; Top-level Entity Name ; lu ; ; Family ; Cyclone V ; @@ -81,13 +81,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 8 15:42:10 2026 + Info: Processing started: Tue Sep 15 16:13:58 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q2 -c lu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file lu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q2/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 658 megabytes - Info: Processing ended: Tue Sep 8 15:42:11 2026 + Info: Processing ended: Tue Sep 15 16:13:59 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A1_Q2/output_files/lu.fit.rpt b/Quartus/A1_Q2/output_files/lu.fit.rpt index 3e9a51b..de0d13d 100644 --- a/Quartus/A1_Q2/output_files/lu.fit.rpt +++ b/Quartus/A1_Q2/output_files/lu.fit.rpt @@ -1,5 +1,5 @@ Fitter report for lu -Tue Sep 8 15:41:53 2026 +Tue Sep 15 16:13:43 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -58,7 +58,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Sep 8 15:41:53 2026 ; +; Fitter Status ; Successful - Tue Sep 15 16:13:43 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; lu ; ; Top-level Entity Name ; lu ; @@ -1371,12 +1371,12 @@ Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 1336 megabytes - Info: Processing ended: Tue Sep 8 15:41:54 2026 + Info: Peak virtual memory: 1337 megabytes + Info: Processing ended: Tue Sep 15 16:13:43 2026 Info: Elapsed time: 00:00:28 - Info: Total CPU time (on all processors): 00:00:40 + Info: Total CPU time (on all processors): 00:00:39 diff --git a/Quartus/A1_Q2/output_files/lu.fit.summary b/Quartus/A1_Q2/output_files/lu.fit.summary index 51ec57c..d7ca099 100644 --- a/Quartus/A1_Q2/output_files/lu.fit.summary +++ b/Quartus/A1_Q2/output_files/lu.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Sep 8 15:41:53 2026 +Fitter Status : Successful - Tue Sep 15 16:13:43 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : lu Top-level Entity Name : lu diff --git a/Quartus/A1_Q2/output_files/lu.flow.rpt b/Quartus/A1_Q2/output_files/lu.flow.rpt index c0e9196..e98ad2b 100644 --- a/Quartus/A1_Q2/output_files/lu.flow.rpt +++ b/Quartus/A1_Q2/output_files/lu.flow.rpt @@ -1,5 +1,5 @@ Flow report for lu -Tue Sep 8 15:42:11 2026 +Tue Sep 15 16:13:59 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,7 +41,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Sep 8 15:42:11 2026 ; +; Flow Status ; Successful - Tue Sep 15 16:13:59 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; lu ; ; Top-level Entity Name ; lu ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/08/2026 15:41:14 ; +; Start date & time ; 09/15/2026 16:13:04 ; ; Main task ; Compilation ; ; Revision Name ; lu ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 86000517901476.178884607407150 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 268883478169649.178945278308519 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -102,11 +102,11 @@ on the Quartus Prime software download page. ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 422 MB ; 00:00:25 ; -; Fitter ; 00:00:27 ; 1.0 ; 1336 MB ; 00:00:40 ; -; Assembler ; 00:00:06 ; 1.0 ; 513 MB ; 00:00:06 ; -; Timing Analyzer ; 00:00:06 ; 1.0 ; 756 MB ; 00:00:06 ; -; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ; -; Total ; 00:00:51 ; -- ; -- ; 00:01:18 ; +; Fitter ; 00:00:28 ; 1.0 ; 1337 MB ; 00:00:38 ; +; Assembler ; 00:00:06 ; 1.0 ; 513 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:05 ; 1.0 ; 760 MB ; 00:00:05 ; +; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 658 MB ; 00:00:01 ; +; Total ; 00:00:52 ; -- ; -- ; 00:01:14 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A1_Q2/output_files/lu.map.rpt b/Quartus/A1_Q2/output_files/lu.map.rpt index 7476f01..0b350f0 100644 --- a/Quartus/A1_Q2/output_files/lu.map.rpt +++ b/Quartus/A1_Q2/output_files/lu.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for lu -Tue Sep 8 15:41:25 2026 +Tue Sep 15 16:13:14 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -45,7 +45,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Sep 8 15:41:25 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Sep 15 16:13:14 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; lu ; ; Top-level Entity Name ; lu ; @@ -278,12 +278,12 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 8 15:41:13 2026 + Info: Processing started: Tue Sep 15 16:13:03 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv - Info (12023): Found entity 1: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 1 + Info (12023): Found entity 1: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3 Info (12127): Elaborating entity "lu" for the top level hierarchy Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" @@ -294,8 +294,8 @@ Info (21057): Implemented 18 device resources after synthesis - the final resour Info (21061): Implemented 4 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning Info: Peak virtual memory: 439 megabytes - Info: Processing ended: Tue Sep 8 15:41:25 2026 - Info: Elapsed time: 00:00:12 - Info: Total CPU time (on all processors): 00:00:25 + Info: Processing ended: Tue Sep 15 16:13:14 2026 + Info: Elapsed time: 00:00:11 + Info: Total CPU time (on all processors): 00:00:26 diff --git a/Quartus/A1_Q2/output_files/lu.map.summary b/Quartus/A1_Q2/output_files/lu.map.summary index 6b8e0e8..d1b0f70 100644 --- a/Quartus/A1_Q2/output_files/lu.map.summary +++ b/Quartus/A1_Q2/output_files/lu.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Tue Sep 8 15:41:25 2026 +Analysis & Synthesis Status : Successful - Tue Sep 15 16:13:14 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : lu Top-level Entity Name : lu diff --git a/Quartus/A1_Q2/output_files/lu.sof b/Quartus/A1_Q2/output_files/lu.sof index f2bdb8b..20a641c 100644 Binary files a/Quartus/A1_Q2/output_files/lu.sof and b/Quartus/A1_Q2/output_files/lu.sof differ diff --git a/Quartus/A1_Q2/output_files/lu.sta.rpt b/Quartus/A1_Q2/output_files/lu.sta.rpt index 1a0fe65..81c2d25 100644 --- a/Quartus/A1_Q2/output_files/lu.sta.rpt +++ b/Quartus/A1_Q2/output_files/lu.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for lu -Tue Sep 8 15:42:09 2026 +Tue Sep 15 16:13:56 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -103,7 +103,7 @@ on the Quartus Prime software download page. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 2.6% ; +; Processor 2 ; 2.8% ; +----------------------------+-------------+ @@ -461,7 +461,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 8 15:42:03 2026 + Info: Processing started: Tue Sep 15 16:13:51 2026 Info: Command: quartus_sta A1_Q2 -c lu Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -521,9 +521,9 @@ Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 756 megabytes - Info: Processing ended: Tue Sep 8 15:42:09 2026 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 + Info: Peak virtual memory: 760 megabytes + Info: Processing ended: Tue Sep 15 16:13:56 2026 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q2/simulation/questa/lu.svo b/Quartus/A1_Q2/simulation/questa/lu.svo index 205d5ea..045f6bb 100644 --- a/Quartus/A1_Q2/simulation/questa/lu.svo +++ b/Quartus/A1_Q2/simulation/questa/lu.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "09/08/2026 15:42:11" +// DATE "09/15/2026 16:13:58" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 diff --git a/Quartus/A1_Q3/asu.qsf b/Quartus/A1_Q3/asu.qsf index e807934..0794b88 100644 --- a/Quartus/A1_Q3/asu.qsf +++ b/Quartus/A1_Q3/asu.qsf @@ -84,4 +84,18 @@ set_location_assignment PIN_F6 -to OUT_1[1] set_location_assignment PIN_G6 -to OUT_1[2] set_location_assignment PIN_G7 -to OUT_1[3] set_location_assignment PIN_J8 -to COUT[0] +set_location_assignment PIN_V19 -to out_seg_1[1] +set_location_assignment PIN_V18 -to out_seg_1[2] +set_location_assignment PIN_V17 -to out_seg_1[3] +set_location_assignment PIN_W18 -to out_seg_1[4] +set_location_assignment PIN_Y20 -to out_seg_1[5] +set_location_assignment PIN_Y19 -to out_seg_1[6] +set_location_assignment PIN_Y18 -to out_seg_1[7] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[7] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[4] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[5] +set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg_1[6] set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/A1_Q3/asu.qws b/Quartus/A1_Q3/asu.qws index af223fb..47d9a93 100644 Binary files a/Quartus/A1_Q3/asu.qws and b/Quartus/A1_Q3/asu.qws differ diff --git a/Quartus/A1_Q3/db/asu.(0).cnf.cdb b/Quartus/A1_Q3/db/asu.(0).cnf.cdb index 6cb2307..6038e98 100644 Binary files a/Quartus/A1_Q3/db/asu.(0).cnf.cdb and b/Quartus/A1_Q3/db/asu.(0).cnf.cdb differ diff --git a/Quartus/A1_Q3/db/asu.(0).cnf.hdb b/Quartus/A1_Q3/db/asu.(0).cnf.hdb index 8f62ddf..136ced4 100644 Binary files a/Quartus/A1_Q3/db/asu.(0).cnf.hdb and b/Quartus/A1_Q3/db/asu.(0).cnf.hdb differ diff --git a/Quartus/A1_Q3/db/asu.(1).cnf.cdb b/Quartus/A1_Q3/db/asu.(1).cnf.cdb new file mode 100644 index 0000000..01312ad Binary files /dev/null and b/Quartus/A1_Q3/db/asu.(1).cnf.cdb differ diff --git a/Quartus/A1_Q3/db/asu.(1).cnf.hdb b/Quartus/A1_Q3/db/asu.(1).cnf.hdb new file mode 100644 index 0000000..d3283b4 Binary files /dev/null and b/Quartus/A1_Q3/db/asu.(1).cnf.hdb differ diff --git a/Quartus/A1_Q3/db/asu.(2).cnf.cdb b/Quartus/A1_Q3/db/asu.(2).cnf.cdb new file mode 100644 index 0000000..eff0d17 Binary files /dev/null and b/Quartus/A1_Q3/db/asu.(2).cnf.cdb differ diff --git a/Quartus/A1_Q3/db/asu.(2).cnf.hdb b/Quartus/A1_Q3/db/asu.(2).cnf.hdb new file mode 100644 index 0000000..de2b024 Binary files /dev/null and b/Quartus/A1_Q3/db/asu.(2).cnf.hdb differ diff --git a/Quartus/A1_Q3/db/asu.asm.qmsg b/Quartus/A1_Q3/db/asu.asm.qmsg index ef6e475..8a4d4be 100644 --- a/Quartus/A1_Q3/db/asu.asm.qmsg +++ b/Quartus/A1_Q3/db/asu.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430466231 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430466231 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:01:06 2026 " "Processing started: Tue Sep 15 10:01:06 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430466231 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789430466231 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789430466232 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789430467233 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789430473784 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430474439 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:01:14 2026 " "Processing ended: Tue Sep 15 10:01:14 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430474439 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430474439 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430474439 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789430474439 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789454394416 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789454394416 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:39:54 2026 " "Processing started: Tue Sep 15 16:39:54 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789454394416 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789454394416 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789454394416 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789454395117 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789454400169 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "507 " "Peak virtual memory: 507 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789454400360 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:40:00 2026 " "Processing ended: Tue Sep 15 16:40:00 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789454400360 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789454400360 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789454400360 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789454400360 ""} diff --git a/Quartus/A1_Q3/db/asu.asm.rdb b/Quartus/A1_Q3/db/asu.asm.rdb index 84e837c..c9bbe9f 100644 Binary files a/Quartus/A1_Q3/db/asu.asm.rdb and b/Quartus/A1_Q3/db/asu.asm.rdb differ diff --git a/Quartus/A1_Q3/db/asu.cmp.bpm b/Quartus/A1_Q3/db/asu.cmp.bpm index bb3800f..28a8014 100644 Binary files a/Quartus/A1_Q3/db/asu.cmp.bpm and b/Quartus/A1_Q3/db/asu.cmp.bpm differ diff --git a/Quartus/A1_Q3/db/asu.cmp.cdb b/Quartus/A1_Q3/db/asu.cmp.cdb index c52fdeb..7720b1d 100644 Binary files a/Quartus/A1_Q3/db/asu.cmp.cdb and b/Quartus/A1_Q3/db/asu.cmp.cdb differ diff --git a/Quartus/A1_Q3/db/asu.cmp.hdb b/Quartus/A1_Q3/db/asu.cmp.hdb index 25277aa..65a59c0 100644 Binary files a/Quartus/A1_Q3/db/asu.cmp.hdb and b/Quartus/A1_Q3/db/asu.cmp.hdb differ diff --git a/Quartus/A1_Q3/db/asu.cmp.idb b/Quartus/A1_Q3/db/asu.cmp.idb index 7402336..5d30a41 100644 Binary files a/Quartus/A1_Q3/db/asu.cmp.idb and b/Quartus/A1_Q3/db/asu.cmp.idb differ diff --git a/Quartus/A1_Q3/db/asu.cmp.logdb b/Quartus/A1_Q3/db/asu.cmp.logdb index 128f290..aaa6372 100644 --- a/Quartus/A1_Q3/db/asu.cmp.logdb +++ b/Quartus/A1_Q3/db/asu.cmp.logdb @@ -29,9 +29,9 @@ IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, -IO_RULES_MATRIX,Total Pass,0;15;15;0;0;15;15;0;0;0;0;0;0;6;0;0;0;0;6;0;0;0;0;6;0;15;15;0, +IO_RULES_MATRIX,Total Pass,0;22;22;0;0;23;22;0;0;0;0;0;0;14;0;0;0;0;14;0;0;0;0;14;0;23;23;0, IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,15;0;0;15;15;0;0;15;15;15;15;15;15;9;15;15;15;15;9;15;15;15;15;9;15;0;0;15, +IO_RULES_MATRIX,Total Inapplicable,23;1;1;23;23;0;1;23;23;23;23;23;23;9;23;23;23;23;9;23;23;23;23;9;23;0;0;23, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, IO_RULES_MATRIX,OUT_1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,OUT_1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, @@ -39,15 +39,23 @@ IO_RULES_MATRIX,OUT_1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;P IO_RULES_MATRIX,OUT_1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,COUT[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,OUT_CIN[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,out_seg_1[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,op[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,B[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,B[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,A[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,B[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,B[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_SUMMARY,Total I/O Rules,28, IO_RULES_SUMMARY,Number of I/O Rules Passed,9, IO_RULES_SUMMARY,Number of I/O Rules Failed,0, diff --git a/Quartus/A1_Q3/db/asu.cmp.rdb b/Quartus/A1_Q3/db/asu.cmp.rdb index 519bdd7..b35dc39 100644 Binary files a/Quartus/A1_Q3/db/asu.cmp.rdb and b/Quartus/A1_Q3/db/asu.cmp.rdb differ diff --git a/Quartus/A1_Q3/db/asu.db_info b/Quartus/A1_Q3/db/asu.db_info index 9629701..cc26bf8 100644 --- a/Quartus/A1_Q3/db/asu.db_info +++ b/Quartus/A1_Q3/db/asu.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Tue Sep 15 09:59:44 2026 +Creation_Time = Tue Sep 15 16:33:04 2026 diff --git a/Quartus/A1_Q3/db/asu.eda.qmsg b/Quartus/A1_Q3/db/asu.eda.qmsg index 2224e88..ae42fd0 100644 --- a/Quartus/A1_Q3/db/asu.eda.qmsg +++ b/Quartus/A1_Q3/db/asu.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430487080 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430487080 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:01:26 2026 " "Processing started: Tue Sep 15 10:01:26 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430487080 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430487080 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430487080 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789430488184 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "asu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/ simulation " "Generated file asu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789430488688 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430488724 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:01:28 2026 " "Processing ended: Tue Sep 15 10:01:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430488724 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430488724 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430488724 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430488724 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789454408641 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789454408642 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:40:08 2026 " "Processing started: Tue Sep 15 16:40:08 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789454408642 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789454408642 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789454408642 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789454409468 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "asu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/ simulation " "Generated file asu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789454409516 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "666 " "Peak virtual memory: 666 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789454409548 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:40:09 2026 " "Processing ended: Tue Sep 15 16:40:09 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789454409548 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789454409548 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789454409548 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789454409548 ""} diff --git a/Quartus/A1_Q3/db/asu.fit.qmsg b/Quartus/A1_Q3/db/asu.fit.qmsg index fcff152..d590f2e 100644 --- a/Quartus/A1_Q3/db/asu.fit.qmsg +++ b/Quartus/A1_Q3/db/asu.fit.qmsg @@ -1,44 +1,45 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789430425537 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789430425538 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "asu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"asu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789430425560 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430425678 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430425678 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789430426269 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789430426326 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789430426505 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789430435756 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430435806 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789430436270 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430436271 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430436271 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789430436272 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789430436272 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789430436272 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789430436272 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789430436272 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789430436272 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430436361 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789430444964 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789430444965 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789430444965 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789430444967 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789430444968 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789430444968 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789430444968 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789430444972 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789430445092 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430446014 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789430446710 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789430447029 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430447030 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789430448297 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789430456410 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789430456410 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789430456726 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789430456726 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789430456726 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430456731 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789430458277 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430458321 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430458745 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430458745 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430459691 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:05 " "Fitter post-fit operations ending: elapsed time is 00:00:05" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430463035 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789430463365 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1380 " "Peak virtual memory: 1380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430464105 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:01:04 2026 " "Processing ended: Tue Sep 15 10:01:04 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430464105 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:41 " "Elapsed time: 00:00:41" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430464105 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:52 " "Total CPU time (on all processors): 00:00:52" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430464105 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789430464105 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789454362614 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789454362614 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "asu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"asu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789454362619 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789454362689 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789454362689 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789454363117 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789454363144 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789454363197 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 23 " "No exact pin location assignment(s) for 1 pins of 23 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789454363455 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789454370323 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789454370380 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789454370383 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789454370383 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789454370383 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789454370383 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789454370384 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789454370384 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789454370384 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789454370384 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789454370384 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789454370407 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789454376903 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789454376904 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789454376904 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789454376905 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789454376906 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789454376907 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789454376907 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789454376911 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789454377049 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789454377960 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789454378619 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789454378881 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789454378881 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789454379535 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X33_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11"} { { 12 { 0 ""} 23 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789454385783 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789454385783 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789454386120 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789454386120 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789454386120 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789454386123 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789454387600 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789454387636 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789454388037 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789454388037 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789454388679 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789454391553 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789454391817 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1340 " "Peak virtual memory: 1340 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789454392460 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:39:52 2026 " "Processing ended: Tue Sep 15 16:39:52 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789454392460 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Elapsed time: 00:00:31" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789454392460 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:42 " "Total CPU time (on all processors): 00:00:42" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789454392460 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789454392460 ""} diff --git a/Quartus/A1_Q3/db/asu.hier_info b/Quartus/A1_Q3/db/asu.hier_info index 5302ca5..2502032 100644 --- a/Quartus/A1_Q3/db/asu.hier_info +++ b/Quartus/A1_Q3/db/asu.hier_info @@ -1,14 +1,14 @@ |asu +op[0] => Add1.IN10 op[0] => operand[3].OUTPUTSELECT op[0] => operand[2].OUTPUTSELECT op[0] => operand[1].OUTPUTSELECT op[0] => operand[0].OUTPUTSELECT -op[0] => _.DATAB -A[0] => _.DATAD -A[1] => _.DATAD -A[2] => _.DATAD +A[0] => Add0.IN4 +A[1] => Add0.IN3 +A[2] => Add0.IN2 +A[3] => Add0.IN1 A[3] => OUT_CIN.IN1 -A[3] => _.DATAD B[0] => operand[0].DATAB B[0] => operand[0].DATAA B[1] => operand[1].DATAB @@ -17,11 +17,65 @@ B[2] => operand[2].DATAB B[2] => operand[2].DATAA B[3] => operand[3].DATAB B[3] => operand[3].DATAA -OUT_1[0] <= _.SUM_OUT -OUT_1[1] <= _.SUM_OUT -OUT_1[2] <= _.SUM_OUT -OUT_1[3] <= _.SUM_OUT -COUT[0] <= _.SUM_OUT -OUT_CIN[0] <= OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[0] << OUT_1[0].DB_MAX_OUTPUT_PORT_TYPE +OUT_1[1] << OUT_1[1].DB_MAX_OUTPUT_PORT_TYPE +OUT_1[2] << OUT_1[2].DB_MAX_OUTPUT_PORT_TYPE +OUT_1[3] << OUT_1[3].DB_MAX_OUTPUT_PORT_TYPE +COUT[0] << Add1.DB_MAX_OUTPUT_PORT_TYPE +OUT_CIN[0] << OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE +out_seg_1[0] << seven_seg:dut.port2 +out_seg_1[1] << seven_seg:dut.port2 +out_seg_1[2] << seven_seg:dut.port2 +out_seg_1[3] << seven_seg:dut.port2 +out_seg_1[4] << seven_seg:dut.port2 +out_seg_1[5] << seven_seg:dut.port2 +out_seg_1[6] << seven_seg:dut.port2 +out_seg_1[7] << seven_seg:dut.port2 + + +|asu|seven_seg:dut +num[0] => Decoder0.IN3 +num[0] => Mux0.IN19 +num[0] => Mux1.IN19 +num[0] => Mux2.IN19 +num[0] => Mux3.IN19 +num[0] => Mux4.IN19 +num[0] => Mux5.IN19 +num[1] => Decoder0.IN2 +num[1] => Mux0.IN18 +num[1] => Mux1.IN18 +num[1] => Mux2.IN18 +num[1] => Mux3.IN18 +num[1] => Mux4.IN18 +num[1] => Mux5.IN18 +num[2] => Decoder0.IN1 +num[2] => Mux0.IN17 +num[2] => Mux1.IN17 +num[2] => Mux2.IN17 +num[2] => Mux3.IN17 +num[2] => Mux4.IN17 +num[2] => Mux5.IN17 +num[3] => Decoder0.IN0 +num[3] => Mux0.IN16 +num[3] => Mux1.IN16 +num[3] => Mux2.IN16 +num[3] => Mux3.IN16 +num[3] => Mux4.IN16 +num[3] => Mux5.IN16 +rbi_inv[0] => Mux0.IN15 +rbi_inv[0] => Mux1.IN15 +rbi_inv[0] => Mux2.IN15 +rbi_inv[0] => Mux3.IN15 +rbi_inv[0] => Mux4.IN15 +rbi_inv[0] => Mux5.IN15 +rbi_inv[0] => segments.DATAB +segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE +segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE diff --git a/Quartus/A1_Q3/db/asu.hif b/Quartus/A1_Q3/db/asu.hif index e50e045..a9651ed 100644 Binary files a/Quartus/A1_Q3/db/asu.hif and b/Quartus/A1_Q3/db/asu.hif differ diff --git a/Quartus/A1_Q3/db/asu.lpc.html b/Quartus/A1_Q3/db/asu.lpc.html index fbc5ab5..1643d3e 100644 --- a/Quartus/A1_Q3/db/asu.lpc.html +++ b/Quartus/A1_Q3/db/asu.lpc.html @@ -15,4 +15,20 @@ Input only Bidir Output only Bidir + +dut +5 +1 +0 +1 +8 +1 +1 +1 +0 +0 +0 +0 +0 + diff --git a/Quartus/A1_Q3/db/asu.lpc.rdb b/Quartus/A1_Q3/db/asu.lpc.rdb index 7be5d4c..29f9a96 100644 Binary files a/Quartus/A1_Q3/db/asu.lpc.rdb and b/Quartus/A1_Q3/db/asu.lpc.rdb differ diff --git a/Quartus/A1_Q3/db/asu.lpc.txt b/Quartus/A1_Q3/db/asu.lpc.txt index a463804..6985ec4 100644 --- a/Quartus/A1_Q3/db/asu.lpc.txt +++ b/Quartus/A1_Q3/db/asu.lpc.txt @@ -3,3 +3,5 @@ +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; dut ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/Quartus/A1_Q3/db/asu.map.bpm b/Quartus/A1_Q3/db/asu.map.bpm index 2582fb0..956eb1f 100644 Binary files a/Quartus/A1_Q3/db/asu.map.bpm and b/Quartus/A1_Q3/db/asu.map.bpm differ diff --git a/Quartus/A1_Q3/db/asu.map.cdb b/Quartus/A1_Q3/db/asu.map.cdb index 790b22d..d0bc2fd 100644 Binary files a/Quartus/A1_Q3/db/asu.map.cdb and b/Quartus/A1_Q3/db/asu.map.cdb differ diff --git a/Quartus/A1_Q3/db/asu.map.hdb b/Quartus/A1_Q3/db/asu.map.hdb index e8874eb..8bd8bb3 100644 Binary files a/Quartus/A1_Q3/db/asu.map.hdb and b/Quartus/A1_Q3/db/asu.map.hdb differ diff --git a/Quartus/A1_Q3/db/asu.map.qmsg b/Quartus/A1_Q3/db/asu.map.qmsg index 709b9ed..88bd951 100644 --- a/Quartus/A1_Q3/db/asu.map.qmsg +++ b/Quartus/A1_Q3/db/asu.map.qmsg @@ -1,11 +1,14 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430407159 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430407160 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:00:06 2026 " "Processing started: Tue Sep 15 10:00:06 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430407160 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430407160 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430407160 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789430407694 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789430407694 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430420346 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430420346 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "asu " "Elaborating entity \"asu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789430420541 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789430421709 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789430422213 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430422213 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789430422350 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789430422350 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789430422350 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789430422350 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430422361 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:00:22 2026 " "Processing ended: Tue Sep 15 10:00:22 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430422361 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430422361 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430422361 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430422361 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789454348355 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789454348356 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:39:08 2026 " "Processing started: Tue Sep 15 16:39:08 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789454348356 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789454348356 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789454348356 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789454348696 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789454348696 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv 2 2 " "Found 2 design units, including 2 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789454359362 ""} { "Info" "ISGN_ENTITY_NAME" "2 asu " "Found entity 2: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789454359362 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789454359362 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "asu " "Elaborating entity \"asu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789454359500 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg:dut " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg:dut\"" { } { { "../../modules/asu.sv" "dut" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789454359502 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1789454360145 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[0\] GND " "Pin \"out_seg_1\[0\]\" is stuck at GND" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 9 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1789454360165 "|asu|out_seg_1[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1789454360165 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789454360297 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789454360752 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789454360752 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789454360818 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789454360818 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789454360818 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789454360818 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789454360833 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:39:20 2026 " "Processing ended: Tue Sep 15 16:39:20 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789454360833 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789454360833 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:28 " "Total CPU time (on all processors): 00:00:28" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789454360833 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789454360833 ""} diff --git a/Quartus/A1_Q3/db/asu.map.rdb b/Quartus/A1_Q3/db/asu.map.rdb index 6b4c376..69d95e5 100644 Binary files a/Quartus/A1_Q3/db/asu.map.rdb and b/Quartus/A1_Q3/db/asu.map.rdb differ diff --git a/Quartus/A1_Q3/db/asu.map_bb.cdb b/Quartus/A1_Q3/db/asu.map_bb.cdb index f2f417b..b805779 100644 Binary files a/Quartus/A1_Q3/db/asu.map_bb.cdb and b/Quartus/A1_Q3/db/asu.map_bb.cdb differ diff --git a/Quartus/A1_Q3/db/asu.map_bb.hdb b/Quartus/A1_Q3/db/asu.map_bb.hdb index 7a8990c..1d53cf7 100644 Binary files a/Quartus/A1_Q3/db/asu.map_bb.hdb and b/Quartus/A1_Q3/db/asu.map_bb.hdb differ diff --git a/Quartus/A1_Q3/db/asu.pre_map.hdb b/Quartus/A1_Q3/db/asu.pre_map.hdb index 7c431bb..511bca9 100644 Binary files a/Quartus/A1_Q3/db/asu.pre_map.hdb and b/Quartus/A1_Q3/db/asu.pre_map.hdb differ diff --git a/Quartus/A1_Q3/db/asu.routing.rdb b/Quartus/A1_Q3/db/asu.routing.rdb index e147f93..0873709 100644 Binary files a/Quartus/A1_Q3/db/asu.routing.rdb and b/Quartus/A1_Q3/db/asu.routing.rdb differ diff --git a/Quartus/A1_Q3/db/asu.rtlv.hdb b/Quartus/A1_Q3/db/asu.rtlv.hdb index 03a689b..80f5417 100644 Binary files a/Quartus/A1_Q3/db/asu.rtlv.hdb and b/Quartus/A1_Q3/db/asu.rtlv.hdb differ diff --git a/Quartus/A1_Q3/db/asu.rtlv_sg.cdb b/Quartus/A1_Q3/db/asu.rtlv_sg.cdb index e8fd017..1c4d1dd 100644 Binary files a/Quartus/A1_Q3/db/asu.rtlv_sg.cdb and b/Quartus/A1_Q3/db/asu.rtlv_sg.cdb differ diff --git a/Quartus/A1_Q3/db/asu.rtlv_sg_swap.cdb b/Quartus/A1_Q3/db/asu.rtlv_sg_swap.cdb index 5e9299c..e196177 100644 Binary files a/Quartus/A1_Q3/db/asu.rtlv_sg_swap.cdb and b/Quartus/A1_Q3/db/asu.rtlv_sg_swap.cdb differ diff --git a/Quartus/A1_Q3/db/asu.sta.qmsg b/Quartus/A1_Q3/db/asu.sta.qmsg index 96c4db1..0a57aad 100644 --- a/Quartus/A1_Q3/db/asu.sta.qmsg +++ b/Quartus/A1_Q3/db/asu.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430476722 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430476723 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:01:16 2026 " "Processing started: Tue Sep 15 10:01:16 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430476723 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430476723 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q3 -c asu " "Command: quartus_sta A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430476723 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789430476825 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789430477740 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789430477740 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430477834 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430477834 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789430478816 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430478817 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430478818 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430478818 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430478819 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430478819 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789430478821 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789430478830 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430478831 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478832 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478842 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478843 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478845 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478846 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478847 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430478852 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430478922 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430481155 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430481259 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430481259 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430481260 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430481260 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481262 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481265 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481267 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481268 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481269 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481270 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430481272 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430481594 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430482658 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430482705 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430482705 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430482706 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430482706 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482707 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482708 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482709 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482710 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482710 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430482712 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430482932 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430482932 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430482932 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430482933 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482934 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482936 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482937 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482938 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482939 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430484833 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430484833 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "785 " "Peak virtual memory: 785 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430484859 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:01:24 2026 " "Processing ended: Tue Sep 15 10:01:24 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430484859 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430484859 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430484859 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789430484859 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789454401998 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789454401999 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:40:01 2026 " "Processing started: Tue Sep 15 16:40:01 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789454401999 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789454401999 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q3 -c asu " "Command: quartus_sta A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789454401999 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789454402068 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789454402536 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789454402536 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789454402608 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789454402608 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789454403185 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789454403186 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789454403186 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789454403187 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789454403187 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789454403187 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789454403188 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789454403192 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789454403192 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454403193 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454403197 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454403198 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454403198 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454403199 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454403200 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789454403202 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789454403246 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789454404289 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789454404375 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789454404375 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789454404375 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789454404376 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454404376 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454404377 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454404378 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454404379 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454404380 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454404380 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789454404382 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789454404630 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789454405237 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789454405284 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789454405284 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789454405284 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789454405284 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405286 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405286 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405287 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405288 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405289 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789454405290 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789454405432 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789454405433 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789454405433 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789454405433 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405434 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405435 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405436 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405437 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789454405437 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789454406977 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789454406978 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "750 " "Peak virtual memory: 750 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789454407005 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:40:07 2026 " "Processing ended: Tue Sep 15 16:40:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789454407005 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789454407005 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789454407005 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789454407005 ""} diff --git a/Quartus/A1_Q3/db/asu.sta.rdb b/Quartus/A1_Q3/db/asu.sta.rdb index 8f83a98..0fa21c3 100644 Binary files a/Quartus/A1_Q3/db/asu.sta.rdb and b/Quartus/A1_Q3/db/asu.sta.rdb differ diff --git a/Quartus/A1_Q3/db/asu.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A1_Q3/db/asu.sta_cmp.7_H6_slow_1100mv_85c.tdb index 61dfb9d..da41d83 100644 Binary files a/Quartus/A1_Q3/db/asu.sta_cmp.7_H6_slow_1100mv_85c.tdb and b/Quartus/A1_Q3/db/asu.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_0c.ddb index 9f981ce..be21359 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_85c.ddb index f4bb6cb..1b1e1f5 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.fastest_slow_1100mv_0c.ddb index 1e5c999..e347d91 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.fastest_slow_1100mv_0c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.fastest_slow_1100mv_85c.ddb index 6a24754..70cb94b 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.fastest_slow_1100mv_85c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_0c.ddb index 67154de..420be25 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_85c.ddb index d969c88..fe44d2e 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tmw_info b/Quartus/A1_Q3/db/asu.tmw_info index 6784514..20de926 100644 --- a/Quartus/A1_Q3/db/asu.tmw_info +++ b/Quartus/A1_Q3/db/asu.tmw_info @@ -1,7 +1,7 @@ -start_full_compilation:s:00:01:24 -start_analysis_synthesis:s:00:00:18-start_full_compilation +start_full_compilation:s:00:01:03 +start_analysis_synthesis:s:00:00:14-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:41-start_full_compilation -start_assembler:s:00:00:11-start_full_compilation -start_timing_analyzer:s:00:00:10-start_full_compilation -start_eda_netlist_writer:s:00:00:04-start_full_compilation +start_fitter:s:00:00:32-start_full_compilation +start_assembler:s:00:00:08-start_full_compilation +start_timing_analyzer:s:00:00:06-start_full_compilation +start_eda_netlist_writer:s:00:00:03-start_full_compilation diff --git a/Quartus/A1_Q3/db/asu.vpr.ammdb b/Quartus/A1_Q3/db/asu.vpr.ammdb index 0d0edda..024a6fd 100644 Binary files a/Quartus/A1_Q3/db/asu.vpr.ammdb and b/Quartus/A1_Q3/db/asu.vpr.ammdb differ diff --git a/Quartus/A1_Q3/db/asu_partition_pins.json b/Quartus/A1_Q3/db/asu_partition_pins.json index 5e52bf5..6b9e38f 100644 --- a/Quartus/A1_Q3/db/asu_partition_pins.json +++ b/Quartus/A1_Q3/db/asu_partition_pins.json @@ -27,16 +27,44 @@ "name" : "OUT_CIN[0]", "strict" : false }, + { + "name" : "out_seg_1[1]", + "strict" : false + }, + { + "name" : "out_seg_1[2]", + "strict" : false + }, + { + "name" : "out_seg_1[3]", + "strict" : false + }, + { + "name" : "out_seg_1[4]", + "strict" : false + }, + { + "name" : "out_seg_1[5]", + "strict" : false + }, + { + "name" : "out_seg_1[6]", + "strict" : false + }, + { + "name" : "out_seg_1[7]", + "strict" : false + }, { "name" : "op[0]", "strict" : false }, { - "name" : "A[3]", + "name" : "B[3]", "strict" : false }, { - "name" : "B[3]", + "name" : "A[3]", "strict" : false }, { @@ -47,21 +75,21 @@ "name" : "A[0]", "strict" : false }, - { - "name" : "A[1]", - "strict" : false - }, { "name" : "B[1]", "strict" : false }, { - "name" : "A[2]", + "name" : "A[1]", "strict" : false }, { "name" : "B[2]", "strict" : false + }, + { + "name" : "A[2]", + "strict" : false } ] } diff --git a/Quartus/A1_Q3/db/prev_cmp_A1_Q3.qmsg b/Quartus/A1_Q3/db/prev_cmp_A1_Q3.qmsg index 2aab1c1..ecc18bf 100644 --- a/Quartus/A1_Q3/db/prev_cmp_A1_Q3.qmsg +++ b/Quartus/A1_Q3/db/prev_cmp_A1_Q3.qmsg @@ -1,136 +1,10 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788926483802 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926483802 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:01:23 2026 " "Processing started: Wed Sep 9 14:01:23 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926483802 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788926483802 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788926483802 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788926484135 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788926484135 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788926493817 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788926493817 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "asu " "Elaborating entity \"asu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788926493967 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788926494810 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788926495220 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788926495220 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788926495353 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788926495353 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788926495353 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788926495353 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926495359 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:01:35 2026 " "Processing ended: Wed Sep 9 14:01:35 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926495359 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926495359 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926495359 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788926495359 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1788926497164 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926497164 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:01:36 2026 " "Processing started: Wed Sep 9 14:01:36 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926497164 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1788926497164 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_fit --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1788926497164 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1788926497419 ""} -{ "Info" "0" "" "Project = A1_Q3" { } { } 0 0 "Project = A1_Q3" 0 0 "Fitter" 0 0 1788926497420 ""} -{ "Info" "0" "" "Revision = asu" { } { } 0 0 "Revision = asu" 0 0 "Fitter" 0 0 1788926497420 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788926497623 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788926497623 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "asu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"asu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788926497629 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788926497701 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788926497701 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788926498129 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788926498176 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788926498329 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "15 15 " "No exact pin location assignment(s) for 15 pins of 15 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1788926498595 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788926505300 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926505385 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788926505403 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788926505404 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788926505404 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788926505404 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788926505404 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788926505404 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788926505404 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788926505405 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788926505405 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926505428 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788926511434 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788926511435 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788926511435 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788926511436 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788926511437 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788926511438 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788926511438 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788926511441 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788926511505 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926512859 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788926513888 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788926514218 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926514218 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788926514811 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y24 X68_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36"} { { 12 { 0 ""} 57 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788926520294 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788926520294 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788926520439 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788926520439 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788926520439 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926520441 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788926521315 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788926521347 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788926521727 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788926521728 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788926522272 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926524805 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1338 " "Peak virtual memory: 1338 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926525617 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:02:05 2026 " "Processing ended: Wed Sep 9 14:02:05 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926525617 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926525617 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926525617 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788926525617 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1788926527388 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926527389 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:02:07 2026 " "Processing started: Wed Sep 9 14:02:07 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926527389 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788926527389 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788926527389 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788926528043 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788926532635 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "517 " "Peak virtual memory: 517 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926532856 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:02:12 2026 " "Processing ended: Wed Sep 9 14:02:12 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926532856 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926532856 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926532856 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788926532856 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1788926533654 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1788926534483 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926534483 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:02:14 2026 " "Processing started: Wed Sep 9 14:02:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926534483 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788926534483 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q3 -c asu " "Command: quartus_sta A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788926534483 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788926534543 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788926535026 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788926535026 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926535101 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926535101 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788926535698 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926535698 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788926535698 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788926535699 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788926535699 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788926535699 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788926535700 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788926535704 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788926535704 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535706 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535713 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535714 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535715 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535716 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535717 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788926535720 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788926535763 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788926536755 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926536841 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788926536841 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788926536841 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788926536842 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536842 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536844 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536845 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536845 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536846 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536847 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788926536848 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788926537107 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788926537653 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926537695 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788926537695 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788926537695 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788926537695 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537697 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537698 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537698 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537699 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537700 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788926537702 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926537846 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788926537846 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788926537847 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788926537847 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537848 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537849 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537850 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537850 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537851 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788926539453 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788926539453 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "760 " "Peak virtual memory: 760 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926539482 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:02:19 2026 " "Processing ended: Wed Sep 9 14:02:19 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926539482 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926539482 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926539482 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788926539482 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1788926541113 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926541114 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:02:20 2026 " "Processing started: Wed Sep 9 14:02:20 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926541114 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788926541114 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788926541114 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788926541877 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "asu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/ simulation " "Generated file asu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788926541950 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "659 " "Peak virtual memory: 659 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926541988 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:02:21 2026 " "Processing ended: Wed Sep 9 14:02:21 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926541988 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926541988 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926541988 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788926541988 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus Prime Full Compilation was successful. 0 errors, 15 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788926542651 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789453676979 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789453676979 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:27:56 2026 " "Processing started: Tue Sep 15 16:27:56 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789453676979 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789453676979 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789453676980 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789453677286 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789453677286 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv 2 2 " "Found 2 design units, including 2 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789453686691 ""} { "Info" "ISGN_ENTITY_NAME" "2 asu " "Found entity 2: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789453686691 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789453686691 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "asu " "Elaborating entity \"asu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789453686847 ""} +{ "Error" "ESGN_ENTITY_IS_MISSING" "dut sevenseg " "Node instance \"dut\" instantiates undefined entity \"sevenseg\". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP." { } { { "../../modules/asu.sv" "dut" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 24 0 0 } } } 0 12006 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP." 0 0 "Analysis & Synthesis" 0 -1 1789453686858 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789453686913 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Sep 15 16:28:06 2026 " "Processing ended: Tue Sep 15 16:28:06 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789453686913 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789453686913 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789453686913 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789453686913 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1 " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789453687579 ""} diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.ammdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.ammdb index 0943504..1fd766e 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.ammdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.ammdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.cdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.cdb index eabbe59..a333e0f 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.cdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.cdb index dc33447..943c97b 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.hdb index ec27649..9e9adc8 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hdb index c24af12..3e9fdf8 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.rcfdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.rcfdb index 7a2c311..6941377 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.rcfdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.rcfdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.cdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.cdb index 89ef368..5fea832 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.cdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.cdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.dpi b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.dpi index 68c02fa..da490a3 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.dpi and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.dpi differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.cdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.cdb index f98b030..259319f 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.cdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.hdb index 79fb0c7..56b2996 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hdb index e9567a2..c411147 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.rrp.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.rrp.hdb index 9a60dd0..9aefa70 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.rrp.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.rrp.hdb differ diff --git a/Quartus/A1_Q3/output_files/asu.asm.rpt b/Quartus/A1_Q3/output_files/asu.asm.rpt index ccbf8fe..a1886be 100644 --- a/Quartus/A1_Q3/output_files/asu.asm.rpt +++ b/Quartus/A1_Q3/output_files/asu.asm.rpt @@ -1,5 +1,5 @@ Assembler report for asu -Tue Sep 15 10:01:14 2026 +Tue Sep 15 16:40:00 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Sep 15 10:01:14 2026 ; +; Assembler Status ; Successful - Tue Sep 15 16:40:00 2026 ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; ; Family ; Cyclone V ; @@ -67,8 +67,8 @@ on the Quartus Prime software download page. +----------------+------------------+ ; Option ; Setting ; +----------------+------------------+ -; JTAG usercode ; 0x00781610 ; -; Checksum ; 0x00781610 ; +; JTAG usercode ; 0x00784D66 ; +; Checksum ; 0x00784D66 ; +----------------+------------------+ @@ -78,14 +78,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:01:06 2026 + Info: Processing started: Tue Sep 15 16:39:54 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 521 megabytes - Info: Processing ended: Tue Sep 15 10:01:14 2026 - Info: Elapsed time: 00:00:08 - Info: Total CPU time (on all processors): 00:00:08 + Info: Peak virtual memory: 507 megabytes + Info: Processing ended: Tue Sep 15 16:40:00 2026 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:06 diff --git a/Quartus/A1_Q3/output_files/asu.done b/Quartus/A1_Q3/output_files/asu.done index 590915f..2104aee 100644 --- a/Quartus/A1_Q3/output_files/asu.done +++ b/Quartus/A1_Q3/output_files/asu.done @@ -1 +1 @@ -Tue Sep 15 10:01:29 2026 +Tue Sep 15 16:40:10 2026 diff --git a/Quartus/A1_Q3/output_files/asu.eda.rpt b/Quartus/A1_Q3/output_files/asu.eda.rpt index 48be722..70a1115 100644 --- a/Quartus/A1_Q3/output_files/asu.eda.rpt +++ b/Quartus/A1_Q3/output_files/asu.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for asu -Tue Sep 15 10:01:28 2026 +Tue Sep 15 16:40:09 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:01:28 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Sep 15 16:40:09 2026 ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; ; Family ; Cyclone V ; @@ -81,14 +81,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:01:26 2026 + Info: Processing started: Tue Sep 15 16:40:08 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file asu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 658 megabytes - Info: Processing ended: Tue Sep 15 10:01:28 2026 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:02 + Info: Peak virtual memory: 666 megabytes + Info: Processing ended: Tue Sep 15 16:40:09 2026 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A1_Q3/output_files/asu.fit.rpt b/Quartus/A1_Q3/output_files/asu.fit.rpt index f1c7b12..0ae7240 100644 --- a/Quartus/A1_Q3/output_files/asu.fit.rpt +++ b/Quartus/A1_Q3/output_files/asu.fit.rpt @@ -1,5 +1,5 @@ Fitter report for asu -Tue Sep 15 10:01:03 2026 +Tue Sep 15 16:39:51 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -58,16 +58,16 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Sep 15 10:01:03 2026 ; +; Fitter Status ; Successful - Tue Sep 15 16:39:51 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; ; Family ; Cyclone V ; ; Device ; 5CGXFC5C6F27C7 ; ; Timing Models ; Final ; -; Logic utilization (in ALMs) ; 4 / 29,080 ( < 1 % ) ; +; Logic utilization (in ALMs) ; 8 / 29,080 ( < 1 % ) ; ; Total registers ; 0 ; -; Total pins ; 15 / 364 ( 4 % ) ; +; Total pins ; 23 / 364 ( 6 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; ; Total RAM Blocks ; 0 / 446 ( 0 % ) ; @@ -153,7 +153,7 @@ on the Quartus Prime software download page. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.3% ; +; Processor 2 ; 0.4% ; +----------------------------+-------------+ @@ -173,8 +173,8 @@ on the Quartus Prime software download page. ; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; +---------------------+-------------------+----------------------------+--------------------------+ ; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; -; -- Achieved ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; +; -- Requested ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ; +; -- Achieved ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ; ; ; ; ; ; ; Routing (by net) ; ; ; ; ; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; @@ -197,7 +197,7 @@ on the Quartus Prime software download page. +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 37 ) ; N/A ; Source File ; N/A ; ; +; Top ; 0.00 % ( 0 / 61 ) ; N/A ; Source File ; N/A ; ; ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ @@ -213,11 +213,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------------------------------------------------------------+--------------------+-------+ ; Resource ; Usage ; % ; +-------------------------------------------------------------+--------------------+-------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 29,080 ; < 1 % ; -; ALMs needed [=A-B+C] ; 4 ; ; -; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 29,080 ; < 1 % ; +; Logic utilization (ALMs needed / total ALMs on device) ; 8 / 29,080 ; < 1 % ; +; ALMs needed [=A-B+C] ; 8 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29,080 ; < 1 % ; ; [a] ALMs used for LUT logic and registers ; 0 ; ; -; [b] ALMs used for LUT logic ; 4 ; ; +; [b] ALMs used for LUT logic ; 8 ; ; ; [c] ALMs used for registers ; 0 ; ; ; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; ; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ; @@ -233,12 +233,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- Logic LABs ; 2 ; ; ; -- Memory LABs (up to half of total LABs) ; 0 ; ; ; ; ; ; -; Combinational ALUT usage for logic ; 7 ; ; +; Combinational ALUT usage for logic ; 15 ; ; ; -- 7 input functions ; 0 ; ; ; -- 6 input functions ; 0 ; ; ; -- 5 input functions ; 0 ; ; -; -- 4 input functions ; 1 ; ; -; -- <=3 input functions ; 6 ; ; +; -- 4 input functions ; 8 ; ; +; -- <=3 input functions ; 7 ; ; ; Combinational ALUT usage for route-throughs ; 0 ; ; ; ; ; ; ; Dedicated logic registers ; 0 ; ; @@ -250,7 +250,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- Routing optimization registers ; 0 ; ; ; ; ; ; ; Virtual pins ; 0 ; ; -; I/O pins ; 15 / 364 ; 4 % ; +; I/O pins ; 23 / 364 ; 6 % ; ; -- Clock pins ; 0 / 14 ; 0 % ; ; -- Dedicated input pins ; 0 / 23 ; 0 % ; ; ; ; ; @@ -281,12 +281,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Channel PLLs ; 0 / 6 ; 0 % ; ; Impedance control blocks ; 0 / 3 ; 0 % ; ; Hard Memory Controllers ; 0 / 2 ; 0 % ; -; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; ; -; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.5% ; ; -; Maximum fan-out ; 5 ; ; -; Highest non-global fan-out ; 5 ; ; -; Total fan-out ; 41 ; ; -; Average fan-out ; 1.11 ; ; +; Average interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.1% ; ; +; Peak interconnect usage (total/H/V) ; 0.3% / 0.2% / 0.5% ; ; +; Maximum fan-out ; 10 ; ; +; Highest non-global fan-out ; 9 ; ; +; Total fan-out ; 86 ; ; +; Average fan-out ; 1.41 ; ; +-------------------------------------------------------------+--------------------+-------+ @@ -295,11 +295,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------------------------------------------------------------+---------------------+--------------------------------+ ; Statistic ; Top ; hard_block:auto_generated_inst ; +-------------------------------------------------------------+---------------------+--------------------------------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; -; ALMs needed [=A-B+C] ; 4 ; 0 ; -; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; Logic utilization (ALMs needed / total ALMs on device) ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 8 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; ; [a] ALMs used for LUT logic and registers ; 0 ; 0 ; -; [b] ALMs used for LUT logic ; 4 ; 0 ; +; [b] ALMs used for LUT logic ; 8 ; 0 ; ; [c] ALMs used for registers ; 0 ; 0 ; ; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; ; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; @@ -315,12 +315,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- Logic LABs ; 2 ; 0 ; ; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; ; ; ; ; -; Combinational ALUT usage for logic ; 7 ; 0 ; +; Combinational ALUT usage for logic ; 15 ; 0 ; ; -- 7 input functions ; 0 ; 0 ; ; -- 6 input functions ; 0 ; 0 ; ; -- 5 input functions ; 0 ; 0 ; -; -- 4 input functions ; 1 ; 0 ; -; -- <=3 input functions ; 6 ; 0 ; +; -- 4 input functions ; 8 ; 0 ; +; -- <=3 input functions ; 7 ; 0 ; ; Combinational ALUT usage for route-throughs ; 0 ; 0 ; ; Memory ALUT usage ; 0 ; 0 ; ; -- 64-address deep ; 0 ; 0 ; @@ -336,7 +336,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; ; ; ; ; ; ; ; ; Virtual pins ; 0 ; 0 ; -; I/O pins ; 15 ; 0 ; +; I/O pins ; 23 ; 0 ; ; I/O registers ; 0 ; 0 ; ; Total block memory bits ; 0 ; 0 ; ; Total block memory implementation bits ; 0 ; 0 ; @@ -348,7 +348,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- Registered Output Connections ; 0 ; 0 ; ; ; ; ; ; Internal Connections ; ; ; -; -- Total Connections ; 45 ; 0 ; +; -- Total Connections ; 86 ; 0 ; ; -- Registered Connections ; 0 ; 0 ; ; ; ; ; ; External Connections ; ; ; @@ -357,7 +357,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; ; ; ; ; Partition Interface ; ; ; ; -- Input Ports ; 9 ; 0 ; -; -- Output Ports ; 6 ; 0 ; +; -- Output Ports ; 14 ; 0 ; ; -- Bidir Ports ; 0 ; 0 ; ; ; ; ; ; Registered Ports ; ; ; @@ -389,40 +389,48 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; B[1] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; ; B[2] ; V10 ; 3B ; 17 ; 0 ; 74 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; ; B[3] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; -; op[0] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; op[0] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; -+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ -; COUT[0] ; J8 ; 8A ; 14 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; -; OUT_1[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; -; OUT_1[1] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; -; OUT_1[2] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; -; OUT_1[3] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; -; OUT_CIN[0] ; L7 ; 8A ; 10 ; 61 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; -+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; COUT[0] ; J8 ; 8A ; 14 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; OUT_1[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; OUT_1[1] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; OUT_1[2] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; OUT_1[3] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; OUT_CIN[0] ; L7 ; 8A ; 10 ; 61 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[0] ; A17 ; 7A ; 55 ; 61 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; out_seg_1[1] ; V19 ; 4A ; 66 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[2] ; V18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[3] ; V17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[4] ; W18 ; 4A ; 66 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[5] ; Y20 ; 4A ; 65 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[6] ; Y19 ; 4A ; 65 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; out_seg_1[7] ; Y18 ; 4A ; 62 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ -+---------------------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+-----------------+---------------+--------------+---------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; -+----------+-----------------+---------------+--------------+---------------+ -; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 3B ; 6 / 32 ( 19 % ) ; 1.2V ; -- ; 2.5V ; -; 4A ; 3 / 80 ( 4 % ) ; 1.2V ; -- ; 2.5V ; -; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 8A ; 6 / 32 ( 19 % ) ; 2.5V ; -- ; 2.5V ; -+----------+-----------------+---------------+--------------+---------------+ ++----------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+------------------+---------------+--------------+---------------+ +; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 6 / 32 ( 19 % ) ; 1.2V ; -- ; 2.5V ; +; 4A ; 10 / 80 ( 13 % ) ; 1.2V ; -- ; 2.5V ; +; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 1 / 80 ( 1 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 6 / 32 ( 19 % ) ; 2.5V ; -- ; 2.5V ; ++----------+------------------+---------------+--------------+---------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -445,7 +453,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; A14 ; 300 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; A15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; A16 ; 294 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A17 ; 292 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 292 ; 7A ; out_seg_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; A18 ; 290 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; A19 ; 288 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; A20 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -1040,9 +1048,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V18 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V19 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V17 ; 154 ; 4A ; out_seg_1[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; V18 ; 156 ; 4A ; out_seg_1[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; V19 ; 164 ; 4A ; out_seg_1[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; @@ -1067,7 +1075,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 162 ; 4A ; out_seg_1[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; @@ -1093,9 +1101,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 153 ; 4A ; out_seg_1[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; Y19 ; 159 ; 4A ; out_seg_1[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; Y20 ; 161 ; 4A ; out_seg_1[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; @@ -1106,18 +1114,27 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu Note: Pin directions (input, output or bidir) are based on device operating in user mode. -+--------------------------------------------+ -; I/O Assignment Warnings ; -+------------+-------------------------------+ -; Pin Name ; Reason ; -+------------+-------------------------------+ -; OUT_1[0] ; Incomplete set of assignments ; -; OUT_1[1] ; Incomplete set of assignments ; -; OUT_1[2] ; Incomplete set of assignments ; -; OUT_1[3] ; Incomplete set of assignments ; -; COUT[0] ; Incomplete set of assignments ; -; OUT_CIN[0] ; Incomplete set of assignments ; -+------------+-------------------------------+ ++-----------------------------------------------------+ +; I/O Assignment Warnings ; ++--------------+--------------------------------------+ +; Pin Name ; Reason ; ++--------------+--------------------------------------+ +; OUT_1[0] ; Incomplete set of assignments ; +; OUT_1[1] ; Incomplete set of assignments ; +; OUT_1[2] ; Incomplete set of assignments ; +; OUT_1[3] ; Incomplete set of assignments ; +; COUT[0] ; Incomplete set of assignments ; +; OUT_CIN[0] ; Incomplete set of assignments ; +; out_seg_1[0] ; Incomplete set of assignments ; +; out_seg_1[1] ; Missing drive strength and slew rate ; +; out_seg_1[2] ; Missing drive strength and slew rate ; +; out_seg_1[3] ; Missing drive strength and slew rate ; +; out_seg_1[4] ; Missing drive strength and slew rate ; +; out_seg_1[5] ; Missing drive strength and slew rate ; +; out_seg_1[6] ; Missing drive strength and slew rate ; +; out_seg_1[7] ; Missing drive strength and slew rate ; +; out_seg_1[0] ; Missing location assignment ; ++--------------+--------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1125,32 +1142,41 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ -; |asu ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 15 ; 0 ; |asu ; asu ; work ; +; |asu ; 7.5 (4.0) ; 7.5 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 15 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 23 ; 0 ; |asu ; asu ; work ; +; |seven_seg:dut| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |asu|seven_seg:dut ; seven_seg ; work ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. -+---------------------------------------------------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ -; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; -+------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ -; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; COUT[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; OUT_CIN[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -+------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ ++-----------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; COUT[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_CIN[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; out_seg_1[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; op[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ++--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +---------------------------------------------------+ @@ -1159,29 +1185,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Source Pin / Fanout ; Pad To Core Index ; Setting ; +---------------------+-------------------+---------+ ; op[0] ; ; ; -; - _~1 ; 0 ; 0 ; -; - _~5 ; 0 ; 0 ; -; - _~9 ; 0 ; 0 ; -; - _~13 ; 0 ; 0 ; -; - OUT_CIN~0 ; 0 ; 0 ; -; A[3] ; ; ; -; - _~13 ; 0 ; 0 ; -; - OUT_CIN~0 ; 0 ; 0 ; +; - Add0~22 ; 1 ; 0 ; +; - Add0~1 ; 1 ; 0 ; +; - Add0~5 ; 1 ; 0 ; +; - Add0~9 ; 1 ; 0 ; +; - Add0~13 ; 1 ; 0 ; +; - OUT_CIN~0 ; 1 ; 0 ; ; B[3] ; ; ; -; - _~13 ; 0 ; 0 ; -; - OUT_CIN~0 ; 0 ; 0 ; +; - Add0~13 ; 1 ; 0 ; +; - OUT_CIN~0 ; 1 ; 0 ; +; A[3] ; ; ; +; - Add0~13 ; 1 ; 0 ; +; - OUT_CIN~0 ; 1 ; 0 ; ; B[0] ; ; ; -; - _~1 ; 0 ; 0 ; +; - Add0~1 ; 0 ; 0 ; ; A[0] ; ; ; -; - _~1 ; 1 ; 0 ; -; A[1] ; ; ; -; - _~5 ; 1 ; 0 ; +; - Add0~1 ; 1 ; 0 ; ; B[1] ; ; ; -; - _~5 ; 1 ; 0 ; -; A[2] ; ; ; -; - _~9 ; 1 ; 0 ; +; - Add0~5 ; 0 ; 0 ; +; A[1] ; ; ; +; - Add0~5 ; 1 ; 0 ; ; B[2] ; ; ; -; - _~9 ; 1 ; 0 ; +; - Add0~9 ; 1 ; 0 ; +; A[2] ; ; ; +; - Add0~9 ; 1 ; 0 ; +---------------------+-------------------+---------+ @@ -1190,22 +1217,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------------------------+------------------------+ ; Routing Resource Type ; Usage ; +------------------------------+------------------------+ -; Block interconnects ; 15 / 217,884 ( < 1 % ) ; -; C12 interconnects ; 8 / 10,080 ( < 1 % ) ; -; C2 interconnects ; 8 / 87,208 ( < 1 % ) ; -; C4 interconnects ; 77 / 41,360 ( < 1 % ) ; +; Block interconnects ; 22 / 217,884 ( < 1 % ) ; +; C12 interconnects ; 0 / 10,080 ( 0 % ) ; +; C2 interconnects ; 18 / 87,208 ( < 1 % ) ; +; C4 interconnects ; 95 / 41,360 ( < 1 % ) ; ; DQS bus muxes ; 0 / 21 ( 0 % ) ; ; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; ; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; ; Direct links ; 0 / 217,884 ( 0 % ) ; ; Global clocks ; 0 / 16 ( 0 % ) ; ; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; -; Local interconnects ; 1 / 58,160 ( < 1 % ) ; +; Local interconnects ; 4 / 58,160 ( < 1 % ) ; ; Quadrant clocks ; 0 / 88 ( 0 % ) ; -; R14 interconnects ; 6 / 9,228 ( < 1 % ) ; -; R14/C12 interconnect drivers ; 12 / 15,096 ( < 1 % ) ; -; R3 interconnects ; 15 / 94,896 ( < 1 % ) ; -; R6 interconnects ; 9 / 194,640 ( < 1 % ) ; +; R14 interconnects ; 14 / 9,228 ( < 1 % ) ; +; R14/C12 interconnect drivers ; 14 / 15,096 ( < 1 % ) ; +; R3 interconnects ; 25 / 94,896 ( < 1 % ) ; +; R6 interconnects ; 48 / 194,640 ( < 1 % ) ; ; Spine clocks ; 0 / 180 ( 0 % ) ; ; Wire stub REs ; 0 / 11,606 ( 0 % ) ; +------------------------------+------------------------+ @@ -1261,31 +1288,39 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Matrix ; -+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ -; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; -+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ -; Total Pass ; 0 ; 15 ; 15 ; 0 ; 0 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 15 ; 15 ; 0 ; -; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 15 ; 0 ; 0 ; 15 ; 15 ; 0 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 15 ; 9 ; 15 ; 15 ; 15 ; 15 ; 9 ; 15 ; 15 ; 15 ; 15 ; 9 ; 15 ; 0 ; 0 ; 15 ; -; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; COUT[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_CIN[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Total Pass ; 0 ; 22 ; 22 ; 0 ; 0 ; 23 ; 22 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 23 ; 23 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 23 ; 1 ; 1 ; 23 ; 23 ; 0 ; 1 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 0 ; 0 ; 23 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; COUT[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_CIN[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; out_seg_1[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +------------------------------------------------------------------------------------------------+ @@ -1342,12 +1377,13 @@ Info (21077): High junction temperature is 85 degrees C Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 23 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. Info (184020): Starting Fitter periphery placement operations Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks -Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10 +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07 Critical Warning (332012): Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. @@ -1363,7 +1399,7 @@ Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources - Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11 + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped @@ -1373,12 +1409,12 @@ Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05 +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 1380 megabytes - Info: Processing ended: Tue Sep 15 10:01:04 2026 - Info: Elapsed time: 00:00:41 - Info: Total CPU time (on all processors): 00:00:52 +Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings + Info: Peak virtual memory: 1340 megabytes + Info: Processing ended: Tue Sep 15 16:39:52 2026 + Info: Elapsed time: 00:00:31 + Info: Total CPU time (on all processors): 00:00:42 diff --git a/Quartus/A1_Q3/output_files/asu.fit.summary b/Quartus/A1_Q3/output_files/asu.fit.summary index 6475df8..135308f 100644 --- a/Quartus/A1_Q3/output_files/asu.fit.summary +++ b/Quartus/A1_Q3/output_files/asu.fit.summary @@ -1,13 +1,13 @@ -Fitter Status : Successful - Tue Sep 15 10:01:03 2026 +Fitter Status : Successful - Tue Sep 15 16:39:51 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : asu Top-level Entity Name : asu Family : Cyclone V Device : 5CGXFC5C6F27C7 Timing Models : Final -Logic utilization (in ALMs) : 4 / 29,080 ( < 1 % ) +Logic utilization (in ALMs) : 8 / 29,080 ( < 1 % ) Total registers : 0 -Total pins : 15 / 364 ( 4 % ) +Total pins : 23 / 364 ( 6 % ) Total virtual pins : 0 Total block memory bits : 0 / 4,567,040 ( 0 % ) Total RAM Blocks : 0 / 446 ( 0 % ) diff --git a/Quartus/A1_Q3/output_files/asu.flow.rpt b/Quartus/A1_Q3/output_files/asu.flow.rpt index 4ff6be8..7152fb6 100644 --- a/Quartus/A1_Q3/output_files/asu.flow.rpt +++ b/Quartus/A1_Q3/output_files/asu.flow.rpt @@ -1,5 +1,5 @@ Flow report for asu -Tue Sep 15 10:01:28 2026 +Tue Sep 15 16:40:09 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,16 +41,16 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Sep 15 10:01:28 2026 ; +; Flow Status ; Successful - Tue Sep 15 16:40:09 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; ; Family ; Cyclone V ; ; Device ; 5CGXFC5C6F27C7 ; ; Timing Models ; Final ; -; Logic utilization (in ALMs) ; 4 / 29,080 ( < 1 % ) ; +; Logic utilization (in ALMs) ; 8 / 29,080 ( < 1 % ) ; ; Total registers ; 0 ; -; Total pins ; 15 / 364 ( 4 % ) ; +; Total pins ; 23 / 364 ( 6 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; ; Total DSP Blocks ; 0 / 150 ( 0 % ) ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/15/2026 10:00:07 ; +; Start date & time ; 09/15/2026 16:39:08 ; ; Main task ; Compilation ; ; Revision Name ; asu ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 253029099468756.178943040705122 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 268883478169649.178945434810068 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,12 +101,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:16 ; 1.0 ; 422 MB ; 00:00:32 ; -; Fitter ; 00:00:40 ; 1.0 ; 1380 MB ; 00:00:51 ; -; Assembler ; 00:00:08 ; 1.0 ; 521 MB ; 00:00:08 ; -; Timing Analyzer ; 00:00:08 ; 1.0 ; 785 MB ; 00:00:08 ; -; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 658 MB ; 00:00:01 ; -; Total ; 00:01:14 ; -- ; -- ; 00:01:40 ; +; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 419 MB ; 00:00:28 ; +; Fitter ; 00:00:30 ; 1.0 ; 1340 MB ; 00:00:42 ; +; Assembler ; 00:00:06 ; 1.0 ; 507 MB ; 00:00:06 ; +; Timing Analyzer ; 00:00:05 ; 1.0 ; 750 MB ; 00:00:05 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ; +; Total ; 00:00:54 ; -- ; -- ; 00:01:22 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A1_Q3/output_files/asu.map.rpt b/Quartus/A1_Q3/output_files/asu.map.rpt index 05078c7..19ed8b3 100644 --- a/Quartus/A1_Q3/output_files/asu.map.rpt +++ b/Quartus/A1_Q3/output_files/asu.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for asu -Tue Sep 15 10:00:22 2026 +Tue Sep 15 16:39:20 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -15,9 +15,10 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 7. Analysis & Synthesis Resource Utilization by Entity 8. General Register Statistics 9. Parameter Settings for User Entity Instance: Top-level Entity: |asu - 10. Post-Synthesis Netlist Statistics for Top Partition - 11. Elapsed Time Per Partition - 12. Analysis & Synthesis Messages + 10. Port Connectivity Checks: "seven_seg:dut" + 11. Post-Synthesis Netlist Statistics for Top Partition + 12. Elapsed Time Per Partition + 13. Analysis & Synthesis Messages @@ -44,14 +45,14 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:00:22 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Sep 15 16:39:20 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; ; Family ; Cyclone V ; ; Logic utilization (in ALMs) ; N/A ; ; Total registers ; 0 ; -; Total pins ; 15 ; +; Total pins ; 23 ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 ; ; Total DSP Blocks ; 0 ; @@ -167,40 +168,41 @@ on the Quartus Prime software download page. +----------------------------+-------------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------+---------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+------------------------------+---------------------------------------------------------+---------+ -; ../../modules/asu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ; -+----------------------------------+-----------------+------------------------------+---------------------------------------------------------+---------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+ +; ../../modules/asu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ; +; seven_seg.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/seven_seg.sv ; ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+ -+-----------------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------------+ -; Resource ; Usage ; -+---------------------------------------------+-------------+ -; Estimate of Logic utilization (ALMs needed) ; 3 ; -; ; ; -; Combinational ALUT usage for logic ; 6 ; -; -- 7 input functions ; 0 ; -; -- 6 input functions ; 0 ; -; -- 5 input functions ; 0 ; -; -- 4 input functions ; 1 ; -; -- <=3 input functions ; 5 ; -; ; ; -; Dedicated logic registers ; 0 ; -; ; ; -; I/O pins ; 15 ; -; ; ; -; Total DSP Blocks ; 0 ; -; ; ; -; Maximum fan-out node ; op[0]~input ; -; Maximum fan-out ; 5 ; -; Total fan-out ; 41 ; -; Average fan-out ; 1.14 ; -+---------------------------------------------+-------------+ ++-------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+---------+ +; Resource ; Usage ; ++---------------------------------------------+---------+ +; Estimate of Logic utilization (ALMs needed) ; 7 ; +; ; ; +; Combinational ALUT usage for logic ; 14 ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 0 ; +; -- 5 input functions ; 0 ; +; -- 4 input functions ; 8 ; +; -- <=3 input functions ; 6 ; +; ; ; +; Dedicated logic registers ; 0 ; +; ; ; +; I/O pins ; 23 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; Add0~13 ; +; Maximum fan-out ; 10 ; +; Total fan-out ; 86 ; +; Average fan-out ; 1.43 ; ++---------------------------------------------+---------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -208,7 +210,8 @@ on the Quartus Prime software download page. +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ -; |asu ; 6 (6) ; 0 (0) ; 0 ; 0 ; 15 ; 0 ; |asu ; asu ; work ; +; |asu ; 14 (7) ; 0 (0) ; 0 ; 0 ; 23 ; 0 ; |asu ; asu ; work ; +; |seven_seg:dut| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |asu|seven_seg:dut ; seven_seg ; work ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -238,21 +241,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "seven_seg:dut" ; ++------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; rbi_inv ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; rbi_inv[0] ; Input ; Info ; Stuck at VCC ; ++------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + +-----------------------------------------------------+ ; Post-Synthesis Netlist Statistics for Top Partition ; +-----------------------+-----------------------------+ ; Type ; Count ; +-----------------------+-----------------------------+ -; arriav_lcell_comb ; 6 ; -; normal ; 1 ; -; 4 data inputs ; 1 ; -; shared ; 5 ; +; arriav_lcell_comb ; 16 ; +; arith ; 6 ; ; 0 data inputs ; 1 ; +; 1 data inputs ; 1 ; ; 3 data inputs ; 4 ; -; boundary_port ; 15 ; +; normal ; 10 ; +; 0 data inputs ; 1 ; +; 1 data inputs ; 1 ; +; 4 data inputs ; 8 ; +; boundary_port ; 23 ; ; ; ; -; Max LUT depth ; 2.30 ; -; Average LUT depth ; 1.95 ; +; Max LUT depth ; 3.40 ; +; Average LUT depth ; 2.82 ; +-----------------------+-----------------------------+ @@ -261,7 +277,7 @@ Note: In order to hide this table in the UI and the text report file, please set +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ -; Top ; 00:00:01 ; +; Top ; 00:00:00 ; +----------------+--------------+ @@ -271,24 +287,29 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:00:06 2026 + Info: Processing started: Tue Sep 15 16:39:08 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv - Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4 +Info (12021): Found 2 design units, including 2 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv + Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/seven_seg.sv Line: 3 + Info (12023): Found entity 2: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 5 Info (12127): Elaborating entity "asu" for the top level hierarchy +Info (12128): Elaborating entity "seven_seg" for hierarchy "seven_seg:dut" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 24 +Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "out_seg_1[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 9 Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 21 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 37 device resources after synthesis - the final resource count might be different Info (21058): Implemented 9 input pins - Info (21059): Implemented 6 output pins - Info (21061): Implemented 6 logic cells -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning - Info: Peak virtual memory: 439 megabytes - Info: Processing ended: Tue Sep 15 10:00:22 2026 - Info: Elapsed time: 00:00:16 - Info: Total CPU time (on all processors): 00:00:32 + Info (21059): Implemented 14 output pins + Info (21061): Implemented 14 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 433 megabytes + Info: Processing ended: Tue Sep 15 16:39:20 2026 + Info: Elapsed time: 00:00:12 + Info: Total CPU time (on all processors): 00:00:28 diff --git a/Quartus/A1_Q3/output_files/asu.map.summary b/Quartus/A1_Q3/output_files/asu.map.summary index efc3915..9dabc96 100644 --- a/Quartus/A1_Q3/output_files/asu.map.summary +++ b/Quartus/A1_Q3/output_files/asu.map.summary @@ -1,11 +1,11 @@ -Analysis & Synthesis Status : Successful - Tue Sep 15 10:00:22 2026 +Analysis & Synthesis Status : Successful - Tue Sep 15 16:39:20 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : asu Top-level Entity Name : asu Family : Cyclone V Logic utilization (in ALMs) : N/A Total registers : 0 -Total pins : 15 +Total pins : 23 Total virtual pins : 0 Total block memory bits : 0 Total DSP Blocks : 0 diff --git a/Quartus/A1_Q3/output_files/asu.pin b/Quartus/A1_Q3/output_files/asu.pin index dda18b5..3993a46 100644 --- a/Quartus/A1_Q3/output_files/asu.pin +++ b/Quartus/A1_Q3/output_files/asu.pin @@ -91,7 +91,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7A : GND : A15 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7A : -RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A : +out_seg_1[0] : A17 : output : 2.5 V : : 7A : N RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A : VCCIO7A : A20 : power : : 2.5V : 7A : @@ -686,9 +686,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A : GND : V16 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A : +out_seg_1[3] : V17 : output : 1.2 V : : 4A : Y +out_seg_1[2] : V18 : output : 1.2 V : : 4A : Y +out_seg_1[1] : V19 : output : 1.2 V : : 4A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A : VCCIO5A : V21 : power : : 2.5V : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A : @@ -713,7 +713,7 @@ VCCIO4A : W14 : power : : 1.2V RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A : +out_seg_1[4] : W18 : output : 1.2 V : : 4A : Y GND : W19 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A : @@ -739,9 +739,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A : VCCIO4A : Y17 : power : : 1.2V : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A : +out_seg_1[7] : Y18 : output : 1.2 V : : 4A : Y +out_seg_1[6] : Y19 : output : 1.2 V : : 4A : Y +out_seg_1[5] : Y20 : output : 1.2 V : : 4A : Y VCCA_FPLL : Y21 : power : : 2.5V : : GND : Y22 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A : diff --git a/Quartus/A1_Q3/output_files/asu.sof b/Quartus/A1_Q3/output_files/asu.sof index 8371371..42cc3b0 100644 Binary files a/Quartus/A1_Q3/output_files/asu.sof and b/Quartus/A1_Q3/output_files/asu.sof differ diff --git a/Quartus/A1_Q3/output_files/asu.sta.rpt b/Quartus/A1_Q3/output_files/asu.sta.rpt index f048c6e..98c7897 100644 --- a/Quartus/A1_Q3/output_files/asu.sta.rpt +++ b/Quartus/A1_Q3/output_files/asu.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for asu -Tue Sep 15 10:01:24 2026 +Tue Sep 15 16:40:07 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -98,12 +98,12 @@ on the Quartus Prime software download page. ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.04 ; +; Average used ; 1.03 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 3.8% ; +; Processor 2 ; 3.3% ; +----------------------------+-------------+ @@ -285,18 +285,26 @@ No synchronizer chains to report. +------------------+-------+------+----------+---------+---------------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Board Trace Model Assignments ; -+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; -+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; COUT[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; OUT_CIN[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; COUT[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_CIN[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[1] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[2] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[3] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[4] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[5] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[6] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; out_seg_1[7] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +----------------------------------------------------------+ @@ -305,71 +313,103 @@ No synchronizer chains to report. ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +-------+--------------+-----------------+-----------------+ ; op[0] ; 1.2 V ; 960 ps ; 960 ps ; -; A[3] ; 1.2 V ; 960 ps ; 960 ps ; ; B[3] ; 1.2 V ; 960 ps ; 960 ps ; +; A[3] ; 1.2 V ; 960 ps ; 960 ps ; ; B[0] ; 1.2 V ; 960 ps ; 960 ps ; ; A[0] ; 1.2 V ; 960 ps ; 960 ps ; -; A[1] ; 1.2 V ; 960 ps ; 960 ps ; ; B[1] ; 1.2 V ; 960 ps ; 960 ps ; -; A[2] ; 1.2 V ; 960 ps ; 960 ps ; +; A[1] ; 1.2 V ; 960 ps ; 960 ps ; ; B[2] ; 1.2 V ; 960 ps ; 960 ps ; +; A[2] ; 1.2 V ; 960 ps ; 960 ps ; +-------+--------------+-----------------+-----------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1100mv 0c Model) ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; -; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; +; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; +; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; +; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; +; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1100mv 85c Model) ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; -; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; +; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; +; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; +; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; +; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; +; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; +; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; +; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Fast 1100mv 0c Model) ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; -; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; +; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Fast 1100mv 85c Model) ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; -; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; -; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; -+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; +; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; +; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; +; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; +; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; ++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ------------------- @@ -398,9 +438,9 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 9 ; 9 ; -; Unconstrained Input Port Paths ; 41 ; 41 ; -; Unconstrained Output Ports ; 6 ; 6 ; -; Unconstrained Output Port Paths ; 41 ; 41 ; +; Unconstrained Input Port Paths ; 105 ; 105 ; +; Unconstrained Output Ports ; 13 ; 13 ; +; Unconstrained Output Port Paths ; 105 ; 105 ; +---------------------------------+-------+------+ @@ -421,18 +461,25 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi +------------+--------------------------------------------------------------------------------------+ -+-----------------------------------------------------------------------------------------------------+ -; Unconstrained Output Ports ; -+-------------+---------------------------------------------------------------------------------------+ -; Output Port ; Comment ; -+-------------+---------------------------------------------------------------------------------------+ -; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -+-------------+---------------------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++--------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++--------------+---------------------------------------------------------------------------------------+ +; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++--------------+---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------+ @@ -452,18 +499,25 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi +------------+--------------------------------------------------------------------------------------+ -+-----------------------------------------------------------------------------------------------------+ -; Unconstrained Output Ports ; -+-------------+---------------------------------------------------------------------------------------+ -; Output Port ; Comment ; -+-------------+---------------------------------------------------------------------------------------+ -; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -+-------------+---------------------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++--------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++--------------+---------------------------------------------------------------------------------------+ +; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; out_seg_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++--------------+---------------------------------------------------------------------------------------+ +--------------------------+ @@ -472,7 +526,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:01:16 2026 + Info: Processing started: Tue Sep 15 16:40:01 2026 Info: Command: quartus_sta A1_Q3 -c asu Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -532,9 +586,9 @@ Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 785 megabytes - Info: Processing ended: Tue Sep 15 10:01:24 2026 - Info: Elapsed time: 00:00:08 - Info: Total CPU time (on all processors): 00:00:08 + Info: Peak virtual memory: 750 megabytes + Info: Processing ended: Tue Sep 15 16:40:07 2026 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q3/seven_seg.sv b/Quartus/A1_Q3/seven_seg.sv new file mode 100644 index 0000000..675f354 --- /dev/null +++ b/Quartus/A1_Q3/seven_seg.sv @@ -0,0 +1,26 @@ +`ifndef SEVEN_SEG_H_SV +`define SEVEN_SEG_H_SV +module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments); + always_comb begin + case (num) + 4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000); + 4'b0001: segments = ~(8'b00001101); + 4'b0010: segments = ~(8'b10110111); + 4'b0011: segments = ~(8'b10011111); + 4'b0100: segments = ~(8'b11001101); + 4'b0101: segments = ~(8'b11011011); + 4'b0110: segments = ~(8'b11111011); + 4'b0111: segments = ~(8'b00001111); + 4'b1000: segments = ~(8'b11111111); + 4'b1001: segments = ~(8'b11001111); + 4'b1010: segments = ~(8'b11101111); + 4'b1011: segments = ~(8'b11111001); + 4'b1100: segments = ~(8'b01110011); + 4'b1101: segments = ~(8'b10111101); + 4'b1110: segments = ~(8'b11110011); + 4'b1111: segments = ~(8'b11100011); + default: segments = ~(8'bxxxxxxxx); + endcase + end +endmodule +`endif \ No newline at end of file diff --git a/Quartus/A1_Q3/simulation/questa/asu.svo b/Quartus/A1_Q3/simulation/questa/asu.svo index 66cd20e..c34a2b7 100644 --- a/Quartus/A1_Q3/simulation/questa/asu.svo +++ b/Quartus/A1_Q3/simulation/questa/asu.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "09/15/2026 10:01:28" +// DATE "09/15/2026 16:40:09" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 @@ -35,13 +35,15 @@ module asu ( B, OUT_1, COUT, - OUT_CIN); -input logic [0:0] op ; -input logic [3:0] A ; -input logic [3:0] B ; -output logic [3:0] OUT_1 ; -output logic [0:0] COUT ; -output logic [0:0] OUT_CIN ; + OUT_CIN, + out_seg_1); +input [0:0] op; +input [3:0] A; +input [3:0] B; +output [3:0] OUT_1; +output [0:0] COUT; +output [0:0] OUT_CIN; +output [7:0] out_seg_1; // Design Ports Information // OUT_1[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default @@ -50,15 +52,23 @@ output logic [0:0] OUT_CIN ; // OUT_1[3] => Location: PIN_G7, I/O Standard: 2.5 V, Current Strength: Default // COUT[0] => Location: PIN_J8, I/O Standard: 2.5 V, Current Strength: Default // OUT_CIN[0] => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_1[0] => Location: PIN_A17, I/O Standard: 2.5 V, Current Strength: Default +// out_seg_1[1] => Location: PIN_V19, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[2] => Location: PIN_V18, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[3] => Location: PIN_V17, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[4] => Location: PIN_W18, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[5] => Location: PIN_Y20, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[6] => Location: PIN_Y19, I/O Standard: 1.2 V, Current Strength: Default +// out_seg_1[7] => Location: PIN_Y18, I/O Standard: 1.2 V, Current Strength: Default // op[0] => Location: PIN_AE19, I/O Standard: 1.2 V, Current Strength: Default -// A[3] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default // B[3] => Location: PIN_AC10, I/O Standard: 1.2 V, Current Strength: Default +// A[3] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default // B[0] => Location: PIN_W11, I/O Standard: 1.2 V, Current Strength: Default // A[0] => Location: PIN_AC9, I/O Standard: 1.2 V, Current Strength: Default -// A[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default // B[1] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default -// A[2] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default +// A[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default // B[2] => Location: PIN_V10, I/O Standard: 1.2 V, Current Strength: Default +// A[2] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default wire gnd; @@ -76,31 +86,35 @@ wire \~QUARTUS_CREATED_GND~I_combout ; wire \op[0]~input_o ; wire \A[0]~input_o ; wire \B[0]~input_o ; -wire \_~1_sumout ; +wire \Add0~22_cout ; +wire \Add0~1_sumout ; wire \A[1]~input_o ; wire \B[1]~input_o ; -wire \_~2 ; -wire \_~3 ; -wire \_~5_sumout ; +wire \Add0~2 ; +wire \Add0~5_sumout ; wire \A[2]~input_o ; wire \B[2]~input_o ; -wire \_~6 ; -wire \_~7 ; -wire \_~9_sumout ; -wire \A[3]~input_o ; +wire \Add0~6 ; +wire \Add0~9_sumout ; wire \B[3]~input_o ; -wire \_~10 ; -wire \_~11 ; -wire \_~13_sumout ; -wire \_~14 ; -wire \_~15 ; -wire \_~17_sumout ; +wire \A[3]~input_o ; +wire \Add0~10 ; +wire \Add0~13_sumout ; +wire \Add0~14 ; +wire \Add0~17_sumout ; wire \OUT_CIN~0_combout ; +wire \dut|Mux5~0_combout ; +wire \dut|Mux4~0_combout ; +wire \dut|Mux3~0_combout ; +wire \dut|Mux2~0_combout ; +wire \dut|Mux1~0_combout ; +wire \dut|Mux0~0_combout ; +wire \dut|WideOr0~0_combout ; // Location: IOOBUF_X14_Y61_N53 cyclonev_io_obuf \OUT_1[0]~output ( - .i(\_~1_sumout ), + .i(\Add0~1_sumout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -116,7 +130,7 @@ defparam \OUT_1[0]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X15_Y61_N36 cyclonev_io_obuf \OUT_1[1]~output ( - .i(\_~5_sumout ), + .i(\Add0~5_sumout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -132,7 +146,7 @@ defparam \OUT_1[1]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X15_Y61_N53 cyclonev_io_obuf \OUT_1[2]~output ( - .i(\_~9_sumout ), + .i(\Add0~9_sumout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -148,7 +162,7 @@ defparam \OUT_1[2]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X14_Y61_N36 cyclonev_io_obuf \OUT_1[3]~output ( - .i(\_~13_sumout ), + .i(\Add0~13_sumout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -164,7 +178,7 @@ defparam \OUT_1[3]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X14_Y61_N19 cyclonev_io_obuf \COUT[0]~output ( - .i(\_~17_sumout ), + .i(\Add0~17_sumout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -194,6 +208,134 @@ defparam \OUT_CIN[0]~output .open_drain_output = "false"; defparam \OUT_CIN[0]~output .shift_series_termination_control = "false"; // synopsys translate_on +// Location: IOOBUF_X55_Y61_N76 +cyclonev_io_obuf \out_seg_1[0]~output ( + .i(gnd), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[0]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[0]~output .bus_hold = "false"; +defparam \out_seg_1[0]~output .open_drain_output = "false"; +defparam \out_seg_1[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X66_Y0_N2 +cyclonev_io_obuf \out_seg_1[1]~output ( + .i(\dut|Mux5~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[1]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[1]~output .bus_hold = "false"; +defparam \out_seg_1[1]~output .open_drain_output = "false"; +defparam \out_seg_1[1]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X64_Y0_N2 +cyclonev_io_obuf \out_seg_1[2]~output ( + .i(\dut|Mux4~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[2]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[2]~output .bus_hold = "false"; +defparam \out_seg_1[2]~output .open_drain_output = "false"; +defparam \out_seg_1[2]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X64_Y0_N19 +cyclonev_io_obuf \out_seg_1[3]~output ( + .i(\dut|Mux3~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[3]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[3]~output .bus_hold = "false"; +defparam \out_seg_1[3]~output .open_drain_output = "false"; +defparam \out_seg_1[3]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X66_Y0_N19 +cyclonev_io_obuf \out_seg_1[4]~output ( + .i(\dut|Mux2~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[4]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[4]~output .bus_hold = "false"; +defparam \out_seg_1[4]~output .open_drain_output = "false"; +defparam \out_seg_1[4]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X65_Y0_N2 +cyclonev_io_obuf \out_seg_1[5]~output ( + .i(\dut|Mux1~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[5]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[5]~output .bus_hold = "false"; +defparam \out_seg_1[5]~output .open_drain_output = "false"; +defparam \out_seg_1[5]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X65_Y0_N19 +cyclonev_io_obuf \out_seg_1[6]~output ( + .i(\dut|Mux0~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[6]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[6]~output .bus_hold = "false"; +defparam \out_seg_1[6]~output .open_drain_output = "false"; +defparam \out_seg_1[6]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X62_Y0_N42 +cyclonev_io_obuf \out_seg_1[7]~output ( + .i(!\dut|WideOr0~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(out_seg_1[7]), + .obar()); +// synopsys translate_off +defparam \out_seg_1[7]~output .bus_hold = "false"; +defparam \out_seg_1[7]~output .open_drain_output = "false"; +defparam \out_seg_1[7]~output .shift_series_termination_control = "false"; +// synopsys translate_on + // Location: IOIBUF_X50_Y0_N35 cyclonev_io_ibuf \op[0]~input ( .i(op[0]), @@ -227,30 +369,53 @@ defparam \B[0]~input .bus_hold = "false"; defparam \B[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X18_Y4_N30 -cyclonev_lcell_comb \_~1 ( +// Location: LABCELL_X27_Y1_N30 +cyclonev_lcell_comb \Add0~22 ( // Equation(s): -// \_~1_sumout = SUM(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC )) -// \_~2 = CARRY(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC )) -// \_~3 = SHARE((!\B[0]~input_o & (\op[0]~input_o )) # (\B[0]~input_o & ((\A[0]~input_o )))) +// \Add0~22_cout = CARRY(( \op[0]~input_o ) + ( VCC ) + ( !VCC )) .dataa(gnd), .datab(!\op[0]~input_o ), - .datac(!\A[0]~input_o ), - .datad(!\B[0]~input_o ), + .datac(gnd), + .datad(gnd), .datae(gnd), .dataf(gnd), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(), - .sumout(\_~1_sumout ), - .cout(\_~2 ), - .shareout(\_~3 )); + .sumout(), + .cout(\Add0~22_cout ), + .shareout()); // synopsys translate_off -defparam \_~1 .extended_lut = "off"; -defparam \_~1 .lut_mask = 64'h0000330F00000FF0; -defparam \_~1 .shared_arith = "on"; +defparam \Add0~22 .extended_lut = "off"; +defparam \Add0~22 .lut_mask = 64'h0000000000003333; +defparam \Add0~22 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X27_Y1_N33 +cyclonev_lcell_comb \Add0~1 ( +// Equation(s): +// \Add0~1_sumout = SUM(( \A[0]~input_o ) + ( !\op[0]~input_o $ (!\B[0]~input_o ) ) + ( \Add0~22_cout )) +// \Add0~2 = CARRY(( \A[0]~input_o ) + ( !\op[0]~input_o $ (!\B[0]~input_o ) ) + ( \Add0~22_cout )) + + .dataa(gnd), + .datab(!\op[0]~input_o ), + .datac(gnd), + .datad(!\A[0]~input_o ), + .datae(gnd), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(\Add0~22_cout ), + .sharein(gnd), + .combout(), + .sumout(\Add0~1_sumout ), + .cout(\Add0~2 ), + .shareout()); +// synopsys translate_off +defparam \Add0~1 .extended_lut = "off"; +defparam \Add0~1 .lut_mask = 64'h0000CC33000000FF; +defparam \Add0~1 .shared_arith = "off"; // synopsys translate_on // Location: IOIBUF_X36_Y0_N52 @@ -275,30 +440,29 @@ defparam \B[1]~input .bus_hold = "false"; defparam \B[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X18_Y4_N33 -cyclonev_lcell_comb \_~5 ( +// Location: LABCELL_X27_Y1_N36 +cyclonev_lcell_comb \Add0~5 ( // Equation(s): -// \_~5_sumout = SUM(( !\A[1]~input_o $ (!\op[0]~input_o $ (\B[1]~input_o )) ) + ( \_~3 ) + ( \_~2 )) -// \_~6 = CARRY(( !\A[1]~input_o $ (!\op[0]~input_o $ (\B[1]~input_o )) ) + ( \_~3 ) + ( \_~2 )) -// \_~7 = SHARE((\A[1]~input_o & (!\op[0]~input_o $ (!\B[1]~input_o )))) +// \Add0~5_sumout = SUM(( !\op[0]~input_o $ (!\B[1]~input_o ) ) + ( \A[1]~input_o ) + ( \Add0~2 )) +// \Add0~6 = CARRY(( !\op[0]~input_o $ (!\B[1]~input_o ) ) + ( \A[1]~input_o ) + ( \Add0~2 )) - .dataa(!\A[1]~input_o ), + .dataa(gnd), .datab(!\op[0]~input_o ), - .datac(!\B[1]~input_o ), - .datad(gnd), + .datac(!\A[1]~input_o ), + .datad(!\B[1]~input_o ), .datae(gnd), .dataf(gnd), .datag(gnd), - .cin(\_~2 ), - .sharein(\_~3 ), + .cin(\Add0~2 ), + .sharein(gnd), .combout(), - .sumout(\_~5_sumout ), - .cout(\_~6 ), - .shareout(\_~7 )); + .sumout(\Add0~5_sumout ), + .cout(\Add0~6 ), + .shareout()); // synopsys translate_off -defparam \_~5 .extended_lut = "off"; -defparam \_~5 .lut_mask = 64'h0000141400006969; -defparam \_~5 .shared_arith = "on"; +defparam \Add0~5 .extended_lut = "off"; +defparam \Add0~5 .lut_mask = 64'h0000F0F0000033CC; +defparam \Add0~5 .shared_arith = "off"; // synopsys translate_on // Location: IOIBUF_X34_Y0_N35 @@ -323,41 +487,29 @@ defparam \B[2]~input .bus_hold = "false"; defparam \B[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X18_Y4_N36 -cyclonev_lcell_comb \_~9 ( +// Location: LABCELL_X27_Y1_N39 +cyclonev_lcell_comb \Add0~9 ( // Equation(s): -// \_~9_sumout = SUM(( !\op[0]~input_o $ (!\A[2]~input_o $ (\B[2]~input_o )) ) + ( \_~7 ) + ( \_~6 )) -// \_~10 = CARRY(( !\op[0]~input_o $ (!\A[2]~input_o $ (\B[2]~input_o )) ) + ( \_~7 ) + ( \_~6 )) -// \_~11 = SHARE((\A[2]~input_o & (!\op[0]~input_o $ (!\B[2]~input_o )))) +// \Add0~9_sumout = SUM(( \A[2]~input_o ) + ( !\op[0]~input_o $ (!\B[2]~input_o ) ) + ( \Add0~6 )) +// \Add0~10 = CARRY(( \A[2]~input_o ) + ( !\op[0]~input_o $ (!\B[2]~input_o ) ) + ( \Add0~6 )) - .dataa(gnd), + .dataa(!\A[2]~input_o ), .datab(!\op[0]~input_o ), - .datac(!\A[2]~input_o ), - .datad(!\B[2]~input_o ), + .datac(gnd), + .datad(gnd), .datae(gnd), - .dataf(gnd), + .dataf(!\B[2]~input_o ), .datag(gnd), - .cin(\_~6 ), - .sharein(\_~7 ), + .cin(\Add0~6 ), + .sharein(gnd), .combout(), - .sumout(\_~9_sumout ), - .cout(\_~10 ), - .shareout(\_~11 )); + .sumout(\Add0~9_sumout ), + .cout(\Add0~10 ), + .shareout()); // synopsys translate_off -defparam \_~9 .extended_lut = "off"; -defparam \_~9 .lut_mask = 64'h0000030C00003CC3; -defparam \_~9 .shared_arith = "on"; -// synopsys translate_on - -// Location: IOIBUF_X14_Y0_N52 -cyclonev_io_ibuf \A[3]~input ( - .i(A[3]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[3]~input_o )); -// synopsys translate_off -defparam \A[3]~input .bus_hold = "false"; -defparam \A[3]~input .simulate_z_as = "z"; +defparam \Add0~9 .extended_lut = "off"; +defparam \Add0~9 .lut_mask = 64'h0000CC3300005555; +defparam \Add0~9 .shared_arith = "off"; // synopsys translate_on // Location: IOIBUF_X12_Y0_N52 @@ -371,36 +523,46 @@ defparam \B[3]~input .bus_hold = "false"; defparam \B[3]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X18_Y4_N39 -cyclonev_lcell_comb \_~13 ( +// Location: IOIBUF_X14_Y0_N52 +cyclonev_io_ibuf \A[3]~input ( + .i(A[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[3]~input_o )); +// synopsys translate_off +defparam \A[3]~input .bus_hold = "false"; +defparam \A[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X27_Y1_N42 +cyclonev_lcell_comb \Add0~13 ( // Equation(s): -// \_~13_sumout = SUM(( !\op[0]~input_o $ (!\A[3]~input_o $ (\B[3]~input_o )) ) + ( \_~11 ) + ( \_~10 )) -// \_~14 = CARRY(( !\op[0]~input_o $ (!\A[3]~input_o $ (\B[3]~input_o )) ) + ( \_~11 ) + ( \_~10 )) -// \_~15 = SHARE((\A[3]~input_o & (!\op[0]~input_o $ (!\B[3]~input_o )))) +// \Add0~13_sumout = SUM(( !\op[0]~input_o $ (!\B[3]~input_o ) ) + ( \A[3]~input_o ) + ( \Add0~10 )) +// \Add0~14 = CARRY(( !\op[0]~input_o $ (!\B[3]~input_o ) ) + ( \A[3]~input_o ) + ( \Add0~10 )) .dataa(gnd), .datab(!\op[0]~input_o ), - .datac(!\A[3]~input_o ), - .datad(!\B[3]~input_o ), + .datac(!\B[3]~input_o ), + .datad(gnd), .datae(gnd), - .dataf(gnd), + .dataf(!\A[3]~input_o ), .datag(gnd), - .cin(\_~10 ), - .sharein(\_~11 ), + .cin(\Add0~10 ), + .sharein(gnd), .combout(), - .sumout(\_~13_sumout ), - .cout(\_~14 ), - .shareout(\_~15 )); + .sumout(\Add0~13_sumout ), + .cout(\Add0~14 ), + .shareout()); // synopsys translate_off -defparam \_~13 .extended_lut = "off"; -defparam \_~13 .lut_mask = 64'h0000030C00003CC3; -defparam \_~13 .shared_arith = "on"; +defparam \Add0~13 .extended_lut = "off"; +defparam \Add0~13 .lut_mask = 64'h0000FF0000003C3C; +defparam \Add0~13 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X18_Y4_N42 -cyclonev_lcell_comb \_~17 ( +// Location: LABCELL_X27_Y1_N45 +cyclonev_lcell_comb \Add0~17 ( // Equation(s): -// \_~17_sumout = SUM(( GND ) + ( \_~15 ) + ( \_~14 )) +// \Add0~17_sumout = SUM(( GND ) + ( GND ) + ( \Add0~14 )) .dataa(gnd), .datab(gnd), @@ -409,30 +571,29 @@ cyclonev_lcell_comb \_~17 ( .datae(gnd), .dataf(gnd), .datag(gnd), - .cin(\_~14 ), - .sharein(\_~15 ), + .cin(\Add0~14 ), + .sharein(gnd), .combout(), - .sumout(\_~17_sumout ), + .sumout(\Add0~17_sumout ), .cout(), .shareout()); // synopsys translate_off -defparam \_~17 .extended_lut = "off"; -defparam \_~17 .lut_mask = 64'h0000000000000000; -defparam \_~17 .shared_arith = "on"; +defparam \Add0~17 .extended_lut = "off"; +defparam \Add0~17 .lut_mask = 64'h0000FFFF00000000; +defparam \Add0~17 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X18_Y4_N0 +// Location: LABCELL_X27_Y1_N0 cyclonev_lcell_comb \OUT_CIN~0 ( // Equation(s): -// \OUT_CIN~0_combout = ( \B[3]~input_o & ( \op[0]~input_o & ( !\_~13_sumout $ (!\A[3]~input_o ) ) ) ) # ( !\B[3]~input_o & ( \op[0]~input_o & ( !\_~13_sumout $ (\A[3]~input_o ) ) ) ) # ( \B[3]~input_o & ( !\op[0]~input_o & ( !\_~13_sumout $ -// (\A[3]~input_o ) ) ) ) # ( !\B[3]~input_o & ( !\op[0]~input_o & ( !\_~13_sumout $ (!\A[3]~input_o ) ) ) ) +// \OUT_CIN~0_combout = ( \op[0]~input_o & ( !\A[3]~input_o $ (!\B[3]~input_o $ (!\Add0~13_sumout )) ) ) # ( !\op[0]~input_o & ( !\A[3]~input_o $ (!\B[3]~input_o $ (\Add0~13_sumout )) ) ) .dataa(gnd), - .datab(!\_~13_sumout ), - .datac(gnd), - .datad(!\A[3]~input_o ), - .datae(!\B[3]~input_o ), - .dataf(!\op[0]~input_o ), + .datab(!\A[3]~input_o ), + .datac(!\B[3]~input_o ), + .datad(!\Add0~13_sumout ), + .datae(!\op[0]~input_o ), + .dataf(gnd), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -442,11 +603,184 @@ cyclonev_lcell_comb \OUT_CIN~0 ( .shareout()); // synopsys translate_off defparam \OUT_CIN~0 .extended_lut = "off"; -defparam \OUT_CIN~0 .lut_mask = 64'h33CCCC33CC3333CC; +defparam \OUT_CIN~0 .lut_mask = 64'h3CC3C33C3CC3C33C; defparam \OUT_CIN~0 .shared_arith = "off"; // synopsys translate_on -// Location: MLABCELL_X42_Y27_N0 +// Location: LABCELL_X27_Y1_N9 +cyclonev_lcell_comb \dut|Mux5~0 ( +// Equation(s): +// \dut|Mux5~0_combout = ( !\Add0~5_sumout & ( \Add0~9_sumout & ( !\Add0~1_sumout $ (\Add0~13_sumout ) ) ) ) # ( \Add0~5_sumout & ( !\Add0~9_sumout & ( (\Add0~1_sumout & \Add0~13_sumout ) ) ) ) # ( !\Add0~5_sumout & ( !\Add0~9_sumout & ( +// (\Add0~1_sumout & !\Add0~13_sumout ) ) ) ) + + .dataa(!\Add0~1_sumout ), + .datab(gnd), + .datac(!\Add0~13_sumout ), + .datad(gnd), + .datae(!\Add0~5_sumout ), + .dataf(!\Add0~9_sumout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\dut|Mux5~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \dut|Mux5~0 .extended_lut = "off"; +defparam \dut|Mux5~0 .lut_mask = 64'h50500505A5A50000; +defparam \dut|Mux5~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X27_Y1_N12 +cyclonev_lcell_comb \dut|Mux4~0 ( +// Equation(s): +// \dut|Mux4~0_combout = ( \Add0~5_sumout & ( \Add0~9_sumout & ( (!\Add0~1_sumout ) # (\Add0~13_sumout ) ) ) ) # ( !\Add0~5_sumout & ( \Add0~9_sumout & ( !\Add0~13_sumout $ (!\Add0~1_sumout ) ) ) ) # ( \Add0~5_sumout & ( !\Add0~9_sumout & ( +// (\Add0~13_sumout & \Add0~1_sumout ) ) ) ) + + .dataa(gnd), + .datab(!\Add0~13_sumout ), + .datac(!\Add0~1_sumout ), + .datad(gnd), + .datae(!\Add0~5_sumout ), + .dataf(!\Add0~9_sumout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\dut|Mux4~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \dut|Mux4~0 .extended_lut = "off"; +defparam \dut|Mux4~0 .lut_mask = 64'h000003033C3CF3F3; +defparam \dut|Mux4~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X27_Y1_N51 +cyclonev_lcell_comb \dut|Mux3~0 ( +// Equation(s): +// \dut|Mux3~0_combout = ( \Add0~5_sumout & ( \Add0~9_sumout & ( \Add0~13_sumout ) ) ) # ( !\Add0~5_sumout & ( \Add0~9_sumout & ( (!\Add0~1_sumout & \Add0~13_sumout ) ) ) ) # ( \Add0~5_sumout & ( !\Add0~9_sumout & ( (!\Add0~1_sumout & +// !\Add0~13_sumout ) ) ) ) + + .dataa(!\Add0~1_sumout ), + .datab(gnd), + .datac(!\Add0~13_sumout ), + .datad(gnd), + .datae(!\Add0~5_sumout ), + .dataf(!\Add0~9_sumout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\dut|Mux3~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \dut|Mux3~0 .extended_lut = "off"; +defparam \dut|Mux3~0 .lut_mask = 64'h0000A0A00A0A0F0F; +defparam \dut|Mux3~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X27_Y1_N24 +cyclonev_lcell_comb \dut|Mux2~0 ( +// Equation(s): +// \dut|Mux2~0_combout = ( \Add0~5_sumout & ( \Add0~9_sumout & ( \Add0~1_sumout ) ) ) # ( !\Add0~5_sumout & ( \Add0~9_sumout & ( (!\Add0~13_sumout & !\Add0~1_sumout ) ) ) ) # ( \Add0~5_sumout & ( !\Add0~9_sumout & ( (\Add0~13_sumout & +// !\Add0~1_sumout ) ) ) ) # ( !\Add0~5_sumout & ( !\Add0~9_sumout & ( \Add0~1_sumout ) ) ) + + .dataa(gnd), + .datab(!\Add0~13_sumout ), + .datac(!\Add0~1_sumout ), + .datad(gnd), + .datae(!\Add0~5_sumout ), + .dataf(!\Add0~9_sumout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\dut|Mux2~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \dut|Mux2~0 .extended_lut = "off"; +defparam \dut|Mux2~0 .lut_mask = 64'h0F0F3030C0C00F0F; +defparam \dut|Mux2~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X27_Y1_N21 +cyclonev_lcell_comb \dut|Mux1~0 ( +// Equation(s): +// \dut|Mux1~0_combout = ( \Add0~5_sumout & ( \Add0~9_sumout & ( (\Add0~1_sumout & !\Add0~13_sumout ) ) ) ) # ( !\Add0~5_sumout & ( \Add0~9_sumout & ( !\Add0~13_sumout ) ) ) # ( \Add0~5_sumout & ( !\Add0~9_sumout & ( (\Add0~1_sumout & +// !\Add0~13_sumout ) ) ) ) # ( !\Add0~5_sumout & ( !\Add0~9_sumout & ( \Add0~1_sumout ) ) ) + + .dataa(!\Add0~1_sumout ), + .datab(gnd), + .datac(!\Add0~13_sumout ), + .datad(gnd), + .datae(!\Add0~5_sumout ), + .dataf(!\Add0~9_sumout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\dut|Mux1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \dut|Mux1~0 .extended_lut = "off"; +defparam \dut|Mux1~0 .lut_mask = 64'h55555050F0F05050; +defparam \dut|Mux1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X27_Y1_N54 +cyclonev_lcell_comb \dut|Mux0~0 ( +// Equation(s): +// \dut|Mux0~0_combout = ( \Add0~9_sumout & ( (\Add0~1_sumout & (!\Add0~13_sumout $ (!\Add0~5_sumout ))) ) ) # ( !\Add0~9_sumout & ( (!\Add0~13_sumout & ((\Add0~5_sumout ) # (\Add0~1_sumout ))) ) ) + + .dataa(!\Add0~1_sumout ), + .datab(!\Add0~13_sumout ), + .datac(!\Add0~5_sumout ), + .datad(gnd), + .datae(gnd), + .dataf(!\Add0~9_sumout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\dut|Mux0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \dut|Mux0~0 .extended_lut = "off"; +defparam \dut|Mux0~0 .lut_mask = 64'h4C4C4C4C14141414; +defparam \dut|Mux0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X27_Y1_N57 +cyclonev_lcell_comb \dut|WideOr0~0 ( +// Equation(s): +// \dut|WideOr0~0_combout = ( \Add0~9_sumout & ( (!\Add0~1_sumout & ((!\Add0~13_sumout ) # (\Add0~5_sumout ))) # (\Add0~1_sumout & ((!\Add0~5_sumout ) # (\Add0~13_sumout ))) ) ) # ( !\Add0~9_sumout & ( (\Add0~5_sumout ) # (\Add0~13_sumout ) ) ) + + .dataa(!\Add0~1_sumout ), + .datab(!\Add0~13_sumout ), + .datac(gnd), + .datad(!\Add0~5_sumout ), + .datae(gnd), + .dataf(!\Add0~9_sumout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\dut|WideOr0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \dut|WideOr0~0 .extended_lut = "off"; +defparam \dut|WideOr0~0 .lut_mask = 64'h33FF33FFDDBBDDBB; +defparam \dut|WideOr0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X51_Y49_N0 cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( // Equation(s): diff --git a/modules/asu.sv b/modules/asu.sv index 5b0440e..7548273 100644 --- a/modules/asu.sv +++ b/modules/asu.sv @@ -1,11 +1,13 @@ `ifndef ASU_H_SV `define ASU_H_SV +`include "seven_seg.sv" module asu #(parameter width = 2)( input logic [0:0] op, input logic[2**width-1:0] A, input logic[2**width-1:0] B, - output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN); - + output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN, + output logic[7:0] out_seg_1); + logic [2**width-1:0] operand; always_comb begin // A + (sub) ? B : -B @@ -18,5 +20,7 @@ module asu #(parameter width = 2)( // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported? // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1]; + + seven_seg dut(OUT_1, 1, out_seg_1); endmodule `endif \ No newline at end of file