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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
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Quartus/A1_Q3/seven_seg.sv
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`ifndef SEVEN_SEG_H_SV
`define SEVEN_SEG_H_SV
module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
always_comb begin
case (num)
4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
4'b0001: segments = ~(8'b00001101);
4'b0010: segments = ~(8'b10110111);
4'b0011: segments = ~(8'b10011111);
4'b0100: segments = ~(8'b11001101);
4'b0101: segments = ~(8'b11011011);
4'b0110: segments = ~(8'b11111011);
4'b0111: segments = ~(8'b00001111);
4'b1000: segments = ~(8'b11111111);
4'b1001: segments = ~(8'b11001111);
4'b1010: segments = ~(8'b11101111);
4'b1011: segments = ~(8'b11111001);
4'b1100: segments = ~(8'b01110011);
4'b1101: segments = ~(8'b10111101);
4'b1110: segments = ~(8'b11110011);
4'b1111: segments = ~(8'b11100011);
default: segments = ~(8'bxxxxxxxx);
endcase
end
endmodule
`endif