TroubleElectrical/FPGA_Uni
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
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commit 9e5fb6f52b
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Quartus/A1_Q3/output_files/asu.map.summary
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Analysis & Synthesis Status : Successful - Tue Sep 15 10:00:22 2026
Analysis & Synthesis Status : Successful - Tue Sep 15 16:39:20 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : asu
Top-level Entity Name : asu
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 15
Total pins : 23
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0