TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

Browse Source
This commit is contained in:
TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Quartus/A1_Q3/output_files/asu.flow.rpt
+12 -12
View File
@@ -1,5 +1,5 @@
Flow report for asu
Tue Sep 15 10:01:28 2026
Tue Sep 15 16:40:09 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,16 +41,16 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Sep 15 10:01:28 2026 ;
; Flow Status ; Successful - Tue Sep 15 16:40:09 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 4 / 29,080 ( < 1 % ) ;
; Logic utilization (in ALMs) ; 8 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 15 / 364 ( 4 % ) ;
; Total pins ; 23 / 364 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/15/2026 10:00:07 ;
; Start date & time ; 09/15/2026 16:39:08 ;
; Main task ; Compilation ;
; Revision Name ; asu ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 253029099468756.178943040705122 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 268883478169649.178945434810068 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:16 ; 1.0 ; 422 MB ; 00:00:32 ;
; Fitter ; 00:00:40 ; 1.0 ; 1380 MB ; 00:00:51 ;
; Assembler ; 00:00:08 ; 1.0 ; 521 MB ; 00:00:08 ;
; Timing Analyzer ; 00:00:08 ; 1.0 ; 785 MB ; 00:00:08 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:01:14 ; -- ; -- ; 00:01:40 ;
; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 419 MB ; 00:00:28 ;
; Fitter ; 00:00:30 ; 1.0 ; 1340 MB ; 00:00:42 ;
; Assembler ; 00:00:06 ; 1.0 ; 507 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 750 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ;
; Total ; 00:00:54 ; -- ; -- ; 00:01:22 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+