TroubleElectrical/FPGA_Uni
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
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Quartus/A1_Q3/output_files/asu.fit.summary
+3 -3
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@@ -1,13 +1,13 @@
Fitter Status : Successful - Tue Sep 15 10:01:03 2026
Fitter Status : Successful - Tue Sep 15 16:39:51 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : asu
Top-level Entity Name : asu
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 4 / 29,080 ( < 1 % )
Logic utilization (in ALMs) : 8 / 29,080 ( < 1 % )
Total registers : 0
Total pins : 15 / 364 ( 4 % )
Total pins : 23 / 364 ( 6 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )