Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
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@@ -1,5 +1,5 @@
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Fitter report for asu
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Tue Sep 15 10:01:03 2026
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Tue Sep 15 16:39:51 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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@@ -58,16 +58,16 @@ on the Quartus Prime software download page.
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+-----------------------------------------------------------------------------------+
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; Fitter Summary ;
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+---------------------------------+-------------------------------------------------+
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; Fitter Status ; Successful - Tue Sep 15 10:01:03 2026 ;
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; Fitter Status ; Successful - Tue Sep 15 16:39:51 2026 ;
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; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
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; Revision Name ; asu ;
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; Top-level Entity Name ; asu ;
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; Family ; Cyclone V ;
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; Device ; 5CGXFC5C6F27C7 ;
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; Timing Models ; Final ;
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; Logic utilization (in ALMs) ; 4 / 29,080 ( < 1 % ) ;
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; Logic utilization (in ALMs) ; 8 / 29,080 ( < 1 % ) ;
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; Total registers ; 0 ;
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; Total pins ; 15 / 364 ( 4 % ) ;
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; Total pins ; 23 / 364 ( 6 % ) ;
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; Total virtual pins ; 0 ;
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; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
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; Total RAM Blocks ; 0 / 446 ( 0 % ) ;
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@@ -153,7 +153,7 @@ on the Quartus Prime software download page.
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 0.3% ;
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; Processor 2 ; 0.4% ;
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+----------------------------+-------------+
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@@ -173,8 +173,8 @@ on the Quartus Prime software download page.
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; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
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+---------------------+-------------------+----------------------------+--------------------------+
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; Placement (by node) ; ; ; ;
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; -- Requested ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ;
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; -- Achieved ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ;
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; -- Requested ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ;
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; -- Achieved ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ;
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; ; ; ; ;
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; Routing (by net) ; ; ; ;
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; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
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@@ -197,7 +197,7 @@ on the Quartus Prime software download page.
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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; Top ; 0.00 % ( 0 / 37 ) ; N/A ; Source File ; N/A ; ;
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; Top ; 0.00 % ( 0 / 61 ) ; N/A ; Source File ; N/A ; ;
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; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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@@ -213,11 +213,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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+-------------------------------------------------------------+--------------------+-------+
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; Resource ; Usage ; % ;
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+-------------------------------------------------------------+--------------------+-------+
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; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 29,080 ; < 1 % ;
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; ALMs needed [=A-B+C] ; 4 ; ;
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; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 29,080 ; < 1 % ;
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; Logic utilization (ALMs needed / total ALMs on device) ; 8 / 29,080 ; < 1 % ;
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; ALMs needed [=A-B+C] ; 8 ; ;
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; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29,080 ; < 1 % ;
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; [a] ALMs used for LUT logic and registers ; 0 ; ;
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; [b] ALMs used for LUT logic ; 4 ; ;
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; [b] ALMs used for LUT logic ; 8 ; ;
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; [c] ALMs used for registers ; 0 ; ;
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; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
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; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ;
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@@ -233,12 +233,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; -- Logic LABs ; 2 ; ;
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; -- Memory LABs (up to half of total LABs) ; 0 ; ;
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; ; ; ;
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; Combinational ALUT usage for logic ; 7 ; ;
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; Combinational ALUT usage for logic ; 15 ; ;
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; -- 7 input functions ; 0 ; ;
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; -- 6 input functions ; 0 ; ;
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; -- 5 input functions ; 0 ; ;
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; -- 4 input functions ; 1 ; ;
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; -- <=3 input functions ; 6 ; ;
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; -- 4 input functions ; 8 ; ;
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; -- <=3 input functions ; 7 ; ;
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; Combinational ALUT usage for route-throughs ; 0 ; ;
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; ; ; ;
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; Dedicated logic registers ; 0 ; ;
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@@ -250,7 +250,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; -- Routing optimization registers ; 0 ; ;
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; ; ; ;
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; Virtual pins ; 0 ; ;
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; I/O pins ; 15 / 364 ; 4 % ;
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; I/O pins ; 23 / 364 ; 6 % ;
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; -- Clock pins ; 0 / 14 ; 0 % ;
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; -- Dedicated input pins ; 0 / 23 ; 0 % ;
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; ; ; ;
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@@ -281,12 +281,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; Channel PLLs ; 0 / 6 ; 0 % ;
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; Impedance control blocks ; 0 / 3 ; 0 % ;
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; Hard Memory Controllers ; 0 / 2 ; 0 % ;
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; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; ;
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; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.5% ; ;
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; Maximum fan-out ; 5 ; ;
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; Highest non-global fan-out ; 5 ; ;
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; Total fan-out ; 41 ; ;
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; Average fan-out ; 1.11 ; ;
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; Average interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.1% ; ;
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; Peak interconnect usage (total/H/V) ; 0.3% / 0.2% / 0.5% ; ;
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; Maximum fan-out ; 10 ; ;
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; Highest non-global fan-out ; 9 ; ;
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; Total fan-out ; 86 ; ;
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; Average fan-out ; 1.41 ; ;
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+-------------------------------------------------------------+--------------------+-------+
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@@ -295,11 +295,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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+-------------------------------------------------------------+---------------------+--------------------------------+
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; Statistic ; Top ; hard_block:auto_generated_inst ;
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+-------------------------------------------------------------+---------------------+--------------------------------+
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; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
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; ALMs needed [=A-B+C] ; 4 ; 0 ;
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; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
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; Logic utilization (ALMs needed / total ALMs on device) ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
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; ALMs needed [=A-B+C] ; 8 ; 0 ;
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; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
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; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
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; [b] ALMs used for LUT logic ; 4 ; 0 ;
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; [b] ALMs used for LUT logic ; 8 ; 0 ;
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; [c] ALMs used for registers ; 0 ; 0 ;
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; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
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; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
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@@ -315,12 +315,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; -- Logic LABs ; 2 ; 0 ;
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; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
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; ; ; ;
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; Combinational ALUT usage for logic ; 7 ; 0 ;
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; Combinational ALUT usage for logic ; 15 ; 0 ;
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; -- 7 input functions ; 0 ; 0 ;
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; -- 6 input functions ; 0 ; 0 ;
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; -- 5 input functions ; 0 ; 0 ;
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; -- 4 input functions ; 1 ; 0 ;
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; -- <=3 input functions ; 6 ; 0 ;
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; -- 4 input functions ; 8 ; 0 ;
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; -- <=3 input functions ; 7 ; 0 ;
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; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
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; Memory ALUT usage ; 0 ; 0 ;
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; -- 64-address deep ; 0 ; 0 ;
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@@ -336,7 +336,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; ; ; ;
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; ; ; ;
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; Virtual pins ; 0 ; 0 ;
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; I/O pins ; 15 ; 0 ;
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; I/O pins ; 23 ; 0 ;
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; I/O registers ; 0 ; 0 ;
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; Total block memory bits ; 0 ; 0 ;
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; Total block memory implementation bits ; 0 ; 0 ;
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@@ -348,7 +348,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; -- Registered Output Connections ; 0 ; 0 ;
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; ; ; ;
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; Internal Connections ; ; ;
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; -- Total Connections ; 45 ; 0 ;
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; -- Total Connections ; 86 ; 0 ;
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; -- Registered Connections ; 0 ; 0 ;
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; ; ; ;
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; External Connections ; ; ;
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@@ -357,7 +357,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; ; ; ;
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; Partition Interface ; ; ;
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; -- Input Ports ; 9 ; 0 ;
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; -- Output Ports ; 6 ; 0 ;
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; -- Output Ports ; 14 ; 0 ;
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; -- Bidir Ports ; 0 ; 0 ;
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; ; ; ;
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; Registered Ports ; ; ;
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@@ -389,40 +389,48 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
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; B[1] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; B[2] ; V10 ; 3B ; 17 ; 0 ; 74 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; B[3] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; op[0] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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; op[0] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
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+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Output Pins ;
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+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
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; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
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+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
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; COUT[0] ; J8 ; 8A ; 14 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_1[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_1[1] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_1[2] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_1[3] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_CIN[0] ; L7 ; 8A ; 10 ; 61 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Output Pins ;
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+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
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; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
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+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
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; COUT[0] ; J8 ; 8A ; 14 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_1[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_1[1] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_1[2] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_1[3] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; OUT_CIN[0] ; L7 ; 8A ; 10 ; 61 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; out_seg_1[0] ; A17 ; 7A ; 55 ; 61 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
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; out_seg_1[1] ; V19 ; 4A ; 66 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; out_seg_1[2] ; V18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; out_seg_1[3] ; V17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; out_seg_1[4] ; W18 ; 4A ; 66 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; out_seg_1[5] ; Y20 ; 4A ; 65 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; out_seg_1[6] ; Y19 ; 4A ; 65 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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; out_seg_1[7] ; Y18 ; 4A ; 62 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
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+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
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+---------------------------------------------------------------------------+
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; I/O Bank Usage ;
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+----------+-----------------+---------------+--------------+---------------+
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; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
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+----------+-----------------+---------------+--------------+---------------+
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; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
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; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
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; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
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||||
; 3B ; 6 / 32 ( 19 % ) ; 1.2V ; -- ; 2.5V ;
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; 4A ; 3 / 80 ( 4 % ) ; 1.2V ; -- ; 2.5V ;
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||||
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
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||||
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
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||||
; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
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||||
; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
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||||
; 8A ; 6 / 32 ( 19 % ) ; 2.5V ; -- ; 2.5V ;
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||||
+----------+-----------------+---------------+--------------+---------------+
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||||
+----------------------------------------------------------------------------+
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||||
; I/O Bank Usage ;
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||||
+----------+------------------+---------------+--------------+---------------+
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||||
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
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||||
+----------+------------------+---------------+--------------+---------------+
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||||
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
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||||
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
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||||
; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
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||||
; 3B ; 6 / 32 ( 19 % ) ; 1.2V ; -- ; 2.5V ;
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; 4A ; 10 / 80 ( 13 % ) ; 1.2V ; -- ; 2.5V ;
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||||
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
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||||
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
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; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
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; 7A ; 1 / 80 ( 1 % ) ; 2.5V ; -- ; 2.5V ;
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||||
; 8A ; 6 / 32 ( 19 % ) ; 2.5V ; -- ; 2.5V ;
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+----------+------------------+---------------+--------------+---------------+
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||||
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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@@ -445,7 +453,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
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; A14 ; 300 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; A16 ; 294 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A17 ; 292 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A17 ; 292 ; 7A ; out_seg_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; A18 ; 290 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A19 ; 288 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A20 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
@@ -1040,9 +1048,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V18 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V19 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; V17 ; 154 ; 4A ; out_seg_1[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; V18 ; 156 ; 4A ; out_seg_1[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; V19 ; 164 ; 4A ; out_seg_1[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
@@ -1067,7 +1075,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W18 ; 162 ; 4A ; out_seg_1[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
@@ -1093,9 +1101,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y18 ; 153 ; 4A ; out_seg_1[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; Y19 ; 159 ; 4A ; out_seg_1[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; Y20 ; 161 ; 4A ; out_seg_1[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||
; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
@@ -1106,18 +1114,27 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
|
||||
|
||||
+--------------------------------------------+
|
||||
; I/O Assignment Warnings ;
|
||||
+------------+-------------------------------+
|
||||
; Pin Name ; Reason ;
|
||||
+------------+-------------------------------+
|
||||
; OUT_1[0] ; Incomplete set of assignments ;
|
||||
; OUT_1[1] ; Incomplete set of assignments ;
|
||||
; OUT_1[2] ; Incomplete set of assignments ;
|
||||
; OUT_1[3] ; Incomplete set of assignments ;
|
||||
; COUT[0] ; Incomplete set of assignments ;
|
||||
; OUT_CIN[0] ; Incomplete set of assignments ;
|
||||
+------------+-------------------------------+
|
||||
+-----------------------------------------------------+
|
||||
; I/O Assignment Warnings ;
|
||||
+--------------+--------------------------------------+
|
||||
; Pin Name ; Reason ;
|
||||
+--------------+--------------------------------------+
|
||||
; OUT_1[0] ; Incomplete set of assignments ;
|
||||
; OUT_1[1] ; Incomplete set of assignments ;
|
||||
; OUT_1[2] ; Incomplete set of assignments ;
|
||||
; OUT_1[3] ; Incomplete set of assignments ;
|
||||
; COUT[0] ; Incomplete set of assignments ;
|
||||
; OUT_CIN[0] ; Incomplete set of assignments ;
|
||||
; out_seg_1[0] ; Incomplete set of assignments ;
|
||||
; out_seg_1[1] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[2] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[3] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[4] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[5] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[6] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[7] ; Missing drive strength and slew rate ;
|
||||
; out_seg_1[0] ; Missing location assignment ;
|
||||
+--------------+--------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@@ -1125,32 +1142,41 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
|
||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; |asu ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 15 ; 0 ; |asu ; asu ; work ;
|
||||
; |asu ; 7.5 (4.0) ; 7.5 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 15 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 23 ; 0 ; |asu ; asu ; work ;
|
||||
; |seven_seg:dut| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |asu|seven_seg:dut ; seven_seg ; work ;
|
||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------+
|
||||
; Delay Chain Summary ;
|
||||
+------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
||||
+------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; COUT[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_CIN[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
+------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
+-----------------------------------------------------------------------------------------------------------------------------+
|
||||
; Delay Chain Summary ;
|
||||
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
||||
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; COUT[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_CIN[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; out_seg_1[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; op[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------+
|
||||
@@ -1159,29 +1185,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
||||
+---------------------+-------------------+---------+
|
||||
; op[0] ; ; ;
|
||||
; - _~1 ; 0 ; 0 ;
|
||||
; - _~5 ; 0 ; 0 ;
|
||||
; - _~9 ; 0 ; 0 ;
|
||||
; - _~13 ; 0 ; 0 ;
|
||||
; - OUT_CIN~0 ; 0 ; 0 ;
|
||||
; A[3] ; ; ;
|
||||
; - _~13 ; 0 ; 0 ;
|
||||
; - OUT_CIN~0 ; 0 ; 0 ;
|
||||
; - Add0~22 ; 1 ; 0 ;
|
||||
; - Add0~1 ; 1 ; 0 ;
|
||||
; - Add0~5 ; 1 ; 0 ;
|
||||
; - Add0~9 ; 1 ; 0 ;
|
||||
; - Add0~13 ; 1 ; 0 ;
|
||||
; - OUT_CIN~0 ; 1 ; 0 ;
|
||||
; B[3] ; ; ;
|
||||
; - _~13 ; 0 ; 0 ;
|
||||
; - OUT_CIN~0 ; 0 ; 0 ;
|
||||
; - Add0~13 ; 1 ; 0 ;
|
||||
; - OUT_CIN~0 ; 1 ; 0 ;
|
||||
; A[3] ; ; ;
|
||||
; - Add0~13 ; 1 ; 0 ;
|
||||
; - OUT_CIN~0 ; 1 ; 0 ;
|
||||
; B[0] ; ; ;
|
||||
; - _~1 ; 0 ; 0 ;
|
||||
; - Add0~1 ; 0 ; 0 ;
|
||||
; A[0] ; ; ;
|
||||
; - _~1 ; 1 ; 0 ;
|
||||
; A[1] ; ; ;
|
||||
; - _~5 ; 1 ; 0 ;
|
||||
; - Add0~1 ; 1 ; 0 ;
|
||||
; B[1] ; ; ;
|
||||
; - _~5 ; 1 ; 0 ;
|
||||
; A[2] ; ; ;
|
||||
; - _~9 ; 1 ; 0 ;
|
||||
; - Add0~5 ; 0 ; 0 ;
|
||||
; A[1] ; ; ;
|
||||
; - Add0~5 ; 1 ; 0 ;
|
||||
; B[2] ; ; ;
|
||||
; - _~9 ; 1 ; 0 ;
|
||||
; - Add0~9 ; 1 ; 0 ;
|
||||
; A[2] ; ; ;
|
||||
; - Add0~9 ; 1 ; 0 ;
|
||||
+---------------------+-------------------+---------+
|
||||
|
||||
|
||||
@@ -1190,22 +1217,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+------------------------------+------------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+------------------------------+------------------------+
|
||||
; Block interconnects ; 15 / 217,884 ( < 1 % ) ;
|
||||
; C12 interconnects ; 8 / 10,080 ( < 1 % ) ;
|
||||
; C2 interconnects ; 8 / 87,208 ( < 1 % ) ;
|
||||
; C4 interconnects ; 77 / 41,360 ( < 1 % ) ;
|
||||
; Block interconnects ; 22 / 217,884 ( < 1 % ) ;
|
||||
; C12 interconnects ; 0 / 10,080 ( 0 % ) ;
|
||||
; C2 interconnects ; 18 / 87,208 ( < 1 % ) ;
|
||||
; C4 interconnects ; 95 / 41,360 ( < 1 % ) ;
|
||||
; DQS bus muxes ; 0 / 21 ( 0 % ) ;
|
||||
; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||
; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||
; Direct links ; 0 / 217,884 ( 0 % ) ;
|
||||
; Global clocks ; 0 / 16 ( 0 % ) ;
|
||||
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
||||
; Local interconnects ; 1 / 58,160 ( < 1 % ) ;
|
||||
; Local interconnects ; 4 / 58,160 ( < 1 % ) ;
|
||||
; Quadrant clocks ; 0 / 88 ( 0 % ) ;
|
||||
; R14 interconnects ; 6 / 9,228 ( < 1 % ) ;
|
||||
; R14/C12 interconnect drivers ; 12 / 15,096 ( < 1 % ) ;
|
||||
; R3 interconnects ; 15 / 94,896 ( < 1 % ) ;
|
||||
; R6 interconnects ; 9 / 194,640 ( < 1 % ) ;
|
||||
; R14 interconnects ; 14 / 9,228 ( < 1 % ) ;
|
||||
; R14/C12 interconnect drivers ; 14 / 15,096 ( < 1 % ) ;
|
||||
; R3 interconnects ; 25 / 94,896 ( < 1 % ) ;
|
||||
; R6 interconnects ; 48 / 194,640 ( < 1 % ) ;
|
||||
; Spine clocks ; 0 / 180 ( 0 % ) ;
|
||||
; Wire stub REs ; 0 / 11,606 ( 0 % ) ;
|
||||
+------------------------------+------------------------+
|
||||
@@ -1261,31 +1288,39 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; I/O Rules Matrix ;
|
||||
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
||||
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Total Pass ; 0 ; 15 ; 15 ; 0 ; 0 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 15 ; 15 ; 0 ;
|
||||
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; Total Inapplicable ; 15 ; 0 ; 0 ; 15 ; 15 ; 0 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 15 ; 9 ; 15 ; 15 ; 15 ; 15 ; 9 ; 15 ; 15 ; 15 ; 15 ; 9 ; 15 ; 0 ; 0 ; 15 ;
|
||||
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; COUT[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_CIN[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; I/O Rules Matrix ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
; Total Pass ; 0 ; 22 ; 22 ; 0 ; 0 ; 23 ; 22 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 23 ; 23 ; 0 ;
|
||||
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; Total Inapplicable ; 23 ; 1 ; 1 ; 23 ; 23 ; 0 ; 1 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 0 ; 0 ; 23 ;
|
||||
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; COUT[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_CIN[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; out_seg_1[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------+
|
||||
@@ -1342,12 +1377,13 @@ Info (21077): High junction temperature is 85 degrees C
|
||||
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
||||
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
|
||||
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
||||
Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 23 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
|
||||
Info (184020): Starting Fitter periphery placement operations
|
||||
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
|
||||
Info (176233): Starting register packing
|
||||
Info (176235): Finished register packing
|
||||
Extra Info (176219): No registers were packed into other blocks
|
||||
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
|
||||
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07
|
||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||||
Info (332144): No user constrained base clocks found in the design
|
||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||||
@@ -1363,7 +1399,7 @@ Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11
|
||||
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170200): Optimizations that may affect the design's timing were skipped
|
||||
@@ -1373,12 +1409,12 @@ Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05
|
||||
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
|
||||
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
|
||||
Info: Peak virtual memory: 1380 megabytes
|
||||
Info: Processing ended: Tue Sep 15 10:01:04 2026
|
||||
Info: Elapsed time: 00:00:41
|
||||
Info: Total CPU time (on all processors): 00:00:52
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings
|
||||
Info: Peak virtual memory: 1340 megabytes
|
||||
Info: Processing ended: Tue Sep 15 16:39:52 2026
|
||||
Info: Elapsed time: 00:00:31
|
||||
Info: Total CPU time (on all processors): 00:00:42
|
||||
|
||||
|
||||
Reference in new issue
Block a user