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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
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Quartus/A1_Q3/output_files/asu.asm.rpt
+9 -9
View File
@@ -1,5 +1,5 @@
Assembler report for asu
Tue Sep 15 10:01:14 2026
Tue Sep 15 16:40:00 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Sep 15 10:01:14 2026 ;
; Assembler Status ; Successful - Tue Sep 15 16:40:00 2026 ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
+----------------+------------------+
; Option ; Setting ;
+----------------+------------------+
; JTAG usercode ; 0x00781610 ;
; Checksum ; 0x00781610 ;
; JTAG usercode ; 0x00784D66 ;
; Checksum ; 0x00784D66 ;
+----------------+------------------+
@@ -78,14 +78,14 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:01:06 2026
Info: Processing started: Tue Sep 15 16:39:54 2026
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 521 megabytes
Info: Processing ended: Tue Sep 15 10:01:14 2026
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:08
Info: Peak virtual memory: 507 megabytes
Info: Processing ended: Tue Sep 15 16:40:00 2026
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:06
Quartus/A1_Q3/output_files/asu.done
+1 -1
View File
@@ -1 +1 @@
Tue Sep 15 10:01:29 2026
Tue Sep 15 16:40:10 2026
Quartus/A1_Q3/output_files/asu.eda.rpt
+7 -7
View File
@@ -1,5 +1,5 @@
EDA Netlist Writer report for asu
Tue Sep 15 10:01:28 2026
Tue Sep 15 16:40:09 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:01:28 2026 ;
; EDA Netlist Writer Status ; Successful - Tue Sep 15 16:40:09 2026 ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
@@ -81,14 +81,14 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:01:26 2026
Info: Processing started: Tue Sep 15 16:40:08 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file asu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 658 megabytes
Info: Processing ended: Tue Sep 15 10:01:28 2026
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Info: Peak virtual memory: 666 megabytes
Info: Processing ended: Tue Sep 15 16:40:09 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Quartus/A1_Q3/output_files/asu.fit.rpt
+199 -163
View File
@@ -1,5 +1,5 @@
Fitter report for asu
Tue Sep 15 10:01:03 2026
Tue Sep 15 16:39:51 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -58,16 +58,16 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Tue Sep 15 10:01:03 2026 ;
; Fitter Status ; Successful - Tue Sep 15 16:39:51 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 4 / 29,080 ( < 1 % ) ;
; Logic utilization (in ALMs) ; 8 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 15 / 364 ( 4 % ) ;
; Total pins ; 23 / 364 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total RAM Blocks ; 0 / 446 ( 0 % ) ;
@@ -153,7 +153,7 @@ on the Quartus Prime software download page.
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.3% ;
; Processor 2 ; 0.4% ;
+----------------------------+-------------+
@@ -173,8 +173,8 @@ on the Quartus Prime software download page.
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+-------------------+----------------------------+--------------------------+
; Placement (by node) ; ; ; ;
; -- Requested ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ;
; -- Achieved ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ;
; -- Requested ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ;
; -- Achieved ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ; 0.00 % ( 0 / 61 ) ;
; ; ; ; ;
; Routing (by net) ; ; ; ;
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
@@ -197,7 +197,7 @@ on the Quartus Prime software download page.
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top ; 0.00 % ( 0 / 37 ) ; N/A ; Source File ; N/A ; ;
; Top ; 0.00 % ( 0 / 61 ) ; N/A ; Source File ; N/A ; ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
@@ -213,11 +213,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
+-------------------------------------------------------------+--------------------+-------+
; Resource ; Usage ; % ;
+-------------------------------------------------------------+--------------------+-------+
; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 29,080 ; < 1 % ;
; ALMs needed [=A-B+C] ; 4 ; ;
; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 29,080 ; < 1 % ;
; Logic utilization (ALMs needed / total ALMs on device) ; 8 / 29,080 ; < 1 % ;
; ALMs needed [=A-B+C] ; 8 ; ;
; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29,080 ; < 1 % ;
; [a] ALMs used for LUT logic and registers ; 0 ; ;
; [b] ALMs used for LUT logic ; 4 ; ;
; [b] ALMs used for LUT logic ; 8 ; ;
; [c] ALMs used for registers ; 0 ; ;
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ;
@@ -233,12 +233,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; -- Logic LABs ; 2 ; ;
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
; ; ; ;
; Combinational ALUT usage for logic ; 7 ; ;
; Combinational ALUT usage for logic ; 15 ; ;
; -- 7 input functions ; 0 ; ;
; -- 6 input functions ; 0 ; ;
; -- 5 input functions ; 0 ; ;
; -- 4 input functions ; 1 ; ;
; -- <=3 input functions ; 6 ; ;
; -- 4 input functions ; 8 ; ;
; -- <=3 input functions ; 7 ; ;
; Combinational ALUT usage for route-throughs ; 0 ; ;
; ; ; ;
; Dedicated logic registers ; 0 ; ;
@@ -250,7 +250,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; -- Routing optimization registers ; 0 ; ;
; ; ; ;
; Virtual pins ; 0 ; ;
; I/O pins ; 15 / 364 ; 4 % ;
; I/O pins ; 23 / 364 ; 6 % ;
; -- Clock pins ; 0 / 14 ; 0 % ;
; -- Dedicated input pins ; 0 / 23 ; 0 % ;
; ; ; ;
@@ -281,12 +281,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; Channel PLLs ; 0 / 6 ; 0 % ;
; Impedance control blocks ; 0 / 3 ; 0 % ;
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; ;
; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.5% ; ;
; Maximum fan-out ; 5 ; ;
; Highest non-global fan-out ; 5 ; ;
; Total fan-out ; 41 ; ;
; Average fan-out ; 1.11 ; ;
; Average interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.1% ; ;
; Peak interconnect usage (total/H/V) ; 0.3% / 0.2% / 0.5% ; ;
; Maximum fan-out ; 10 ; ;
; Highest non-global fan-out ; 9 ; ;
; Total fan-out ; 86 ; ;
; Average fan-out ; 1.41 ; ;
+-------------------------------------------------------------+--------------------+-------+
@@ -295,11 +295,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
+-------------------------------------------------------------+---------------------+--------------------------------+
; Statistic ; Top ; hard_block:auto_generated_inst ;
+-------------------------------------------------------------+---------------------+--------------------------------+
; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
; ALMs needed [=A-B+C] ; 4 ; 0 ;
; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
; Logic utilization (ALMs needed / total ALMs on device) ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
; ALMs needed [=A-B+C] ; 8 ; 0 ;
; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
; [b] ALMs used for LUT logic ; 4 ; 0 ;
; [b] ALMs used for LUT logic ; 8 ; 0 ;
; [c] ALMs used for registers ; 0 ; 0 ;
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
@@ -315,12 +315,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; -- Logic LABs ; 2 ; 0 ;
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
; ; ; ;
; Combinational ALUT usage for logic ; 7 ; 0 ;
; Combinational ALUT usage for logic ; 15 ; 0 ;
; -- 7 input functions ; 0 ; 0 ;
; -- 6 input functions ; 0 ; 0 ;
; -- 5 input functions ; 0 ; 0 ;
; -- 4 input functions ; 1 ; 0 ;
; -- <=3 input functions ; 6 ; 0 ;
; -- 4 input functions ; 8 ; 0 ;
; -- <=3 input functions ; 7 ; 0 ;
; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
; Memory ALUT usage ; 0 ; 0 ;
; -- 64-address deep ; 0 ; 0 ;
@@ -336,7 +336,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; ; ; ;
; ; ; ;
; Virtual pins ; 0 ; 0 ;
; I/O pins ; 15 ; 0 ;
; I/O pins ; 23 ; 0 ;
; I/O registers ; 0 ; 0 ;
; Total block memory bits ; 0 ; 0 ;
; Total block memory implementation bits ; 0 ; 0 ;
@@ -348,7 +348,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
; -- Total Connections ; 45 ; 0 ;
; -- Total Connections ; 86 ; 0 ;
; -- Registered Connections ; 0 ; 0 ;
; ; ; ;
; External Connections ; ; ;
@@ -357,7 +357,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; ; ; ;
; Partition Interface ; ; ;
; -- Input Ports ; 9 ; 0 ;
; -- Output Ports ; 6 ; 0 ;
; -- Output Ports ; 14 ; 0 ;
; -- Bidir Ports ; 0 ; 0 ;
; ; ; ;
; Registered Ports ; ; ;
@@ -389,40 +389,48 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; B[1] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
; B[2] ; V10 ; 3B ; 17 ; 0 ; 74 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
; B[3] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
; op[0] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
; op[0] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
; COUT[0] ; J8 ; 8A ; 14 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_1[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_1[1] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_1[2] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_1[3] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_CIN[0] ; L7 ; 8A ; 10 ; 61 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
; COUT[0] ; J8 ; 8A ; 14 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_1[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_1[1] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_1[2] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_1[3] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; OUT_CIN[0] ; L7 ; 8A ; 10 ; 61 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; out_seg_1[0] ; A17 ; 7A ; 55 ; 61 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
; out_seg_1[1] ; V19 ; 4A ; 66 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; out_seg_1[2] ; V18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; out_seg_1[3] ; V17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; out_seg_1[4] ; W18 ; 4A ; 66 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; out_seg_1[5] ; Y20 ; 4A ; 65 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; out_seg_1[6] ; Y19 ; 4A ; 65 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; out_seg_1[7] ; Y18 ; 4A ; 62 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+---------------------------------------------------------------------------+
; I/O Bank Usage ;
+----------+-----------------+---------------+--------------+---------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
+----------+-----------------+---------------+--------------+---------------+
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 3B ; 6 / 32 ( 19 % ) ; 1.2V ; -- ; 2.5V ;
; 4A ; 3 / 80 ( 4 % ) ; 1.2V ; -- ; 2.5V ;
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 8A ; 6 / 32 ( 19 % ) ; 2.5V ; -- ; 2.5V ;
+----------+-----------------+---------------+--------------+---------------+
+----------------------------------------------------------------------------+
; I/O Bank Usage ;
+----------+------------------+---------------+--------------+---------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
+----------+------------------+---------------+--------------+---------------+
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 3B ; 6 / 32 ( 19 % ) ; 1.2V ; -- ; 2.5V ;
; 4A ; 10 / 80 ( 13 % ) ; 1.2V ; -- ; 2.5V ;
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 7A ; 1 / 80 ( 1 % ) ; 2.5V ; -- ; 2.5V ;
; 8A ; 6 / 32 ( 19 % ) ; 2.5V ; -- ; 2.5V ;
+----------+------------------+---------------+--------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -445,7 +453,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; A14 ; 300 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; A16 ; 294 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A17 ; 292 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A17 ; 292 ; 7A ; out_seg_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; A18 ; 290 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A19 ; 288 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A20 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
@@ -1040,9 +1048,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V18 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V19 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; V17 ; 154 ; 4A ; out_seg_1[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; V18 ; 156 ; 4A ; out_seg_1[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; V19 ; 164 ; 4A ; out_seg_1[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
@@ -1067,7 +1075,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; W18 ; 162 ; 4A ; out_seg_1[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
@@ -1093,9 +1101,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; Y18 ; 153 ; 4A ; out_seg_1[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; Y19 ; 159 ; 4A ; out_seg_1[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; Y20 ; 161 ; 4A ; out_seg_1[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
@@ -1106,18 +1114,27 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+--------------------------------------------+
; I/O Assignment Warnings ;
+------------+-------------------------------+
; Pin Name ; Reason ;
+------------+-------------------------------+
; OUT_1[0] ; Incomplete set of assignments ;
; OUT_1[1] ; Incomplete set of assignments ;
; OUT_1[2] ; Incomplete set of assignments ;
; OUT_1[3] ; Incomplete set of assignments ;
; COUT[0] ; Incomplete set of assignments ;
; OUT_CIN[0] ; Incomplete set of assignments ;
+------------+-------------------------------+
+-----------------------------------------------------+
; I/O Assignment Warnings ;
+--------------+--------------------------------------+
; Pin Name ; Reason ;
+--------------+--------------------------------------+
; OUT_1[0] ; Incomplete set of assignments ;
; OUT_1[1] ; Incomplete set of assignments ;
; OUT_1[2] ; Incomplete set of assignments ;
; OUT_1[3] ; Incomplete set of assignments ;
; COUT[0] ; Incomplete set of assignments ;
; OUT_CIN[0] ; Incomplete set of assignments ;
; out_seg_1[0] ; Incomplete set of assignments ;
; out_seg_1[1] ; Missing drive strength and slew rate ;
; out_seg_1[2] ; Missing drive strength and slew rate ;
; out_seg_1[3] ; Missing drive strength and slew rate ;
; out_seg_1[4] ; Missing drive strength and slew rate ;
; out_seg_1[5] ; Missing drive strength and slew rate ;
; out_seg_1[6] ; Missing drive strength and slew rate ;
; out_seg_1[7] ; Missing drive strength and slew rate ;
; out_seg_1[0] ; Missing location assignment ;
+--------------+--------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -1125,32 +1142,41 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
; |asu ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 15 ; 0 ; |asu ; asu ; work ;
; |asu ; 7.5 (4.0) ; 7.5 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 15 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 23 ; 0 ; |asu ; asu ; work ;
; |seven_seg:dut| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |asu|seven_seg:dut ; seven_seg ; work ;
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------+
; Delay Chain Summary ;
+------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
+------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; COUT[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; OUT_CIN[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; A[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; B[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; B[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; A[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; B[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Delay Chain Summary ;
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; COUT[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; OUT_CIN[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; out_seg_1[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
; op[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; A[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; B[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; A[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+---------------------------------------------------+
@@ -1159,29 +1185,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; op[0] ; ; ;
; - _~1 ; 0 ; 0 ;
; - _~5 ; 0 ; 0 ;
; - _~9 ; 0 ; 0 ;
; - _~13 ; 0 ; 0 ;
; - OUT_CIN~0 ; 0 ; 0 ;
; A[3] ; ; ;
; - _~13 ; 0 ; 0 ;
; - OUT_CIN~0 ; 0 ; 0 ;
; - Add0~22 ; 1 ; 0 ;
; - Add0~1 ; 1 ; 0 ;
; - Add0~5 ; 1 ; 0 ;
; - Add0~9 ; 1 ; 0 ;
; - Add0~13 ; 1 ; 0 ;
; - OUT_CIN~0 ; 1 ; 0 ;
; B[3] ; ; ;
; - _~13 ; 0 ; 0 ;
; - OUT_CIN~0 ; 0 ; 0 ;
; - Add0~13 ; 1 ; 0 ;
; - OUT_CIN~0 ; 1 ; 0 ;
; A[3] ; ; ;
; - Add0~13 ; 1 ; 0 ;
; - OUT_CIN~0 ; 1 ; 0 ;
; B[0] ; ; ;
; - _~1 ; 0 ; 0 ;
; - Add0~1 ; 0 ; 0 ;
; A[0] ; ; ;
; - _~1 ; 1 ; 0 ;
; A[1] ; ; ;
; - _~5 ; 1 ; 0 ;
; - Add0~1 ; 1 ; 0 ;
; B[1] ; ; ;
; - _~5 ; 1 ; 0 ;
; A[2] ; ; ;
; - _~9 ; 1 ; 0 ;
; - Add0~5 ; 0 ; 0 ;
; A[1] ; ; ;
; - Add0~5 ; 1 ; 0 ;
; B[2] ; ; ;
; - _~9 ; 1 ; 0 ;
; - Add0~9 ; 1 ; 0 ;
; A[2] ; ; ;
; - Add0~9 ; 1 ; 0 ;
+---------------------+-------------------+---------+
@@ -1190,22 +1217,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------+------------------------+
; Routing Resource Type ; Usage ;
+------------------------------+------------------------+
; Block interconnects ; 15 / 217,884 ( < 1 % ) ;
; C12 interconnects ; 8 / 10,080 ( < 1 % ) ;
; C2 interconnects ; 8 / 87,208 ( < 1 % ) ;
; C4 interconnects ; 77 / 41,360 ( < 1 % ) ;
; Block interconnects ; 22 / 217,884 ( < 1 % ) ;
; C12 interconnects ; 0 / 10,080 ( 0 % ) ;
; C2 interconnects ; 18 / 87,208 ( < 1 % ) ;
; C4 interconnects ; 95 / 41,360 ( < 1 % ) ;
; DQS bus muxes ; 0 / 21 ( 0 % ) ;
; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ;
; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ;
; Direct links ; 0 / 217,884 ( 0 % ) ;
; Global clocks ; 0 / 16 ( 0 % ) ;
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
; Local interconnects ; 1 / 58,160 ( < 1 % ) ;
; Local interconnects ; 4 / 58,160 ( < 1 % ) ;
; Quadrant clocks ; 0 / 88 ( 0 % ) ;
; R14 interconnects ; 6 / 9,228 ( < 1 % ) ;
; R14/C12 interconnect drivers ; 12 / 15,096 ( < 1 % ) ;
; R3 interconnects ; 15 / 94,896 ( < 1 % ) ;
; R6 interconnects ; 9 / 194,640 ( < 1 % ) ;
; R14 interconnects ; 14 / 9,228 ( < 1 % ) ;
; R14/C12 interconnect drivers ; 14 / 15,096 ( < 1 % ) ;
; R3 interconnects ; 25 / 94,896 ( < 1 % ) ;
; R6 interconnects ; 48 / 194,640 ( < 1 % ) ;
; Spine clocks ; 0 / 180 ( 0 % ) ;
; Wire stub REs ; 0 / 11,606 ( 0 % ) ;
+------------------------------+------------------------+
@@ -1261,31 +1288,39 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix ;
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
; Total Pass ; 0 ; 15 ; 15 ; 0 ; 0 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 15 ; 15 ; 0 ;
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Inapplicable ; 15 ; 0 ; 0 ; 15 ; 15 ; 0 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 15 ; 9 ; 15 ; 15 ; 15 ; 15 ; 9 ; 15 ; 15 ; 15 ; 15 ; 9 ; 15 ; 0 ; 0 ; 15 ;
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; COUT[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; OUT_CIN[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
; Total Pass ; 0 ; 22 ; 22 ; 0 ; 0 ; 23 ; 22 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 23 ; 23 ; 0 ;
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Inapplicable ; 23 ; 1 ; 1 ; 23 ; 23 ; 0 ; 1 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 23 ; 23 ; 23 ; 9 ; 23 ; 0 ; 0 ; 23 ;
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; COUT[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; OUT_CIN[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; out_seg_1[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; B[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+------------------------------------------------------------------------------------------------+
@@ -1342,12 +1377,13 @@ Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 23 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Info (184020): Starting Fitter periphery placement operations
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176219): No registers were packed into other blocks
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07
Critical Warning (332012): Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
@@ -1363,7 +1399,7 @@ Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
@@ -1373,12 +1409,12 @@ Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 1380 megabytes
Info: Processing ended: Tue Sep 15 10:01:04 2026
Info: Elapsed time: 00:00:41
Info: Total CPU time (on all processors): 00:00:52
Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings
Info: Peak virtual memory: 1340 megabytes
Info: Processing ended: Tue Sep 15 16:39:52 2026
Info: Elapsed time: 00:00:31
Info: Total CPU time (on all processors): 00:00:42
Quartus/A1_Q3/output_files/asu.fit.summary
+3 -3
View File
@@ -1,13 +1,13 @@
Fitter Status : Successful - Tue Sep 15 10:01:03 2026
Fitter Status : Successful - Tue Sep 15 16:39:51 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : asu
Top-level Entity Name : asu
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 4 / 29,080 ( < 1 % )
Logic utilization (in ALMs) : 8 / 29,080 ( < 1 % )
Total registers : 0
Total pins : 15 / 364 ( 4 % )
Total pins : 23 / 364 ( 6 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )
Quartus/A1_Q3/output_files/asu.flow.rpt
+12 -12
View File
@@ -1,5 +1,5 @@
Flow report for asu
Tue Sep 15 10:01:28 2026
Tue Sep 15 16:40:09 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,16 +41,16 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Sep 15 10:01:28 2026 ;
; Flow Status ; Successful - Tue Sep 15 16:40:09 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 4 / 29,080 ( < 1 % ) ;
; Logic utilization (in ALMs) ; 8 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 15 / 364 ( 4 % ) ;
; Total pins ; 23 / 364 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/15/2026 10:00:07 ;
; Start date & time ; 09/15/2026 16:39:08 ;
; Main task ; Compilation ;
; Revision Name ; asu ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 253029099468756.178943040705122 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 268883478169649.178945434810068 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:16 ; 1.0 ; 422 MB ; 00:00:32 ;
; Fitter ; 00:00:40 ; 1.0 ; 1380 MB ; 00:00:51 ;
; Assembler ; 00:00:08 ; 1.0 ; 521 MB ; 00:00:08 ;
; Timing Analyzer ; 00:00:08 ; 1.0 ; 785 MB ; 00:00:08 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:01:14 ; -- ; -- ; 00:01:40 ;
; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 419 MB ; 00:00:28 ;
; Fitter ; 00:00:30 ; 1.0 ; 1340 MB ; 00:00:42 ;
; Assembler ; 00:00:06 ; 1.0 ; 507 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 750 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ;
; Total ; 00:00:54 ; -- ; -- ; 00:01:22 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
Quartus/A1_Q3/output_files/asu.map.rpt
+79 -58
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for asu
Tue Sep 15 10:00:22 2026
Tue Sep 15 16:39:20 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -15,9 +15,10 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Parameter Settings for User Entity Instance: Top-level Entity: |asu
10. Post-Synthesis Netlist Statistics for Top Partition
11. Elapsed Time Per Partition
12. Analysis & Synthesis Messages
10. Port Connectivity Checks: "seven_seg:dut"
11. Post-Synthesis Netlist Statistics for Top Partition
12. Elapsed Time Per Partition
13. Analysis & Synthesis Messages
@@ -44,14 +45,14 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:00:22 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 15 16:39:20 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 0 ;
; Total pins ; 15 ;
; Total pins ; 23 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; Total DSP Blocks ; 0 ;
@@ -167,40 +168,41 @@ on the Quartus Prime software download page.
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------+---------+
; ../../modules/asu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
; ../../modules/asu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ;
; seven_seg.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/seven_seg.sv ; ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------------+
; Resource ; Usage ;
+---------------------------------------------+-------------+
; Estimate of Logic utilization (ALMs needed) ; 3 ;
; ; ;
; Combinational ALUT usage for logic ; 6 ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
; -- 5 input functions ; 0 ;
; -- 4 input functions ; 1 ;
; -- <=3 input functions ; 5 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 15 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; op[0]~input ;
; Maximum fan-out ; 5 ;
; Total fan-out ; 41 ;
; Average fan-out ; 1.14 ;
+---------------------------------------------+-------------+
+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
; Estimate of Logic utilization (ALMs needed) ; 7 ;
; ; ;
; Combinational ALUT usage for logic ; 14 ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
; -- 5 input functions ; 0 ;
; -- 4 input functions ; 8 ;
; -- <=3 input functions ; 6 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 23 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; Add0~13 ;
; Maximum fan-out ; 10 ;
; Total fan-out ; 86 ;
; Average fan-out ; 1.43 ;
+---------------------------------------------+---------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -208,7 +210,8 @@ on the Quartus Prime software download page.
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; |asu ; 6 (6) ; 0 (0) ; 0 ; 0 ; 15 ; 0 ; |asu ; asu ; work ;
; |asu ; 14 (7) ; 0 (0) ; 0 ; 0 ; 23 ; 0 ; |asu ; asu ; work ;
; |seven_seg:dut| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |asu|seven_seg:dut ; seven_seg ; work ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -238,21 +241,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "seven_seg:dut" ;
+------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; rbi_inv ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
; rbi_inv[0] ; Input ; Info ; Stuck at VCC ;
+------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_lcell_comb ; 6 ;
; normal ; 1 ;
; 4 data inputs ; 1 ;
; shared ; 5 ;
; arriav_lcell_comb ; 16 ;
; arith ; 6 ;
; 0 data inputs ; 1 ;
; 1 data inputs ; 1 ;
; 3 data inputs ; 4 ;
; boundary_port ; 15 ;
; normal ; 10 ;
; 0 data inputs ; 1 ;
; 1 data inputs ; 1 ;
; 4 data inputs ; 8 ;
; boundary_port ; 23 ;
; ; ;
; Max LUT depth ; 2.30 ;
; Average LUT depth ; 1.95 ;
; Max LUT depth ; 3.40 ;
; Average LUT depth ; 2.82 ;
+-----------------------+-----------------------------+
@@ -261,7 +277,7 @@ Note: In order to hide this table in the UI and the text report file, please set
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:01 ;
; Top ; 00:00:00 ;
+----------------+--------------+
@@ -271,24 +287,29 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:00:06 2026
Info: Processing started: Tue Sep 15 16:39:08 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv
Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4
Info (12021): Found 2 design units, including 2 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv
Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/seven_seg.sv Line: 3
Info (12023): Found entity 2: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 5
Info (12127): Elaborating entity "asu" for the top level hierarchy
Info (12128): Elaborating entity "seven_seg" for hierarchy "seven_seg:dut" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 24
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "out_seg_1[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 9
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 21 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 37 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 9 input pins
Info (21059): Implemented 6 output pins
Info (21061): Implemented 6 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 439 megabytes
Info: Processing ended: Tue Sep 15 10:00:22 2026
Info: Elapsed time: 00:00:16
Info: Total CPU time (on all processors): 00:00:32
Info (21059): Implemented 14 output pins
Info (21061): Implemented 14 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 433 megabytes
Info: Processing ended: Tue Sep 15 16:39:20 2026
Info: Elapsed time: 00:00:12
Info: Total CPU time (on all processors): 00:00:28
Quartus/A1_Q3/output_files/asu.map.summary
+2 -2
View File
@@ -1,11 +1,11 @@
Analysis & Synthesis Status : Successful - Tue Sep 15 10:00:22 2026
Analysis & Synthesis Status : Successful - Tue Sep 15 16:39:20 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : asu
Top-level Entity Name : asu
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 15
Total pins : 23
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Quartus/A1_Q3/output_files/asu.pin
+8 -8
View File
@@ -91,7 +91,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7A :
GND : A15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A :
out_seg_1[0] : A17 : output : 2.5 V : : 7A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A :
VCCIO7A : A20 : power : : 2.5V : 7A :
@@ -686,9 +686,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A :
GND : V16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A :
out_seg_1[3] : V17 : output : 1.2 V : : 4A : Y
out_seg_1[2] : V18 : output : 1.2 V : : 4A : Y
out_seg_1[1] : V19 : output : 1.2 V : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A :
VCCIO5A : V21 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A :
@@ -713,7 +713,7 @@ VCCIO4A : W14 : power : : 1.2V
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A :
out_seg_1[4] : W18 : output : 1.2 V : : 4A : Y
GND : W19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
@@ -739,9 +739,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A :
VCCIO4A : Y17 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A :
out_seg_1[7] : Y18 : output : 1.2 V : : 4A : Y
out_seg_1[6] : Y19 : output : 1.2 V : : 4A : Y
out_seg_1[5] : Y20 : output : 1.2 V : : 4A : Y
VCCA_FPLL : Y21 : power : : 2.5V : :
GND : Y22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
Quartus/A1_Q3/output_files/asu.sof
BIN
View File
Binary file not shown.
Quartus/A1_Q3/output_files/asu.sta.rpt
+152 -98
View File
@@ -1,5 +1,5 @@
Timing Analyzer report for asu
Tue Sep 15 10:01:24 2026
Tue Sep 15 16:40:07 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -98,12 +98,12 @@ on the Quartus Prime software download page.
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.04 ;
; Average used ; 1.03 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 3.8% ;
; Processor 2 ; 3.3% ;
+----------------------------+-------------+
@@ -285,18 +285,26 @@ No synchronizer chains to report.
+------------------+-------+------+----------+---------+---------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; COUT[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_CIN[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; COUT[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_CIN[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; out_seg_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; out_seg_1[1] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; out_seg_1[2] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; out_seg_1[3] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; out_seg_1[4] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; out_seg_1[5] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; out_seg_1[6] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; out_seg_1[7] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+----------------------------------------------------------+
@@ -305,71 +313,103 @@ No synchronizer chains to report.
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------+--------------+-----------------+-----------------+
; op[0] ; 1.2 V ; 960 ps ; 960 ps ;
; A[3] ; 1.2 V ; 960 ps ; 960 ps ;
; B[3] ; 1.2 V ; 960 ps ; 960 ps ;
; A[3] ; 1.2 V ; 960 ps ; 960 ps ;
; B[0] ; 1.2 V ; 960 ps ; 960 ps ;
; A[0] ; 1.2 V ; 960 ps ; 960 ps ;
; A[1] ; 1.2 V ; 960 ps ; 960 ps ;
; B[1] ; 1.2 V ; 960 ps ; 960 ps ;
; A[2] ; 1.2 V ; 960 ps ; 960 ps ;
; A[1] ; 1.2 V ; 960 ps ; 960 ps ;
; B[2] ; 1.2 V ; 960 ps ; 960 ps ;
; A[2] ; 1.2 V ; 960 ps ; 960 ps ;
+-------+--------------+-----------------+-----------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; out_seg_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; out_seg_1[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_1[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_1[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
; out_seg_1[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
@@ -398,9 +438,9 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 9 ; 9 ;
; Unconstrained Input Port Paths ; 41 ; 41 ;
; Unconstrained Output Ports ; 6 ; 6 ;
; Unconstrained Output Port Paths ; 41 ; 41 ;
; Unconstrained Input Port Paths ; 105 ; 105 ;
; Unconstrained Output Ports ; 13 ; 13 ;
; Unconstrained Output Port Paths ; 105 ; 105 ;
+---------------------------------+-------+------+
@@ -421,18 +461,25 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+--------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+--------------+---------------------------------------------------------------------------------------+
; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
@@ -452,18 +499,25 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+--------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+--------------+---------------------------------------------------------------------------------------+
; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------+---------------------------------------------------------------------------------------+
+--------------------------+
@@ -472,7 +526,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:01:16 2026
Info: Processing started: Tue Sep 15 16:40:01 2026
Info: Command: quartus_sta A1_Q3 -c asu
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -532,9 +586,9 @@ Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 785 megabytes
Info: Processing ended: Tue Sep 15 10:01:24 2026
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:08
Info: Peak virtual memory: 750 megabytes
Info: Processing ended: Tue Sep 15 16:40:07 2026
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05