TroubleElectrical/FPGA_Uni
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
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commit 9e5fb6f52b
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+1611 -1253
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Quartus/A1_Q2/simulation/questa/lu.svo
+1 -1
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@@ -17,7 +17,7 @@
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
// DATE "09/08/2026 15:42:11"
// DATE "09/15/2026 16:13:58"
//
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672