TroubleElectrical/FPGA_Uni
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
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Quartus/A1_Q2/output_files/lu.map.rpt
+7 -7
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for lu
Tue Sep 8 15:41:25 2026
Tue Sep 15 16:13:14 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -45,7 +45,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 8 15:41:25 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 15 16:13:14 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; lu ;
; Top-level Entity Name ; lu ;
@@ -278,12 +278,12 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 8 15:41:13 2026
Info: Processing started: Tue Sep 15 16:13:03 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q2 -c lu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv
Info (12023): Found entity 1: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 1
Info (12023): Found entity 1: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3
Info (12127): Elaborating entity "lu" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
@@ -294,8 +294,8 @@ Info (21057): Implemented 18 device resources after synthesis - the final resour
Info (21061): Implemented 4 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 439 megabytes
Info: Processing ended: Tue Sep 8 15:41:25 2026
Info: Elapsed time: 00:00:12
Info: Total CPU time (on all processors): 00:00:25
Info: Processing ended: Tue Sep 15 16:13:14 2026
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:26