TroubleElectrical/FPGA_Uni
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
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Quartus/A1_Q2/output_files/lu.flow.rpt
+9 -9
View File
@@ -1,5 +1,5 @@
Flow report for lu
Tue Sep 8 15:42:11 2026
Tue Sep 15 16:13:59 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Sep 8 15:42:11 2026 ;
; Flow Status ; Successful - Tue Sep 15 16:13:59 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; lu ;
; Top-level Entity Name ; lu ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/08/2026 15:41:14 ;
; Start date & time ; 09/15/2026 16:13:04 ;
; Main task ; Compilation ;
; Revision Name ; lu ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 86000517901476.178884607407150 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 268883478169649.178945278308519 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -102,11 +102,11 @@ on the Quartus Prime software download page.
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 422 MB ; 00:00:25 ;
; Fitter ; 00:00:27 ; 1.0 ; 1336 MB ; 00:00:40 ;
; Assembler ; 00:00:06 ; 1.0 ; 513 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 756 MB ; 00:00:06 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:00:51 ; -- ; -- ; 00:01:18 ;
; Fitter ; 00:00:28 ; 1.0 ; 1337 MB ; 00:00:38 ;
; Assembler ; 00:00:06 ; 1.0 ; 513 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 760 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:00:52 ; -- ; -- ; 00:01:14 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+