TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

Browse Source
This commit is contained in:
TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Quartus/A1_Q2/db/lu.tmw_info
+4 -4
View File
@@ -1,7 +1,7 @@
start_full_compilation:s:00:00:59
start_analysis_synthesis:s:00:00:12-start_full_compilation
start_full_compilation:s:00:00:57
start_analysis_synthesis:s:00:00:13-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:30-start_full_compilation
start_fitter:s:00:00:29-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:08-start_full_compilation
start_timing_analyzer:s:00:00:06-start_full_compilation
start_eda_netlist_writer:s:00:00:02-start_full_compilation