Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

Quartus/A1_Q1/seven_seg.sv

@@ -1,3 +1,5 @@
+`ifndef SEVEN_SEG_H_SV
+`define SEVEN_SEG_H_SV
 module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
         always_comb begin
            case (num)
@@ -21,3 +23,4 @@ module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic
            endcase     
         end
 endmodule
+`endif