TroubleElectrical/FPGA_Uni
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
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Quartus/A1_Q1/output_files/seven_seg.map.summary
+1 -1
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@@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Thu Sep 3 16:57:07 2026
Analysis & Synthesis Status : Successful - Tue Sep 15 16:09:45 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : seven_seg
Top-level Entity Name : seven_seg