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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
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Quartus/A1_Q1/output_files/seven_seg.map.rpt
+6 -6
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for seven_seg
Thu Sep 3 16:57:07 2026
Tue Sep 15 16:09:45 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -44,7 +44,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 3 16:57:07 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 15 16:09:45 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; seven_seg ;
; Top-level Entity Name ; seven_seg ;
@@ -269,12 +269,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Thu Sep 3 16:56:55 2026
Info: Processing started: Tue Sep 15 16:09:33 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file seven_seg.sv
Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 1
Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 3
Info (12127): Elaborating entity "seven_seg" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
@@ -285,8 +285,8 @@ Info (21057): Implemented 21 device resources after synthesis - the final resour
Info (21061): Implemented 8 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 436 megabytes
Info: Processing ended: Thu Sep 3 16:57:07 2026
Info: Processing ended: Tue Sep 15 16:09:45 2026
Info: Elapsed time: 00:00:12
Info: Total CPU time (on all processors): 00:00:27
Info: Total CPU time (on all processors): 00:00:24