TroubleElectrical/FPGA_Uni
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
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Quartus/A1_Q1/output_files/seven_seg.flow.rpt
+8 -8
View File
@@ -1,5 +1,5 @@
Flow report for seven_seg
Thu Sep 3 16:57:51 2026
Tue Sep 15 16:10:32 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Thu Sep 3 16:57:51 2026 ;
; Flow Status ; Successful - Tue Sep 15 16:10:32 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; seven_seg ;
; Top-level Entity Name ; seven_seg ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/03/2026 16:56:55 ;
; Start date & time ; 09/15/2026 16:09:34 ;
; Main task ; Compilation ;
; Revision Name ; seven_seg ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 55629860311554.178841861509729 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 268883478169649.178945257408043 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,10 +101,10 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ;
; Fitter ; 00:00:27 ; 1.0 ; 1384 MB ; 00:00:38 ;
; Assembler ; 00:00:05 ; 1.0 ; 525 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 780 MB ; 00:00:05 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ;
; Fitter ; 00:00:28 ; 1.0 ; 1384 MB ; 00:00:40 ;
; Assembler ; 00:00:05 ; 1.0 ; 521 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 788 MB ; 00:00:06 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:00:50 ; -- ; -- ; 00:01:16 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+