TroubleElectrical/FPGA_Uni
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

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TroubleElectrical committed 2026-09-15 16:52:48 +10:00
1 parent 05361dcf70
commit 9e5fb6f52b
179 files changed
+1611 -1253
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Quartus/A1_Q1/output_files/seven_seg.fit.rpt
+6 -6
View File
@@ -1,5 +1,5 @@
Fitter report for seven_seg
Thu Sep 3 16:57:35 2026
Tue Sep 15 16:10:14 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -57,7 +57,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Thu Sep 3 16:57:35 2026 ;
; Fitter Status ; Successful - Tue Sep 15 16:10:14 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; seven_seg ;
; Top-level Entity Name ; seven_seg ;
@@ -152,7 +152,7 @@ on the Quartus Prime software download page.
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.2% ;
; Processor 2 ; 0.3% ;
+----------------------------+-------------+
@@ -1386,8 +1386,8 @@ Info (334004): Delay annotation completed successfully
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 1384 megabytes
Info: Processing ended: Thu Sep 3 16:57:35 2026
Info: Elapsed time: 00:00:27
Info: Total CPU time (on all processors): 00:00:39
Info: Processing ended: Tue Sep 15 16:10:15 2026
Info: Elapsed time: 00:00:29
Info: Total CPU time (on all processors): 00:00:40