Added zero initialization for r0

modules/register_file.sv

@@ -10,6 +10,10 @@ module register_file #(parameter width=5, parameter nregs=32)(
     localparam BW = 2**width;
     logic [2**width-1:0] regs[nregs];
 
+    initial begin
+        regs[0] = {(2**width){1'b0}};
+    end
+
     always_ff @(posedge clk) begin
         if (we & (WA != {(2**width){1'b0}} )) begin
             regs[WA] <= WD;