Switched to used boolean && rather than bitwise & in sign extender

modules/sign_extender.sv

@@ -7,7 +7,7 @@ module sign_extender #(in_width=4, out_width=5)(
     output logic [2**out_width-1:0] ext_val
 );
     logic [0:0] msb;
-    assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
+    assign msb = (val && {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
     always_comb begin
         if (op) begin
             ext_val = { {(2**(out_width-in_width)){msb}}, val};