From 9648db6e77199565e63773f2051767c77631906d Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Tue, 20 Oct 2026 16:02:14 +1100
Subject: [PATCH] Switched to used boolean `&&` rather than bitwise `&` in sign
 extender

---
 modules/sign_extender.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/modules/sign_extender.sv b/modules/sign_extender.sv
index a0e2ef9..1f784ae 100644
--- a/modules/sign_extender.sv
+++ b/modules/sign_extender.sv
@@ -7,7 +7,7 @@ module sign_extender #(in_width=4, out_width=5)(
     output logic [2**out_width-1:0] ext_val
 );
     logic [0:0] msb;
-    assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
+    assign msb = (val && {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
     always_comb begin
         if (op) begin
             ext_val = { {(2**(out_width-in_width)){msb}}, val};