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Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

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TroubleElectrical committed 2026-09-15 19:43:28 +10:00
1 parent 9d0c7011ce
commit 9583abd307
75 files changed
+1510 -3407
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Quartus/A1_Q4/alu.qws
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Quartus/A1_Q4/db/alu.pplq.rdb
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Quartus/A1_Q4/db/A1_Q4.quiproj.2570.rdr.flock → Quartus/A1_Q5/db/A1_Q5.quiproj.2570.rdr.flock
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Quartus/A1_Q5/db/prev_cmp_A1_Q5.qmsg
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@@ -0,0 +1,37 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465036231 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465036232 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:37:16 2026 " "Processing started: Tue Sep 15 19:37:16 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465036232 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465036232 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465036232 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789465036549 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789465036550 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789465046004 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465046004 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789465046140 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789465046905 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789465047246 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789465047246 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789465047275 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789465047275 ""} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Implemented 32 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789465047275 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789465047275 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465047282 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:37:27 2026 " "Processing ended: Tue Sep 15 19:37:27 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465047282 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465047282 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465047282 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465047282 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1789465048807 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465048808 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:37:28 2026 " "Processing started: Tue Sep 15 19:37:28 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465048808 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1789465048808 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_fit --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1789465048808 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1789465048858 ""}
{ "Info" "0" "" "Project = A1_Q5" { } { } 0 0 "Project = A1_Q5" 0 0 "Fitter" 0 0 1789465048859 ""}
{ "Info" "0" "" "Revision = shifter" { } { } 0 0 "Revision = shifter" 0 0 "Fitter" 0 0 1789465048859 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789465049047 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789465049047 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789465049052 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465049129 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465049129 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789465049534 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789465049561 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789465049613 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 17 " "No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789465049868 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789465056595 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465056643 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789465056645 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465056646 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465056646 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789465056646 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789465056646 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789465056646 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789465056647 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789465056647 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789465056647 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465056666 ""}
Quartus/A1_Q5/db/shifter.(0).cnf.cdb
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Quartus/A1_Q5/db/shifter.(0).cnf.hdb
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Quartus/A1_Q5/db/shifter.asm.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430803604 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430803605 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:06:43 2026 " "Processing started: Tue Sep 15 10:06:43 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430803605 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789430803605 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789430803605 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789430804252 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789430808582 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "518 " "Peak virtual memory: 518 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430808780 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:48 2026 " "Processing ended: Tue Sep 15 10:06:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430808780 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430808780 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430808780 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789430808780 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465167736 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465167737 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:27 2026 " "Processing started: Tue Sep 15 19:39:27 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465167737 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789465167737 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789465167737 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789465168580 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789465173536 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "507 " "Peak virtual memory: 507 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:33 2026 " "Processing ended: Tue Sep 15 19:39:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789465173727 ""}
Quartus/A1_Q5/db/shifter.asm.rdb
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Quartus/A1_Q5/db/shifter.cmp.bpm
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Quartus/A1_Q5/db/shifter.cmp.cdb
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Quartus/A1_Q5/db/shifter.cmp.hdb
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Quartus/A1_Q5/db/shifter.cmp.idb
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Quartus/A1_Q5/db/shifter.cmp.logdb
+23 -36
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v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
@@ -29,42 +29,29 @@ IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
IO_RULES_MATRIX,Total Pass,0;0;0;0;0;30;0;0;0;0;0;0;0;8;0;0;0;0;8;0;0;0;0;8;0;30;30;0,
IO_RULES_MATRIX,Total Pass,0;15;15;0;0;17;15;0;0;0;0;0;0;4;0;0;0;0;4;0;0;0;0;4;0;17;17;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,30;30;30;30;30;0;30;30;30;30;30;30;30;22;30;30;30;30;22;30;30;30;30;22;30;0;0;30,
IO_RULES_MATRIX,Total Inapplicable,17;2;2;17;17;0;2;17;17;17;17;17;17;13;17;17;17;17;13;17;17;17;17;13;17;0;0;17,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,OUT_1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,C[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,28,
IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19,
Quartus/A1_Q5/db/shifter.cmp.rdb
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Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd
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Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd
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Quartus/A1_Q5/db/shifter.db_info
+1 -1
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@@ -1,3 +1,3 @@
Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Version_Index = 604268800
Creation_Time = Tue Sep 15 10:05:43 2026
Creation_Time = Tue Sep 15 19:14:26 2026
Quartus/A1_Q5/db/shifter.eda.qmsg
+6 -6
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@@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430816693 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430816694 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:06:56 2026 " "Processing started: Tue Sep 15 10:06:56 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430816694 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430816694 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430816694 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789430817425 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "shifter.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/ simulation " "Generated file shifter.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789430817488 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430817524 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:57 2026 " "Processing ended: Tue Sep 15 10:06:57 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430817524 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430817524 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430817524 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430817524 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465182961 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465182961 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:42 2026 " "Processing started: Tue Sep 15 19:39:42 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465182961 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465182961 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465182961 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789465183869 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "shifter.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/ simulation " "Generated file shifter.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789465183961 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "666 " "Peak virtual memory: 666 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:44 2026 " "Processing ended: Tue Sep 15 19:39:44 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465184019 ""}
Quartus/A1_Q5/db/shifter.fit.qmsg
+45 -44
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@@ -1,44 +1,45 @@
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789430770929 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789430770930 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789430770935 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430771006 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430771006 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789430771421 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789430771454 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789430771502 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "30 30 " "No exact pin location assignment(s) for 30 pins of 30 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789430771778 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789430778347 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430778461 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789430778464 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430778464 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430778464 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789430778465 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789430778465 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789430778465 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789430778465 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789430778465 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789430778465 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430778484 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789430784343 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789430784344 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789430784344 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789430784345 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789430784346 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789430784346 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789430784347 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789430784351 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789430784396 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:04 " "Fitter placement preparation operations ending: elapsed time is 00:00:04" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430788050 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789430789723 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789430790074 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430790074 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789430790662 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y24 X68_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36"} { { 12 { 0 ""} 57 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789430796160 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789430796160 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789430796398 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789430796398 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789430796398 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430796401 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789430797416 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430797458 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430797888 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430797888 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430798495 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430801226 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1347 " "Peak virtual memory: 1347 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430802055 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:42 2026 " "Processing ended: Tue Sep 15 10:06:42 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430802055 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430802055 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430802055 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789430802055 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789465130214 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789465130214 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789465130221 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465130300 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465130300 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789465130803 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789465130840 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789465130902 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 17 " "No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789465131227 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789465138495 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465138551 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789465138553 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465138554 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465138554 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789465138554 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789465138554 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789465138554 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789465138555 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789465138555 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789465138555 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465138575 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789465145753 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789465145754 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789465145754 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789465145755 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789465145756 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789465145756 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789465145756 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789465145760 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789465145841 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465147357 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789465148341 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789465148587 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465148587 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789465149821 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789465158188 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789465158188 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789465158582 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789465158582 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789465158582 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465158584 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789465160095 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465160145 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465160585 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465160585 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465161535 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465164913 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789465165221 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1379 " "Peak virtual memory: 1379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:25 2026 " "Processing ended: Tue Sep 15 19:39:25 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:36 " "Elapsed time: 00:00:36" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:50 " "Total CPU time (on all processors): 00:00:50" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789465165869 ""}
Quartus/A1_Q5/db/shifter.hier_info
+56 -119
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@@ -3,132 +3,69 @@ op[0] => Mux0.IN8
op[0] => Mux1.IN8
op[0] => Mux2.IN8
op[0] => Mux3.IN8
op[0] => Mux4.IN8
op[0] => Mux5.IN8
op[0] => Mux6.IN8
op[0] => Mux7.IN8
op[1] => Mux0.IN7
op[1] => Mux1.IN7
op[1] => Mux2.IN7
op[1] => Mux3.IN7
op[1] => Mux4.IN7
op[1] => Mux5.IN7
op[1] => Mux6.IN7
op[1] => Mux7.IN7
op[2] => Mux0.IN6
op[2] => Mux1.IN6
op[2] => Mux2.IN6
op[2] => Mux3.IN6
op[2] => Mux4.IN6
op[2] => Mux5.IN6
op[2] => Mux6.IN6
op[2] => Mux7.IN6
A[0] => ShiftLeft0.IN8
A[0] => ShiftRight0.IN8
A[0] => ShiftRight1.IN8
A[0] => ShiftLeft1.IN8
A[0] => ShiftRight2.IN8
A[0] => ShiftRight3.IN8
A[0] => Mux7.IN9
A[0] => Mux7.IN10
A[1] => ShiftLeft0.IN7
A[1] => ShiftRight0.IN7
A[1] => ShiftRight1.IN7
A[1] => ShiftLeft1.IN7
A[1] => ShiftRight2.IN7
A[1] => ShiftRight3.IN7
A[1] => Mux6.IN9
A[1] => Mux6.IN10
A[2] => ShiftLeft0.IN6
A[2] => ShiftRight0.IN6
A[2] => ShiftRight1.IN6
A[2] => ShiftLeft1.IN6
A[2] => ShiftRight2.IN6
A[2] => ShiftRight3.IN6
A[2] => Mux5.IN9
A[2] => Mux5.IN10
A[3] => ShiftLeft0.IN5
A[3] => ShiftRight0.IN5
A[3] => ShiftRight1.IN5
A[3] => ShiftLeft1.IN5
A[3] => ShiftRight2.IN5
A[3] => ShiftRight3.IN5
A[3] => Mux4.IN9
A[3] => Mux4.IN10
A[4] => ShiftLeft0.IN4
A[4] => ShiftRight0.IN4
A[4] => ShiftRight1.IN4
A[4] => ShiftLeft1.IN4
A[4] => ShiftRight2.IN4
A[4] => ShiftRight3.IN4
A[4] => Mux3.IN9
A[4] => Mux3.IN10
A[5] => ShiftLeft0.IN3
A[5] => ShiftRight0.IN3
A[5] => ShiftRight1.IN3
A[5] => ShiftLeft1.IN3
A[5] => ShiftRight2.IN3
A[5] => ShiftRight3.IN3
A[5] => Mux2.IN9
A[5] => Mux2.IN10
A[6] => ShiftLeft0.IN2
A[6] => ShiftRight0.IN2
A[6] => ShiftRight1.IN2
A[6] => ShiftLeft1.IN2
A[6] => ShiftRight2.IN2
A[6] => ShiftRight3.IN2
A[6] => Mux1.IN9
A[6] => Mux1.IN10
A[7] => ShiftLeft0.IN1
A[7] => ShiftRight0.IN1
A[7] => ShiftRight1.IN0
A[7] => ShiftRight1.IN1
A[7] => ShiftLeft1.IN1
A[7] => ShiftRight2.IN1
A[7] => ShiftRight3.IN0
A[7] => ShiftRight3.IN1
A[7] => Mux0.IN9
A[7] => Mux0.IN10
C[0] => ShiftLeft0.IN16
C[0] => ShiftRight0.IN16
C[0] => ShiftRight1.IN16
C[1] => ShiftLeft0.IN15
C[1] => ShiftRight0.IN15
C[1] => ShiftRight1.IN15
C[2] => ShiftLeft0.IN14
C[2] => ShiftRight0.IN14
C[2] => ShiftRight1.IN14
C[3] => ShiftLeft0.IN13
C[3] => ShiftRight0.IN13
C[3] => ShiftRight1.IN13
C[4] => ShiftLeft0.IN12
C[4] => ShiftRight0.IN12
C[4] => ShiftRight1.IN12
C[5] => ShiftLeft0.IN11
C[5] => ShiftRight0.IN11
C[5] => ShiftRight1.IN11
C[6] => ShiftLeft0.IN10
C[6] => ShiftRight0.IN10
C[6] => ShiftRight1.IN10
C[7] => ShiftLeft0.IN9
C[7] => ShiftRight0.IN9
C[7] => ShiftRight1.IN9
B[0] => ShiftLeft1.IN11
B[0] => ShiftRight2.IN11
B[0] => ShiftRight3.IN11
B[1] => ShiftLeft1.IN10
B[1] => ShiftRight2.IN10
B[1] => ShiftRight3.IN10
B[2] => ShiftLeft1.IN9
B[2] => ShiftRight2.IN9
B[2] => ShiftRight3.IN9
OUT_1[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
A[0] => ShiftLeft0.IN4
A[0] => ShiftRight0.IN4
A[0] => ShiftRight1.IN4
A[0] => ShiftLeft1.IN4
A[0] => ShiftRight2.IN4
A[0] => ShiftRight3.IN4
A[0] => Mux3.IN9
A[0] => Mux3.IN10
A[1] => ShiftLeft0.IN3
A[1] => ShiftRight0.IN3
A[1] => ShiftRight1.IN3
A[1] => ShiftLeft1.IN3
A[1] => ShiftRight2.IN3
A[1] => ShiftRight3.IN3
A[1] => Mux2.IN9
A[1] => Mux2.IN10
A[2] => ShiftLeft0.IN2
A[2] => ShiftRight0.IN2
A[2] => ShiftRight1.IN2
A[2] => ShiftLeft1.IN2
A[2] => ShiftRight2.IN2
A[2] => ShiftRight3.IN2
A[2] => Mux1.IN9
A[2] => Mux1.IN10
A[3] => ShiftLeft0.IN1
A[3] => ShiftRight0.IN1
A[3] => ShiftRight1.IN0
A[3] => ShiftRight1.IN1
A[3] => ShiftLeft1.IN1
A[3] => ShiftRight2.IN1
A[3] => ShiftRight3.IN0
A[3] => ShiftRight3.IN1
A[3] => Mux0.IN9
A[3] => Mux0.IN10
B[0] => ShiftLeft1.IN8
B[0] => ShiftRight2.IN8
B[0] => ShiftRight3.IN8
B[1] => ShiftLeft1.IN7
B[1] => ShiftRight2.IN7
B[1] => ShiftRight3.IN7
B[2] => ShiftLeft1.IN6
B[2] => ShiftRight2.IN6
B[2] => ShiftRight3.IN6
B[3] => ShiftLeft1.IN5
B[3] => ShiftRight2.IN5
B[3] => ShiftRight3.IN5
C[0] => ShiftLeft0.IN6
C[0] => ShiftRight0.IN6
C[0] => ShiftRight1.IN6
C[1] => ShiftLeft0.IN5
C[1] => ShiftRight0.IN5
C[1] => ShiftRight1.IN5
OUT_1[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
Quartus/A1_Q5/db/shifter.hif
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Quartus/A1_Q5/db/shifter.map.bpm
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Quartus/A1_Q5/db/shifter.map.qmsg
+11 -11
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@@ -1,11 +1,11 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430758021 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430758022 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:05:57 2026 " "Processing started: Tue Sep 15 10:05:57 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430758022 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430758022 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430758022 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789430758320 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789430758321 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430767297 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430767297 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789430767432 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789430768701 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789430769122 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430769122 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "115 " "Implemented 115 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789430769167 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789430769167 ""} { "Info" "ICUT_CUT_TM_LCELLS" "85 " "Implemented 85 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789430769167 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789430769167 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430769173 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:09 2026 " "Processing ended: Tue Sep 15 10:06:09 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430769173 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430769173 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430769173 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430769173 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465117698 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465117698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:38:37 2026 " "Processing started: Tue Sep 15 19:38:37 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465117698 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465117698 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465117699 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789465118007 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789465118007 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789465126919 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465126919 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789465127060 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789465127834 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789465128194 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789465128194 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789465128236 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789465128236 ""} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Implemented 32 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789465128236 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789465128236 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:38:48 2026 " "Processing ended: Tue Sep 15 19:38:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465128243 ""}
Quartus/A1_Q5/db/shifter.map.rdb
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430810263 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430810263 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:06:49 2026 " "Processing started: Tue Sep 15 10:06:49 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430810263 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430810263 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q5 -c shifter " "Command: quartus_sta A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430810264 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789430810318 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789430810787 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789430810787 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430810861 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430810861 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789430811445 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430811446 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430811446 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430811447 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430811447 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430811447 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789430811448 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789430811452 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430811453 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811454 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811458 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811459 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811459 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811460 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811461 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430811463 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430811501 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430812500 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430812608 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430812608 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430812609 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430812609 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812610 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812611 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812612 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812613 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812614 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812614 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430812616 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430812867 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430813469 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430813518 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430813518 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430813518 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430813519 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813520 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813521 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813521 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813522 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813523 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430813525 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430813673 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430813673 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430813673 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430813674 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813675 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813676 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813676 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813677 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813678 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430815121 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430815122 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "750 " "Peak virtual memory: 750 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430815157 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:55 2026 " "Processing ended: Tue Sep 15 10:06:55 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430815157 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430815157 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430815157 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789430815157 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465175261 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465175262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:34 2026 " "Processing started: Tue Sep 15 19:39:34 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465175262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465175262 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q5 -c shifter " "Command: quartus_sta A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465175262 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789465175322 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789465175845 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789465175845 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465175922 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465175922 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789465176538 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465176538 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465176539 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465176539 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465176539 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465176540 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789465176540 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789465176545 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465176545 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176547 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176550 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176551 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176552 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176553 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176553 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465176556 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465176606 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465178030 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465178130 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178131 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178133 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178134 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178135 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178136 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178136 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465178138 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465178417 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465179197 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465179249 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179251 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179252 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179253 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179254 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179254 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465179256 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465179414 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179415 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179416 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179417 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179418 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179418 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465180905 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465180906 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "777 " "Peak virtual memory: 777 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:40 2026 " "Processing ended: Tue Sep 15 19:39:40 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789465180932 ""}
Quartus/A1_Q5/db/shifter.sta.rdb
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Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb
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Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb
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Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb
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Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb
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Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb
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Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb
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Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb
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Quartus/A1_Q5/db/shifter.tmw_info
+5 -5
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@@ -1,7 +1,7 @@
start_full_compilation:s:00:01:02
start_analysis_synthesis:s:00:00:13-start_full_compilation
start_full_compilation:s:00:01:08
start_analysis_synthesis:s:00:00:12-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:33-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:06-start_full_compilation
start_fitter:s:00:00:38-start_full_compilation
start_assembler:s:00:00:08-start_full_compilation
start_timing_analyzer:s:00:00:07-start_full_compilation
start_eda_netlist_writer:s:00:00:03-start_full_compilation
Quartus/A1_Q5/db/shifter.vpr.ammdb
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Quartus/A1_Q5/db/shifter_partition_pins.json
+6 -58
View File
@@ -20,29 +20,13 @@
"strict" : false
},
{
"name" : "OUT_1[4]",
"strict" : false
},
{
"name" : "OUT_1[5]",
"strict" : false
},
{
"name" : "OUT_1[6]",
"strict" : false
},
{
"name" : "OUT_1[7]",
"name" : "A[0]",
"strict" : false
},
{
"name" : "op[0]",
"strict" : false
},
{
"name" : "A[0]",
"strict" : false
},
{
"name" : "op[2]",
"strict" : false
@@ -52,31 +36,7 @@
"strict" : false
},
{
"name" : "C[2]",
"strict" : false
},
{
"name" : "C[3]",
"strict" : false
},
{
"name" : "C[4]",
"strict" : false
},
{
"name" : "C[5]",
"strict" : false
},
{
"name" : "C[6]",
"strict" : false
},
{
"name" : "C[7]",
"strict" : false
},
{
"name" : "A[7]",
"name" : "C[1]",
"strict" : false
},
{
@@ -84,19 +44,19 @@
"strict" : false
},
{
"name" : "C[1]",
"name" : "B[2]",
"strict" : false
},
{
"name" : "A[6]",
"name" : "B[3]",
"strict" : false
},
{
"name" : "A[4]",
"name" : "B[1]",
"strict" : false
},
{
"name" : "A[5]",
"name" : "B[0]",
"strict" : false
},
{
@@ -110,18 +70,6 @@
{
"name" : "A[3]",
"strict" : false
},
{
"name" : "B[2]",
"strict" : false
},
{
"name" : "B[0]",
"strict" : false
},
{
"name" : "B[1]",
"strict" : false
}
]
}
Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.dpi
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb
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Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrs.cdb
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Quartus/A1_Q5/output_files/shifter.asm.rpt
+9 -9
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@@ -1,5 +1,5 @@
Assembler report for shifter
Tue Sep 15 10:06:48 2026
Tue Sep 15 19:39:33 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Sep 15 10:06:48 2026 ;
; Assembler Status ; Successful - Tue Sep 15 19:39:33 2026 ;
; Revision Name ; shifter ;
; Top-level Entity Name ; shifter ;
; Family ; Cyclone V ;
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
+----------------+----------------------+
; Option ; Setting ;
+----------------+----------------------+
; JTAG usercode ; 0x007990C3 ;
; Checksum ; 0x007990C3 ;
; JTAG usercode ; 0x007896D6 ;
; Checksum ; 0x007896D6 ;
+----------------+----------------------+
@@ -78,14 +78,14 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:06:43 2026
Info: Processing started: Tue Sep 15 19:39:27 2026
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 518 megabytes
Info: Processing ended: Tue Sep 15 10:06:48 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
Info: Peak virtual memory: 507 megabytes
Info: Processing ended: Tue Sep 15 19:39:33 2026
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:06
Quartus/A1_Q5/output_files/shifter.done
+1 -1
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@@ -1 +1 @@
Tue Sep 15 10:06:58 2026
Tue Sep 15 19:39:44 2026
Quartus/A1_Q5/output_files/shifter.eda.rpt
+6 -6
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@@ -1,5 +1,5 @@
EDA Netlist Writer report for shifter
Tue Sep 15 10:06:57 2026
Tue Sep 15 19:39:43 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:06:57 2026 ;
; EDA Netlist Writer Status ; Successful - Tue Sep 15 19:39:43 2026 ;
; Revision Name ; shifter ;
; Top-level Entity Name ; shifter ;
; Family ; Cyclone V ;
@@ -81,14 +81,14 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:06:56 2026
Info: Processing started: Tue Sep 15 19:39:42 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file shifter.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 670 megabytes
Info: Processing ended: Tue Sep 15 10:06:57 2026
Info: Elapsed time: 00:00:01
Info: Peak virtual memory: 666 megabytes
Info: Processing ended: Tue Sep 15 19:39:44 2026
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Quartus/A1_Q5/output_files/shifter.fit.rpt
+345 -595
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File diff suppressed because it is too large. Load diff
Quartus/A1_Q5/output_files/shifter.fit.smsg
+6
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@@ -0,0 +1,6 @@
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
Quartus/A1_Q5/output_files/shifter.fit.summary
+3 -3
View File
@@ -1,13 +1,13 @@
Fitter Status : Successful - Tue Sep 15 10:06:41 2026
Fitter Status : Successful - Tue Sep 15 19:39:25 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : shifter
Top-level Entity Name : shifter
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 48 / 29,080 ( < 1 % )
Logic utilization (in ALMs) : 21 / 29,080 ( < 1 % )
Total registers : 0
Total pins : 30 / 364 ( 8 % )
Total pins : 17 / 364 ( 5 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )
Quartus/A1_Q5/output_files/shifter.flow.rpt
+12 -12
View File
@@ -1,5 +1,5 @@
Flow report for shifter
Tue Sep 15 10:06:57 2026
Tue Sep 15 19:39:43 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,16 +41,16 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Sep 15 10:06:57 2026 ;
; Flow Status ; Successful - Tue Sep 15 19:39:43 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; shifter ;
; Top-level Entity Name ; shifter ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 48 / 29,080 ( < 1 % ) ;
; Logic utilization (in ALMs) ; 21 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 30 / 364 ( 8 % ) ;
; Total pins ; 17 / 364 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/15/2026 10:05:58 ;
; Start date & time ; 09/15/2026 19:38:37 ;
; Main task ; Compilation ;
; Revision Name ; shifter ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 253029099468756.178943075805931 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 268883478169649.178946511707335 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 413 MB ; 00:00:25 ;
; Fitter ; 00:00:31 ; 1.0 ; 1347 MB ; 00:00:48 ;
; Assembler ; 00:00:05 ; 1.0 ; 518 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 750 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
; Total ; 00:00:55 ; -- ; -- ; 00:01:24 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ;
; Fitter ; 00:00:36 ; 1.0 ; 1379 MB ; 00:00:50 ;
; Assembler ; 00:00:06 ; 1.0 ; 507 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 777 MB ; 00:00:06 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ;
; Total ; 00:01:00 ; -- ; -- ; 00:01:27 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
Quartus/A1_Q5/output_files/shifter.map.rpt
+45 -58
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for shifter
Tue Sep 15 10:06:09 2026
Tue Sep 15 19:38:48 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -14,11 +14,10 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Multiplexer Restructuring Statistics (Restructuring Performed)
10. Parameter Settings for User Entity Instance: Top-level Entity: |shifter
11. Post-Synthesis Netlist Statistics for Top Partition
12. Elapsed Time Per Partition
13. Analysis & Synthesis Messages
9. Parameter Settings for User Entity Instance: Top-level Entity: |shifter
10. Post-Synthesis Netlist Statistics for Top Partition
11. Elapsed Time Per Partition
12. Analysis & Synthesis Messages
@@ -45,14 +44,14 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:06:09 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:38:48 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; shifter ;
; Top-level Entity Name ; shifter ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 0 ;
; Total pins ; 30 ;
; Total pins ; 17 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; Total DSP Blocks ; 0 ;
@@ -177,31 +176,31 @@ on the Quartus Prime software download page.
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+
+-----------------------------------------------------------+
+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------------+
+---------------------------------------------+------------+
; Resource ; Usage ;
+---------------------------------------------+-------------+
; Estimate of Logic utilization (ALMs needed) ; 56 ;
+---------------------------------------------+------------+
; Estimate of Logic utilization (ALMs needed) ; 23 ;
; ; ;
; Combinational ALUT usage for logic ; 85 ;
; -- 7 input functions ; 3 ;
; -- 6 input functions ; 23 ;
; -- 5 input functions ; 41 ;
; -- 4 input functions ; 9 ;
; -- <=3 input functions ; 9 ;
; Combinational ALUT usage for logic ; 32 ;
; -- 7 input functions ; 1 ;
; -- 6 input functions ; 13 ;
; -- 5 input functions ; 5 ;
; -- 4 input functions ; 6 ;
; -- <=3 input functions ; 7 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 30 ;
; I/O pins ; 17 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; op[2]~input ;
; Maximum fan-out ; 29 ;
; Total fan-out ; 462 ;
; Average fan-out ; 3.19 ;
+---------------------------------------------+-------------+
; Maximum fan-out node ; A[3]~input ;
; Maximum fan-out ; 15 ;
; Total fan-out ; 173 ;
; Average fan-out ; 2.62 ;
+---------------------------------------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -209,7 +208,7 @@ on the Quartus Prime software download page.
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; |shifter ; 85 (85) ; 0 (0) ; 0 ; 0 ; 30 ; 0 ; |shifter ; shifter ; work ;
; |shifter ; 32 (32) ; 0 (0) ; 0 ; 0 ; 17 ; 0 ; |shifter ; shifter ; work ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -229,24 +228,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |shifter|ShiftLeft0 ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |shifter|ShiftRight2 ;
; 23:1 ; 2 bits ; 30 LEs ; 20 LEs ; 10 LEs ; No ; |shifter|Mux1 ;
; 21:1 ; 2 bits ; 28 LEs ; 20 LEs ; 8 LEs ; No ; |shifter|Mux5 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |shifter ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------+
; width ; 8 ; Signed Integer ;
; width ; 2 ; Signed Integer ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
@@ -256,19 +243,19 @@ Note: In order to hide this table in the UI and the text report file, please set
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_lcell_comb ; 85 ;
; extend ; 3 ;
; 7 data inputs ; 3 ;
; normal ; 82 ;
; arriav_lcell_comb ; 32 ;
; extend ; 1 ;
; 7 data inputs ; 1 ;
; normal ; 31 ;
; 2 data inputs ; 3 ;
; 3 data inputs ; 6 ;
; 4 data inputs ; 9 ;
; 5 data inputs ; 41 ;
; 6 data inputs ; 23 ;
; boundary_port ; 30 ;
; 3 data inputs ; 4 ;
; 4 data inputs ; 6 ;
; 5 data inputs ; 5 ;
; 6 data inputs ; 13 ;
; boundary_port ; 17 ;
; ; ;
; Max LUT depth ; 4.00 ;
; Average LUT depth ; 3.75 ;
; Average LUT depth ; 3.13 ;
+-----------------------+-----------------------------+
@@ -277,7 +264,7 @@ Note: In order to hide this table in the UI and the text report file, please set
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:01 ;
; Top ; 00:00:00 ;
+----------------+--------------+
@@ -287,7 +274,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:05:57 2026
Info: Processing started: Tue Sep 15 19:38:37 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
@@ -297,14 +284,14 @@ Info (12127): Elaborating entity "shifter" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 115 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 22 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 85 logic cells
Info (21057): Implemented 49 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 13 input pins
Info (21059): Implemented 4 output pins
Info (21061): Implemented 32 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 430 megabytes
Info: Processing ended: Tue Sep 15 10:06:09 2026
Info: Elapsed time: 00:00:12
Info: Total CPU time (on all processors): 00:00:25
Info: Peak virtual memory: 433 megabytes
Info: Processing ended: Tue Sep 15 19:38:48 2026
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:24
Quartus/A1_Q5/output_files/shifter.map.summary
+2 -2
View File
@@ -1,11 +1,11 @@
Analysis & Synthesis Status : Successful - Tue Sep 15 10:06:09 2026
Analysis & Synthesis Status : Successful - Tue Sep 15 19:38:48 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : shifter
Top-level Entity Name : shifter
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 30
Total pins : 17
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Quartus/A1_Q5/output_files/shifter.pin
+63 -63
View File
@@ -29,8 +29,8 @@
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 3A: 2.5V
-- Bank 3B: 2.5V
-- Bank 4A: 2.5V
-- Bank 3B: 1.2V
-- Bank 4A: 1.2V
-- Bank 5A: 2.5V
-- Bank 5B: 2.5V
-- Bank 6A: 2.5V
@@ -109,7 +109,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A :
VCC_AUX : AA8 : power : : 2.5V : :
VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCIO3B : AA10 : power : : 2.5V : 3B :
VCCIO3B : AA10 : power : : 1.2V : 3B :
VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A :
NC : AA12 : : : : :
VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A :
@@ -119,13 +119,13 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : :
VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A :
VCCIO4A : AA20 : power : : 2.5V : 4A :
VCCIO4A : AA20 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5B :
GND : AA25 : gnd : : : :
B[2] : AA26 : input : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
GND : AB1 : : : : B0L :
GND : AB2 : : : : B0L :
GND : AB3 : gnd : : : :
@@ -138,7 +138,7 @@ VCCPD3A : AB9 : power : : 2.5V
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
VCCIO4A : AB13 : power : : 2.5V : 4A :
VCCIO4A : AB13 : power : : 1.2V : 4A :
VCC_AUX : AB14 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A :
@@ -151,7 +151,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : :
VCCIO5A : AB23 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B :
A[3] : AB26 : input : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5B :
GND : AC1 : gnd : : : :
GND : AC2 : gnd : : : :
GXB_NC : AC3 : : : : B0L :
@@ -159,15 +159,15 @@ GXB_NC : AC4 : : :
GND : AC5 : gnd : : : :
VCCIO3A : AC6 : power : : 2.5V : 3A :
VREFB3AN0 : AC7 : power : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B :
B[1] : AC8 : input : 1.2 V : : 3B : Y
C[0] : AC9 : input : 1.2 V : : 3B : Y
op[0] : AC10 : input : 1.2 V : : 3B : Y
GND : AC11 : gnd : : : :
VREFB3BN0 : AC12 : power : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A :
VCCIO4A : AC16 : power : : 2.5V : 4A :
VCCIO4A : AC16 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A :
@@ -186,17 +186,17 @@ AS_DATA1, DATA1 : AD5 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B :
VCCIO3B : AD9 : power : : 2.5V : 3B :
VCCIO3B : AD9 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 4A :
B[0] : AD13 : input : 1.2 V : : 4A : Y
GND : AD14 : gnd : : : :
VREFB4AN0 : AD15 : power : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A :
VCCIO4A : AD19 : power : : 2.5V : 4A :
VCCIO4A : AD19 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A :
@@ -209,23 +209,23 @@ GND : AE2 : gnd : :
GXB_NC : AE3 : : : : B0L :
GXB_NC : AE4 : : : : B0L :
GND : AE5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3B :
B[3] : AE6 : input : 1.2 V : : 3B : N
GND : AE7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A :
C[1] : AE10 : input : 1.2 V : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A :
VCCIO4A : AE12 : power : : 2.5V : 4A :
VCCIO4A : AE12 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
GND : AE17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
op[2] : AE19 : input : 1.2 V : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A :
VCCIO4A : AE22 : power : : 2.5V : 4A :
VCCIO4A : AE22 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A :
@@ -234,7 +234,7 @@ GND : AF2 : gnd : :
GND : AF3 : gnd : : : :
GND : AF4 : gnd : : : :
AS_DATA0, ASDO, DATA0 : AF5 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B :
B[2] : AF6 : input : 1.2 V : : 3B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B :
@@ -243,7 +243,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A :
VCCIO4A : AF15 : power : : 2.5V : 4A :
VCCIO4A : AF15 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
@@ -331,7 +331,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : :
GND : D23 : : : : 7A :
GND : D24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 6A :
OUT_1[2] : D26 : output : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6A :
GND : E1 : gnd : : : :
GND : E2 : gnd : : : :
NC : E3 : : : : :
@@ -363,8 +363,8 @@ NC : F2 : : :
GND : F3 : gnd : : : :
GND : F4 : gnd : : : :
nCONFIG : F5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A :
OUT_1[1] : F6 : output : 2.5 V : : 8A : Y
OUT_1[0] : F7 : output : 2.5 V : : 8A : Y
VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A :
GND : F10 : gnd : : : :
@@ -383,14 +383,14 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6A :
VCCIO6A : F25 : power : : 2.5V : 6A :
OUT_1[0] : F26 : output : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
GND : G1 : gnd : : : :
GND : G2 : gnd : : : :
NC : G3 : : : : :
NC : G4 : : : : :
GND : G5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
OUT_1[2] : G6 : output : 2.5 V : : 8A : Y
OUT_1[3] : G7 : output : 2.5 V : : 8A : Y
VCCIO8A : G8 : power : : 2.5V : 8A :
VCC_AUX : G9 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
@@ -407,9 +407,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : :
VCCA_FPLL : G21 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6A :
GND : G23 : gnd : : : :
C[5] : G24 : input : 2.5 V : : 6A : N
C[3] : G25 : input : 2.5 V : : 6A : N
C[1] : G26 : input : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
NC : H1 : : : : :
NC : H2 : : : : :
GND : H3 : gnd : : : :
@@ -434,7 +434,7 @@ VCCIO6A : H21 : power : : 2.5V
RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
A[2] : H25 : input : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
GND : H26 : gnd : : : :
GND : J1 : gnd : : : :
GND : J2 : gnd : : : :
@@ -460,8 +460,8 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : :
VCCPD6A : J22 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
VCCIO6A : J24 : power : : 2.5V : 6A :
C[4] : J25 : input : 2.5 V : : 6A : N
op[1] : J26 : input : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
GXB_NC : K1 : : : : B1L :
GXB_NC : K2 : : : : B1L :
GND : K3 : gnd : : : :
@@ -534,11 +534,11 @@ GND : M17 : gnd : :
VCC : M18 : power : : 1.1V : :
GND : M19 : gnd : : : :
VCC : M20 : power : : 1.1V : :
C[7] : M21 : input : 2.5 V : : 6A : N
OUT_1[7] : M22 : output : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
VCCIO6A : M23 : power : : 2.5V : 6A :
B[1] : M24 : input : 2.5 V : : 6A : N
OUT_1[5] : M25 : output : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
GND : N1 : gnd : : : :
GND : N2 : gnd : : : :
@@ -559,12 +559,12 @@ GND : N16 : gnd : :
VCC : N17 : power : : 1.1V : :
GND : N18 : gnd : : : :
VCC : N19 : power : : 1.1V : :
OUT_1[4] : N20 : output : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6A :
GND : N21 : gnd : : : :
VCCPD5B : N22 : power : : 2.5V : 5B :
OUT_1[1] : N23 : output : 2.5 V : : 6A : N
A[0] : N24 : input : 2.5 V : : 6A : N
A[7] : N25 : input : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 5B :
VCCIO5B : N26 : power : : 2.5V : 5B :
GXB_NC : P1 : : : : B1L :
GXB_NC : P2 : : : : B1L :
@@ -576,8 +576,8 @@ GND : P7 : gnd : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3A :
GND : P9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3B :
A[0] : P11 : input : 1.2 V : : 3B : Y
A[1] : P12 : input : 1.2 V : : 3B : Y
GND : P13 : gnd : : : :
VCC : P14 : power : : 1.1V : :
GND : P15 : gnd : : : :
@@ -586,12 +586,12 @@ GND : P17 : gnd : :
VCC : P18 : power : : 1.1V : :
GND : P19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5B :
C[2] : P21 : input : 2.5 V : : 5B : N
op[2] : P22 : input : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P23 : : : : 5B :
GND : P24 : gnd : : : :
VREFB5BN0 : P25 : power : : : 5B :
op[0] : P26 : input : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 5B :
GND : R1 : gnd : : : :
GND : R2 : gnd : : : :
VCCH_GXBL : R3 : power : : 2.5V : :
@@ -611,13 +611,13 @@ GND : R16 : gnd : :
VCC : R17 : power : : 1.1V : :
GND : R18 : gnd : : : :
VCC : R19 : power : : 1.1V : :
C[6] : R20 : input : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5B :
VCCPD5B : R21 : power : : 2.5V : 5B :
VCCIO5B : R22 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5B :
A[1] : R26 : input : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5B :
GND : T1 : : : : B1L :
GND : T2 : : : : B1L :
GND : T3 : gnd : : : :
@@ -643,7 +643,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 5B :
VCCIO5B : T25 : power : : 2.5V : 5B :
OUT_1[6] : T26 : output : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5B :
GND : U1 : gnd : : : :
GND : U2 : gnd : : : :
VCCL_GXBL : U3 : power : : 1.1V : :
@@ -651,7 +651,7 @@ GND : U4 : gnd : :
VCCE_GXBL : U5 : power : : 1.1V : :
AS_DATA3, DATA3 : U6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A :
VCCIO3B : U8 : power : : 2.5V : 3B :
VCCIO3B : U8 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
@@ -661,15 +661,15 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A :
VCCIO4A : U18 : power : : 2.5V : 4A :
VCCIO4A : U18 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A :
VCCPD5A : U21 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A :
GND : U23 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5B :
B[0] : U25 : input : 2.5 V : : 5B : N
OUT_1[3] : U26 : output : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5B :
GND : V1 : : : : B1L :
GND : V2 : : : : B1L :
GND : V3 : gnd : : : :
@@ -680,7 +680,7 @@ TDO : V7 : output : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B :
VCCIO3B : V11 : power : : 2.5V : 3B :
VCCIO3B : V11 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A :
@@ -709,7 +709,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
VCCIO4A : W14 : power : : 2.5V : 4A :
VCCIO4A : W14 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
@@ -720,8 +720,8 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : :
VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : :
VREFB5AN0 : W23 : power : : : 5A :
VCCIO5B : W24 : power : : 2.5V : 5B :
A[5] : W25 : input : 2.5 V : : 5B : N
C[0] : W26 : input : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5B :
GND : Y1 : : : : B0L :
GND : Y2 : : : : B0L :
GND : Y3 : gnd : : : :
@@ -732,13 +732,13 @@ VCCIO3A : Y7 : power : : 2.5V
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B :
op[1] : Y11 : input : 1.2 V : : 3B : Y
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A :
VCCIO4A : Y17 : power : : 2.5V : 4A :
A[2] : Y15 : input : 1.2 V : : 4A : Y
A[3] : Y16 : input : 1.2 V : : 4A : Y
VCCIO4A : Y17 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A :
@@ -746,5 +746,5 @@ VCCA_FPLL : Y21 : power : : 2.5V
GND : Y22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
A[6] : Y25 : input : 2.5 V : : 5B : N
A[4] : Y26 : input : 2.5 V : : 5B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
Quartus/A1_Q5/output_files/shifter.sof
BIN
View File
Binary file not shown.
Quartus/A1_Q5/output_files/shifter.sta.rpt
+42 -97
View File
@@ -1,5 +1,5 @@
Timing Analyzer report for shifter
Tue Sep 15 10:06:55 2026
Tue Sep 15 19:39:40 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -98,12 +98,12 @@ on the Quartus Prime software download page.
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.05 ;
; Average used ; 1.03 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 5.0% ;
; Processor 2 ; 3.0% ;
+----------------------------+-------------+
@@ -294,10 +294,6 @@ No synchronizer chains to report.
; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
@@ -306,28 +302,19 @@ No synchronizer chains to report.
+-------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------+--------------+-----------------+-----------------+
; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
; A[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
; C[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
; C[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
; C[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
; C[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
; C[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
; C[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
; A[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
; C[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
; C[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
; A[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
; A[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
; A[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
; A[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
; A[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
; A[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
; B[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
; B[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
; B[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
; A[0] ; 1.2 V ; 960 ps ; 960 ps ;
; op[0] ; 1.2 V ; 960 ps ; 960 ps ;
; op[2] ; 1.2 V ; 960 ps ; 960 ps ;
; op[1] ; 1.2 V ; 960 ps ; 960 ps ;
; C[1] ; 1.2 V ; 960 ps ; 960 ps ;
; C[0] ; 1.2 V ; 960 ps ; 960 ps ;
; B[2] ; 1.2 V ; 960 ps ; 960 ps ;
; B[3] ; 1.2 V ; 960 ps ; 960 ps ;
; B[1] ; 1.2 V ; 960 ps ; 960 ps ;
; B[0] ; 1.2 V ; 960 ps ; 960 ps ;
; A[2] ; 1.2 V ; 960 ps ; 960 ps ;
; A[1] ; 1.2 V ; 960 ps ; 960 ps ;
; A[3] ; 1.2 V ; 960 ps ; 960 ps ;
+-------+--------------+-----------------+-----------------+
@@ -336,14 +323,10 @@ No synchronizer chains to report.
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
@@ -352,14 +335,10 @@ No synchronizer chains to report.
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
@@ -368,14 +347,10 @@ No synchronizer chains to report.
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
@@ -384,14 +359,10 @@ No synchronizer chains to report.
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
@@ -420,10 +391,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 22 ; 22 ;
; Unconstrained Input Port Paths ; 176 ; 176 ;
; Unconstrained Output Ports ; 8 ; 8 ;
; Unconstrained Output Port Paths ; 176 ; 176 ;
; Unconstrained Input Ports ; 13 ; 13 ;
; Unconstrained Input Port Paths ; 52 ; 52 ;
; Unconstrained Output Ports ; 4 ; 4 ;
; Unconstrained Output Port Paths ; 52 ; 52 ;
+---------------------------------+-------+------+
@@ -436,21 +407,12 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -466,10 +428,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
@@ -482,21 +440,12 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; C[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -512,10 +461,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
@@ -525,7 +470,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:06:49 2026
Info: Processing started: Tue Sep 15 19:39:34 2026
Info: Command: quartus_sta A1_Q5 -c shifter
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -585,9 +530,9 @@ Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 750 megabytes
Info: Processing ended: Tue Sep 15 10:06:55 2026
Info: Peak virtual memory: 777 megabytes
Info: Processing ended: Tue Sep 15 19:39:40 2026
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05
Info: Total CPU time (on all processors): 00:00:06
Quartus/A1_Q5/shifter.qsf
+33 -1
View File
@@ -55,7 +55,39 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_F7 -to OUT_1[0]
set_location_assignment PIN_F6 -to OUT_1[1]
set_location_assignment PIN_G6 -to OUT_1[2]
set_location_assignment PIN_G7 -to OUT_1[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to C[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to C[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to C[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to C[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to C
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op
set_location_assignment PIN_AE19 -to op[2]
set_location_assignment PIN_Y11 -to op[1]
set_location_assignment PIN_AC10 -to op[0]
set_location_assignment PIN_AC9 -to C[0]
set_location_assignment PIN_AE10 -to C[1]
set_location_assignment PIN_AD13 -to B[0]
set_location_assignment PIN_AC8 -to B[1]
set_location_assignment PIN_P11 -to A[0]
set_location_assignment PIN_P12 -to A[1]
set_location_assignment PIN_Y15 -to A[2]
set_location_assignment PIN_Y16 -to A[3]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Quartus/A1_Q5/shifter.qws
BIN
View File
Binary file not shown.
Quartus/A1_Q5/simulation/questa/shifter.svo
+664 -2210
View File
File diff suppressed because it is too large. Load diff
modules/shifter.sv
+3 -3
View File
@@ -1,8 +1,8 @@
`ifndef SHIFTER_H_SV
`define SHIFTER_H_SV
module shifter #(width=8)(input logic [2:0] op,
input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
output logic[width-1:0] OUT_1);
module shifter #(width=2)(input logic [2:0] op,
input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C,
output logic[2**width-1:0] OUT_1);
always_comb begin
case (op)
modules/shifter.sv.bak
+19
View File
@@ -0,0 +1,19 @@
`ifndef SHIFTER_H_SV
`define SHIFTER_H_SV
module shifter #(width=8)(input logic [2:0] op,
input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
output logic[width-1:0] OUT_1);
always_comb begin
case (op)
3'b000: OUT_1 = A << C;
3'b001: OUT_1 = A >> C;
3'b011: OUT_1 = $signed(A) >>> C;
3'b100: OUT_1 = A << B;
3'b101: OUT_1 = A >> B;
3'b111: OUT_1 = $signed(A) >>> B;
default:OUT_1 = A;
endcase
end
endmodule
`endif