diff --git a/Quartus/A1_Q4/alu.qws b/Quartus/A1_Q4/alu.qws new file mode 100644 index 0000000..ff3a47e Binary files /dev/null and b/Quartus/A1_Q4/alu.qws differ diff --git a/Quartus/A1_Q4/db/alu.pplq.rdb b/Quartus/A1_Q4/db/alu.pplq.rdb index 46c284e..e1f255e 100644 Binary files a/Quartus/A1_Q4/db/alu.pplq.rdb and b/Quartus/A1_Q4/db/alu.pplq.rdb differ diff --git a/Quartus/A1_Q4/db/A1_Q4.quiproj.2570.rdr.flock b/Quartus/A1_Q5/db/A1_Q5.quiproj.2570.rdr.flock similarity index 100% rename from Quartus/A1_Q4/db/A1_Q4.quiproj.2570.rdr.flock rename to Quartus/A1_Q5/db/A1_Q5.quiproj.2570.rdr.flock diff --git a/Quartus/A1_Q5/db/prev_cmp_A1_Q5.qmsg b/Quartus/A1_Q5/db/prev_cmp_A1_Q5.qmsg new file mode 100644 index 0000000..8eedf84 --- /dev/null +++ b/Quartus/A1_Q5/db/prev_cmp_A1_Q5.qmsg @@ -0,0 +1,37 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465036231 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465036232 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:37:16 2026 " "Processing started: Tue Sep 15 19:37:16 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465036232 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465036232 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465036232 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789465036549 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789465036550 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789465046004 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465046004 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789465046140 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789465046905 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789465047246 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789465047246 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789465047275 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789465047275 ""} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Implemented 32 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789465047275 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789465047275 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465047282 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:37:27 2026 " "Processing ended: Tue Sep 15 19:37:27 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465047282 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465047282 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465047282 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465047282 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1789465048807 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465048808 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:37:28 2026 " "Processing started: Tue Sep 15 19:37:28 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465048808 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1789465048808 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_fit --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1789465048808 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1789465048858 ""} +{ "Info" "0" "" "Project = A1_Q5" { } { } 0 0 "Project = A1_Q5" 0 0 "Fitter" 0 0 1789465048859 ""} +{ "Info" "0" "" "Revision = shifter" { } { } 0 0 "Revision = shifter" 0 0 "Fitter" 0 0 1789465048859 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789465049047 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789465049047 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789465049052 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465049129 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465049129 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789465049534 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789465049561 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789465049613 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 17 " "No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789465049868 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789465056595 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465056643 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789465056645 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465056646 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465056646 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789465056646 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789465056646 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789465056646 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789465056647 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789465056647 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789465056647 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465056666 ""} diff --git a/Quartus/A1_Q5/db/shifter.(0).cnf.cdb b/Quartus/A1_Q5/db/shifter.(0).cnf.cdb index 3976864..c95c67d 100644 Binary files a/Quartus/A1_Q5/db/shifter.(0).cnf.cdb and b/Quartus/A1_Q5/db/shifter.(0).cnf.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.(0).cnf.hdb b/Quartus/A1_Q5/db/shifter.(0).cnf.hdb index 4ac19de..15310df 100644 Binary files a/Quartus/A1_Q5/db/shifter.(0).cnf.hdb and b/Quartus/A1_Q5/db/shifter.(0).cnf.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.asm.qmsg b/Quartus/A1_Q5/db/shifter.asm.qmsg index d4b946c..36dd42e 100644 --- a/Quartus/A1_Q5/db/shifter.asm.qmsg +++ b/Quartus/A1_Q5/db/shifter.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430803604 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430803605 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:06:43 2026 " "Processing started: Tue Sep 15 10:06:43 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430803605 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789430803605 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789430803605 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789430804252 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789430808582 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "518 " "Peak virtual memory: 518 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430808780 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:48 2026 " "Processing ended: Tue Sep 15 10:06:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430808780 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430808780 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430808780 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789430808780 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465167736 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465167737 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:27 2026 " "Processing started: Tue Sep 15 19:39:27 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465167737 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789465167737 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789465167737 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789465168580 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789465173536 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "507 " "Peak virtual memory: 507 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:33 2026 " "Processing ended: Tue Sep 15 19:39:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465173727 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789465173727 ""} diff --git a/Quartus/A1_Q5/db/shifter.asm.rdb b/Quartus/A1_Q5/db/shifter.asm.rdb index 5d0fe9d..e1c2f35 100644 Binary files a/Quartus/A1_Q5/db/shifter.asm.rdb and b/Quartus/A1_Q5/db/shifter.asm.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.bpm b/Quartus/A1_Q5/db/shifter.cmp.bpm index cede5e0..b537841 100644 Binary files a/Quartus/A1_Q5/db/shifter.cmp.bpm and b/Quartus/A1_Q5/db/shifter.cmp.bpm differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.cdb b/Quartus/A1_Q5/db/shifter.cmp.cdb index 12ccafa..f410f43 100644 Binary files a/Quartus/A1_Q5/db/shifter.cmp.cdb and b/Quartus/A1_Q5/db/shifter.cmp.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.hdb b/Quartus/A1_Q5/db/shifter.cmp.hdb index 04c759e..00c1666 100644 Binary files a/Quartus/A1_Q5/db/shifter.cmp.hdb and b/Quartus/A1_Q5/db/shifter.cmp.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.idb b/Quartus/A1_Q5/db/shifter.cmp.idb index ee299ad..12a4086 100644 Binary files a/Quartus/A1_Q5/db/shifter.cmp.idb and b/Quartus/A1_Q5/db/shifter.cmp.idb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.logdb b/Quartus/A1_Q5/db/shifter.cmp.logdb index 9060170..bc090df 100644 --- a/Quartus/A1_Q5/db/shifter.cmp.logdb +++ b/Quartus/A1_Q5/db/shifter.cmp.logdb @@ -1,11 +1,11 @@ v1 IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, -IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, -IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, @@ -29,42 +29,29 @@ IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, -IO_RULES_MATRIX,Total Pass,0;0;0;0;0;30;0;0;0;0;0;0;0;8;0;0;0;0;8;0;0;0;0;8;0;30;30;0, +IO_RULES_MATRIX,Total Pass,0;15;15;0;0;17;15;0;0;0;0;0;0;4;0;0;0;0;4;0;0;0;0;4;0;17;17;0, IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,30;30;30;30;30;0;30;30;30;30;30;30;30;22;30;30;30;30;22;30;30;30;30;22;30;0;0;30, +IO_RULES_MATRIX,Total Inapplicable,17;2;2;17;17;0;2;17;17;17;17;17;17;13;17;17;17;17;13;17;17;17;17;13;17;0;0;17, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,OUT_1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,OUT_1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,OUT_1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,OUT_1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,OUT_1[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,OUT_1[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,OUT_1[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,OUT_1[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,C[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,C[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,C[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,C[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,C[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,C[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,C[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,C[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_SUMMARY,Total I/O Rules,28, -IO_RULES_SUMMARY,Number of I/O Rules Passed,6, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, IO_RULES_SUMMARY,Number of I/O Rules Failed,0, IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, -IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19, diff --git a/Quartus/A1_Q5/db/shifter.cmp.rdb b/Quartus/A1_Q5/db/shifter.cmp.rdb index 69284a8..010e7fe 100644 Binary files a/Quartus/A1_Q5/db/shifter.cmp.rdb and b/Quartus/A1_Q5/db/shifter.cmp.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd index b19b6d1..5b25938 100644 Binary files a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd and b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd index 118df22..0778662 100644 Binary files a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd and b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A1_Q5/db/shifter.db_info b/Quartus/A1_Q5/db/shifter.db_info index 21c503d..eda06ad 100644 --- a/Quartus/A1_Q5/db/shifter.db_info +++ b/Quartus/A1_Q5/db/shifter.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Tue Sep 15 10:05:43 2026 +Creation_Time = Tue Sep 15 19:14:26 2026 diff --git a/Quartus/A1_Q5/db/shifter.eda.qmsg b/Quartus/A1_Q5/db/shifter.eda.qmsg index 910dd95..08bfbd0 100644 --- a/Quartus/A1_Q5/db/shifter.eda.qmsg +++ b/Quartus/A1_Q5/db/shifter.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430816693 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430816694 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:06:56 2026 " "Processing started: Tue Sep 15 10:06:56 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430816694 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430816694 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430816694 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789430817425 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "shifter.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/ simulation " "Generated file shifter.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789430817488 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430817524 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:57 2026 " "Processing ended: Tue Sep 15 10:06:57 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430817524 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430817524 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430817524 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430817524 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465182961 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465182961 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:42 2026 " "Processing started: Tue Sep 15 19:39:42 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465182961 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465182961 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465182961 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789465183869 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "shifter.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/ simulation " "Generated file shifter.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789465183961 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "666 " "Peak virtual memory: 666 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:44 2026 " "Processing ended: Tue Sep 15 19:39:44 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465184019 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789465184019 ""} diff --git a/Quartus/A1_Q5/db/shifter.fit.qmsg b/Quartus/A1_Q5/db/shifter.fit.qmsg index 3a99f2c..7754089 100644 --- a/Quartus/A1_Q5/db/shifter.fit.qmsg +++ b/Quartus/A1_Q5/db/shifter.fit.qmsg @@ -1,44 +1,45 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789430770929 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789430770930 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789430770935 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430771006 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430771006 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789430771421 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789430771454 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789430771502 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "30 30 " "No exact pin location assignment(s) for 30 pins of 30 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789430771778 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789430778347 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430778461 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789430778464 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430778464 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430778464 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789430778465 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789430778465 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789430778465 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789430778465 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789430778465 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789430778465 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430778484 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789430784343 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789430784344 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789430784344 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789430784345 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789430784346 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789430784346 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789430784347 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789430784351 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789430784396 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:04 " "Fitter placement preparation operations ending: elapsed time is 00:00:04" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430788050 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789430789723 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789430790074 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430790074 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789430790662 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y24 X68_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36"} { { 12 { 0 ""} 57 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789430796160 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789430796160 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789430796398 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789430796398 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789430796398 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430796401 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789430797416 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430797458 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430797888 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430797888 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430798495 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430801226 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1347 " "Peak virtual memory: 1347 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430802055 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:42 2026 " "Processing ended: Tue Sep 15 10:06:42 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430802055 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430802055 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430802055 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789430802055 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789465130214 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789465130214 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789465130221 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465130300 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789465130300 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789465130803 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789465130840 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789465130902 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 17 " "No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789465131227 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789465138495 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465138551 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789465138553 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789465138554 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789465138555 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789465138555 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789465138555 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465138575 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789465145753 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789465145754 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789465145754 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789465145755 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789465145756 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789465145756 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789465145756 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789465145760 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789465145841 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465147357 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789465148341 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789465148587 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465148587 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789465149821 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789465158188 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789465158188 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789465158582 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789465158582 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789465158582 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465158584 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789465160095 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465160145 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465160585 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789465160585 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789465161535 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789465164913 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789465165221 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1379 " "Peak virtual memory: 1379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:25 2026 " "Processing ended: Tue Sep 15 19:39:25 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:36 " "Elapsed time: 00:00:36" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:50 " "Total CPU time (on all processors): 00:00:50" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465165869 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789465165869 ""} diff --git a/Quartus/A1_Q5/db/shifter.hier_info b/Quartus/A1_Q5/db/shifter.hier_info index f3e0c16..2a52d65 100644 --- a/Quartus/A1_Q5/db/shifter.hier_info +++ b/Quartus/A1_Q5/db/shifter.hier_info @@ -3,132 +3,69 @@ op[0] => Mux0.IN8 op[0] => Mux1.IN8 op[0] => Mux2.IN8 op[0] => Mux3.IN8 -op[0] => Mux4.IN8 -op[0] => Mux5.IN8 -op[0] => Mux6.IN8 -op[0] => Mux7.IN8 op[1] => Mux0.IN7 op[1] => Mux1.IN7 op[1] => Mux2.IN7 op[1] => Mux3.IN7 -op[1] => Mux4.IN7 -op[1] => Mux5.IN7 -op[1] => Mux6.IN7 -op[1] => Mux7.IN7 op[2] => Mux0.IN6 op[2] => Mux1.IN6 op[2] => Mux2.IN6 op[2] => Mux3.IN6 -op[2] => Mux4.IN6 -op[2] => Mux5.IN6 -op[2] => Mux6.IN6 -op[2] => Mux7.IN6 -A[0] => ShiftLeft0.IN8 -A[0] => ShiftRight0.IN8 -A[0] => ShiftRight1.IN8 -A[0] => ShiftLeft1.IN8 -A[0] => ShiftRight2.IN8 -A[0] => ShiftRight3.IN8 -A[0] => Mux7.IN9 -A[0] => Mux7.IN10 -A[1] => ShiftLeft0.IN7 -A[1] => ShiftRight0.IN7 -A[1] => ShiftRight1.IN7 -A[1] => ShiftLeft1.IN7 -A[1] => ShiftRight2.IN7 -A[1] => ShiftRight3.IN7 -A[1] => Mux6.IN9 -A[1] => Mux6.IN10 -A[2] => ShiftLeft0.IN6 -A[2] => ShiftRight0.IN6 -A[2] => ShiftRight1.IN6 -A[2] => ShiftLeft1.IN6 -A[2] => ShiftRight2.IN6 -A[2] => ShiftRight3.IN6 -A[2] => Mux5.IN9 -A[2] => Mux5.IN10 -A[3] => ShiftLeft0.IN5 -A[3] => ShiftRight0.IN5 -A[3] => ShiftRight1.IN5 -A[3] => ShiftLeft1.IN5 -A[3] => ShiftRight2.IN5 -A[3] => ShiftRight3.IN5 -A[3] => Mux4.IN9 -A[3] => Mux4.IN10 -A[4] => ShiftLeft0.IN4 -A[4] => ShiftRight0.IN4 -A[4] => ShiftRight1.IN4 -A[4] => ShiftLeft1.IN4 -A[4] => ShiftRight2.IN4 -A[4] => ShiftRight3.IN4 -A[4] => Mux3.IN9 -A[4] => Mux3.IN10 -A[5] => ShiftLeft0.IN3 -A[5] => ShiftRight0.IN3 -A[5] => ShiftRight1.IN3 -A[5] => ShiftLeft1.IN3 -A[5] => ShiftRight2.IN3 -A[5] => ShiftRight3.IN3 -A[5] => Mux2.IN9 -A[5] => Mux2.IN10 -A[6] => ShiftLeft0.IN2 -A[6] => ShiftRight0.IN2 -A[6] => ShiftRight1.IN2 -A[6] => ShiftLeft1.IN2 -A[6] => ShiftRight2.IN2 -A[6] => ShiftRight3.IN2 -A[6] => Mux1.IN9 -A[6] => Mux1.IN10 -A[7] => ShiftLeft0.IN1 -A[7] => ShiftRight0.IN1 -A[7] => ShiftRight1.IN0 -A[7] => ShiftRight1.IN1 -A[7] => ShiftLeft1.IN1 -A[7] => ShiftRight2.IN1 -A[7] => ShiftRight3.IN0 -A[7] => ShiftRight3.IN1 -A[7] => Mux0.IN9 -A[7] => Mux0.IN10 -C[0] => ShiftLeft0.IN16 -C[0] => ShiftRight0.IN16 -C[0] => ShiftRight1.IN16 -C[1] => ShiftLeft0.IN15 -C[1] => ShiftRight0.IN15 -C[1] => ShiftRight1.IN15 -C[2] => ShiftLeft0.IN14 -C[2] => ShiftRight0.IN14 -C[2] => ShiftRight1.IN14 -C[3] => ShiftLeft0.IN13 -C[3] => ShiftRight0.IN13 -C[3] => ShiftRight1.IN13 -C[4] => ShiftLeft0.IN12 -C[4] => ShiftRight0.IN12 -C[4] => ShiftRight1.IN12 -C[5] => ShiftLeft0.IN11 -C[5] => ShiftRight0.IN11 -C[5] => ShiftRight1.IN11 -C[6] => ShiftLeft0.IN10 -C[6] => ShiftRight0.IN10 -C[6] => ShiftRight1.IN10 -C[7] => ShiftLeft0.IN9 -C[7] => ShiftRight0.IN9 -C[7] => ShiftRight1.IN9 -B[0] => ShiftLeft1.IN11 -B[0] => ShiftRight2.IN11 -B[0] => ShiftRight3.IN11 -B[1] => ShiftLeft1.IN10 -B[1] => ShiftRight2.IN10 -B[1] => ShiftRight3.IN10 -B[2] => ShiftLeft1.IN9 -B[2] => ShiftRight2.IN9 -B[2] => ShiftRight3.IN9 -OUT_1[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE -OUT_1[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +A[0] => ShiftLeft0.IN4 +A[0] => ShiftRight0.IN4 +A[0] => ShiftRight1.IN4 +A[0] => ShiftLeft1.IN4 +A[0] => ShiftRight2.IN4 +A[0] => ShiftRight3.IN4 +A[0] => Mux3.IN9 +A[0] => Mux3.IN10 +A[1] => ShiftLeft0.IN3 +A[1] => ShiftRight0.IN3 +A[1] => ShiftRight1.IN3 +A[1] => ShiftLeft1.IN3 +A[1] => ShiftRight2.IN3 +A[1] => ShiftRight3.IN3 +A[1] => Mux2.IN9 +A[1] => Mux2.IN10 +A[2] => ShiftLeft0.IN2 +A[2] => ShiftRight0.IN2 +A[2] => ShiftRight1.IN2 +A[2] => ShiftLeft1.IN2 +A[2] => ShiftRight2.IN2 +A[2] => ShiftRight3.IN2 +A[2] => Mux1.IN9 +A[2] => Mux1.IN10 +A[3] => ShiftLeft0.IN1 +A[3] => ShiftRight0.IN1 +A[3] => ShiftRight1.IN0 +A[3] => ShiftRight1.IN1 +A[3] => ShiftLeft1.IN1 +A[3] => ShiftRight2.IN1 +A[3] => ShiftRight3.IN0 +A[3] => ShiftRight3.IN1 +A[3] => Mux0.IN9 +A[3] => Mux0.IN10 +B[0] => ShiftLeft1.IN8 +B[0] => ShiftRight2.IN8 +B[0] => ShiftRight3.IN8 +B[1] => ShiftLeft1.IN7 +B[1] => ShiftRight2.IN7 +B[1] => ShiftRight3.IN7 +B[2] => ShiftLeft1.IN6 +B[2] => ShiftRight2.IN6 +B[2] => ShiftRight3.IN6 +B[3] => ShiftLeft1.IN5 +B[3] => ShiftRight2.IN5 +B[3] => ShiftRight3.IN5 +C[0] => ShiftLeft0.IN6 +C[0] => ShiftRight0.IN6 +C[0] => ShiftRight1.IN6 +C[1] => ShiftLeft0.IN5 +C[1] => ShiftRight0.IN5 +C[1] => ShiftRight1.IN5 +OUT_1[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE diff --git a/Quartus/A1_Q5/db/shifter.hif b/Quartus/A1_Q5/db/shifter.hif index a2ea335..9dc7ae2 100644 Binary files a/Quartus/A1_Q5/db/shifter.hif and b/Quartus/A1_Q5/db/shifter.hif differ diff --git a/Quartus/A1_Q5/db/shifter.map.bpm b/Quartus/A1_Q5/db/shifter.map.bpm index e4cbac7..8f73719 100644 Binary files a/Quartus/A1_Q5/db/shifter.map.bpm and b/Quartus/A1_Q5/db/shifter.map.bpm differ diff --git a/Quartus/A1_Q5/db/shifter.map.cdb b/Quartus/A1_Q5/db/shifter.map.cdb index 5ed5000..d026a47 100644 Binary files a/Quartus/A1_Q5/db/shifter.map.cdb and b/Quartus/A1_Q5/db/shifter.map.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.map.hdb b/Quartus/A1_Q5/db/shifter.map.hdb index 3e8e620..06823f2 100644 Binary files a/Quartus/A1_Q5/db/shifter.map.hdb and b/Quartus/A1_Q5/db/shifter.map.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.map.qmsg b/Quartus/A1_Q5/db/shifter.map.qmsg index 1208da4..9da54d9 100644 --- a/Quartus/A1_Q5/db/shifter.map.qmsg +++ b/Quartus/A1_Q5/db/shifter.map.qmsg @@ -1,11 +1,11 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430758021 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430758022 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:05:57 2026 " "Processing started: Tue Sep 15 10:05:57 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430758022 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430758022 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430758022 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789430758320 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789430758321 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430767297 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430767297 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789430767432 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789430768701 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789430769122 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430769122 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "115 " "Implemented 115 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789430769167 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789430769167 ""} { "Info" "ICUT_CUT_TM_LCELLS" "85 " "Implemented 85 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789430769167 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789430769167 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430769173 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:09 2026 " "Processing ended: Tue Sep 15 10:06:09 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430769173 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430769173 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430769173 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430769173 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465117698 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465117698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:38:37 2026 " "Processing started: Tue Sep 15 19:38:37 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465117698 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465117698 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465117699 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789465118007 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789465118007 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789465126919 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465126919 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789465127060 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789465127834 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789465128194 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789465128194 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "49 " "Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789465128236 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789465128236 ""} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Implemented 32 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789465128236 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789465128236 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:38:48 2026 " "Processing ended: Tue Sep 15 19:38:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465128243 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789465128243 ""} diff --git a/Quartus/A1_Q5/db/shifter.map.rdb b/Quartus/A1_Q5/db/shifter.map.rdb index 35d36c8..f5cb174 100644 Binary files a/Quartus/A1_Q5/db/shifter.map.rdb and b/Quartus/A1_Q5/db/shifter.map.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.map_bb.cdb b/Quartus/A1_Q5/db/shifter.map_bb.cdb index e5d06b6..e26dfbf 100644 Binary files a/Quartus/A1_Q5/db/shifter.map_bb.cdb and b/Quartus/A1_Q5/db/shifter.map_bb.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.map_bb.hdb b/Quartus/A1_Q5/db/shifter.map_bb.hdb index 21bfada..9c83f7c 100644 Binary files a/Quartus/A1_Q5/db/shifter.map_bb.hdb and b/Quartus/A1_Q5/db/shifter.map_bb.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.pplq.rdb b/Quartus/A1_Q5/db/shifter.pplq.rdb new file mode 100644 index 0000000..e1f255e Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.pplq.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.pre_map.hdb b/Quartus/A1_Q5/db/shifter.pre_map.hdb index 5c8fd3b..93e40dc 100644 Binary files a/Quartus/A1_Q5/db/shifter.pre_map.hdb and b/Quartus/A1_Q5/db/shifter.pre_map.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.routing.rdb b/Quartus/A1_Q5/db/shifter.routing.rdb index c06b242..b5b070a 100644 Binary files a/Quartus/A1_Q5/db/shifter.routing.rdb and b/Quartus/A1_Q5/db/shifter.routing.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.rtlv.hdb b/Quartus/A1_Q5/db/shifter.rtlv.hdb index 8885f64..f0a202a 100644 Binary files a/Quartus/A1_Q5/db/shifter.rtlv.hdb and b/Quartus/A1_Q5/db/shifter.rtlv.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb b/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb index d38b2ea..125fb57 100644 Binary files a/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb and b/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.sta.qmsg b/Quartus/A1_Q5/db/shifter.sta.qmsg index 2fb2152..cf8dbcf 100644 --- a/Quartus/A1_Q5/db/shifter.sta.qmsg +++ b/Quartus/A1_Q5/db/shifter.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430810263 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430810263 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:06:49 2026 " "Processing started: Tue Sep 15 10:06:49 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430810263 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430810263 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q5 -c shifter " "Command: quartus_sta A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430810264 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789430810318 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789430810787 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789430810787 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430810861 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430810861 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789430811445 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430811446 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430811446 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430811447 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430811447 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430811447 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789430811448 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789430811452 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430811453 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811454 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811458 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811459 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811459 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811460 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811461 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430811463 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430811501 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430812500 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430812608 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430812608 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430812609 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430812609 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812610 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812611 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812612 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812613 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812614 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812614 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430812616 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430812867 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430813469 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430813518 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430813518 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430813518 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430813519 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813520 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813521 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813521 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813522 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813523 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430813525 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430813673 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430813673 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430813673 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430813674 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813675 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813676 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813676 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813677 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813678 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430815121 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430815122 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "750 " "Peak virtual memory: 750 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430815157 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:55 2026 " "Processing ended: Tue Sep 15 10:06:55 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430815157 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430815157 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430815157 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789430815157 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789465175261 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789465175262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 19:39:34 2026 " "Processing started: Tue Sep 15 19:39:34 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789465175262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465175262 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q5 -c shifter " "Command: quartus_sta A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465175262 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789465175322 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789465175845 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789465175845 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465175922 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465175922 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789465176538 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465176538 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465176539 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465176539 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789465176539 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465176540 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789465176540 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789465176545 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465176545 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176547 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176550 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176551 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176552 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176553 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465176553 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465176556 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465176606 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465178030 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465178130 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178131 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178133 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178134 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178135 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178136 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465178136 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789465178138 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789465178417 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789465179197 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465179249 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465179250 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179251 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179252 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179253 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179254 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179254 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789465179256 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789465179414 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179415 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179416 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179417 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179418 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789465179418 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465180905 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789465180906 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "777 " "Peak virtual memory: 777 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 19:39:40 2026 " "Processing ended: Tue Sep 15 19:39:40 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789465180932 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789465180932 ""} diff --git a/Quartus/A1_Q5/db/shifter.sta.rdb b/Quartus/A1_Q5/db/shifter.sta.rdb index bea46c3..3213de6 100644 Binary files a/Quartus/A1_Q5/db/shifter.sta.rdb and b/Quartus/A1_Q5/db/shifter.sta.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb index bbfea3d..75037be 100644 Binary files a/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb and b/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb index adc4878..d870da6 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb index 406700f..09dfe7d 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb index e4573dc..ce4bfcd 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb index fd2ebcf..a407d67 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb index ff330e9..471ce93 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb index 6588c1f..59eb94c 100644 Binary files a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tmw_info b/Quartus/A1_Q5/db/shifter.tmw_info index ab250eb..3931c4b 100644 --- a/Quartus/A1_Q5/db/shifter.tmw_info +++ b/Quartus/A1_Q5/db/shifter.tmw_info @@ -1,7 +1,7 @@ -start_full_compilation:s:00:01:02 -start_analysis_synthesis:s:00:00:13-start_full_compilation +start_full_compilation:s:00:01:08 +start_analysis_synthesis:s:00:00:12-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:33-start_full_compilation -start_assembler:s:00:00:07-start_full_compilation -start_timing_analyzer:s:00:00:06-start_full_compilation +start_fitter:s:00:00:38-start_full_compilation +start_assembler:s:00:00:08-start_full_compilation +start_timing_analyzer:s:00:00:07-start_full_compilation start_eda_netlist_writer:s:00:00:03-start_full_compilation diff --git a/Quartus/A1_Q5/db/shifter.vpr.ammdb b/Quartus/A1_Q5/db/shifter.vpr.ammdb index cae37eb..ac5d8d5 100644 Binary files a/Quartus/A1_Q5/db/shifter.vpr.ammdb and b/Quartus/A1_Q5/db/shifter.vpr.ammdb differ diff --git a/Quartus/A1_Q5/db/shifter_partition_pins.json b/Quartus/A1_Q5/db/shifter_partition_pins.json index 753304c..15883bf 100644 --- a/Quartus/A1_Q5/db/shifter_partition_pins.json +++ b/Quartus/A1_Q5/db/shifter_partition_pins.json @@ -20,29 +20,13 @@ "strict" : false }, { - "name" : "OUT_1[4]", - "strict" : false - }, - { - "name" : "OUT_1[5]", - "strict" : false - }, - { - "name" : "OUT_1[6]", - "strict" : false - }, - { - "name" : "OUT_1[7]", + "name" : "A[0]", "strict" : false }, { "name" : "op[0]", "strict" : false }, - { - "name" : "A[0]", - "strict" : false - }, { "name" : "op[2]", "strict" : false @@ -52,31 +36,7 @@ "strict" : false }, { - "name" : "C[2]", - "strict" : false - }, - { - "name" : "C[3]", - "strict" : false - }, - { - "name" : "C[4]", - "strict" : false - }, - { - "name" : "C[5]", - "strict" : false - }, - { - "name" : "C[6]", - "strict" : false - }, - { - "name" : "C[7]", - "strict" : false - }, - { - "name" : "A[7]", + "name" : "C[1]", "strict" : false }, { @@ -84,19 +44,19 @@ "strict" : false }, { - "name" : "C[1]", + "name" : "B[2]", "strict" : false }, { - "name" : "A[6]", + "name" : "B[3]", "strict" : false }, { - "name" : "A[4]", + "name" : "B[1]", "strict" : false }, { - "name" : "A[5]", + "name" : "B[0]", "strict" : false }, { @@ -110,18 +70,6 @@ { "name" : "A[3]", "strict" : false - }, - { - "name" : "B[2]", - "strict" : false - }, - { - "name" : "B[0]", - "strict" : false - }, - { - "name" : "B[1]", - "strict" : false } ] } diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb index 2ea8512..1e0a846 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb index 8f9fcbe..4325c99 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb index ec3c1e0..e5625c4 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb index b0cba88..d28b497 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb index 8b0d586..50072cb 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb index 1140261..3e42912 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb index 0041519..c965f78 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.dpi b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.dpi index 299e850..f973246 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.dpi and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.dpi differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb index 7211204..87d6272 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb index 97d1f57..f3c0da7 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb index 06f3b87..1b48f45 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb index 053a0b9..db284db 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrs.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrs.cdb index 0a75dc7..1742976 100644 Binary files a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrs.cdb and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrs.cdb differ diff --git a/Quartus/A1_Q5/output_files/shifter.asm.rpt b/Quartus/A1_Q5/output_files/shifter.asm.rpt index 1f227bb..c973bbb 100644 --- a/Quartus/A1_Q5/output_files/shifter.asm.rpt +++ b/Quartus/A1_Q5/output_files/shifter.asm.rpt @@ -1,5 +1,5 @@ Assembler report for shifter -Tue Sep 15 10:06:48 2026 +Tue Sep 15 19:39:33 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Sep 15 10:06:48 2026 ; +; Assembler Status ; Successful - Tue Sep 15 19:39:33 2026 ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; ; Family ; Cyclone V ; @@ -67,8 +67,8 @@ on the Quartus Prime software download page. +----------------+----------------------+ ; Option ; Setting ; +----------------+----------------------+ -; JTAG usercode ; 0x007990C3 ; -; Checksum ; 0x007990C3 ; +; JTAG usercode ; 0x007896D6 ; +; Checksum ; 0x007896D6 ; +----------------+----------------------+ @@ -78,14 +78,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:06:43 2026 + Info: Processing started: Tue Sep 15 19:39:27 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 518 megabytes - Info: Processing ended: Tue Sep 15 10:06:48 2026 - Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:05 + Info: Peak virtual memory: 507 megabytes + Info: Processing ended: Tue Sep 15 19:39:33 2026 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:06 diff --git a/Quartus/A1_Q5/output_files/shifter.done b/Quartus/A1_Q5/output_files/shifter.done index 458a2c6..879d0bb 100644 --- a/Quartus/A1_Q5/output_files/shifter.done +++ b/Quartus/A1_Q5/output_files/shifter.done @@ -1 +1 @@ -Tue Sep 15 10:06:58 2026 +Tue Sep 15 19:39:44 2026 diff --git a/Quartus/A1_Q5/output_files/shifter.eda.rpt b/Quartus/A1_Q5/output_files/shifter.eda.rpt index 554c950..9607ead 100644 --- a/Quartus/A1_Q5/output_files/shifter.eda.rpt +++ b/Quartus/A1_Q5/output_files/shifter.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for shifter -Tue Sep 15 10:06:57 2026 +Tue Sep 15 19:39:43 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:06:57 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Sep 15 19:39:43 2026 ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; ; Family ; Cyclone V ; @@ -81,14 +81,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:06:56 2026 + Info: Processing started: Tue Sep 15 19:39:42 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file shifter.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 670 megabytes - Info: Processing ended: Tue Sep 15 10:06:57 2026 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 666 megabytes + Info: Processing ended: Tue Sep 15 19:39:44 2026 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A1_Q5/output_files/shifter.fit.rpt b/Quartus/A1_Q5/output_files/shifter.fit.rpt index 75ccc78..602dd46 100644 --- a/Quartus/A1_Q5/output_files/shifter.fit.rpt +++ b/Quartus/A1_Q5/output_files/shifter.fit.rpt @@ -1,5 +1,5 @@ Fitter report for shifter -Tue Sep 15 10:06:41 2026 +Tue Sep 15 19:39:25 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -10,27 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 2. Fitter Summary 3. Fitter Settings 4. Parallel Compilation - 5. Incremental Compilation Preservation Summary - 6. Incremental Compilation Partition Settings - 7. Incremental Compilation Placement Preservation - 8. Pin-Out File - 9. Fitter Resource Usage Summary - 10. Fitter Partition Statistics - 11. Input Pins - 12. Output Pins - 13. I/O Bank Usage - 14. All Package Pins - 15. I/O Assignment Warnings - 16. Fitter Resource Utilization by Entity - 17. Delay Chain Summary - 18. Pad To Core Delay Chain Fanout - 19. Routing Usage Summary - 20. I/O Rules Summary - 21. I/O Rules Details - 22. I/O Rules Matrix - 23. Fitter Device Options - 24. Operating Settings and Conditions - 25. Fitter Messages + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. I/O Rules Summary + 22. I/O Rules Details + 23. I/O Rules Matrix + 24. Fitter Device Options + 25. Operating Settings and Conditions + 26. Fitter Messages @@ -57,16 +58,16 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Sep 15 10:06:41 2026 ; +; Fitter Status ; Successful - Tue Sep 15 19:39:25 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; ; Family ; Cyclone V ; ; Device ; 5CGXFC5C6F27C7 ; ; Timing Models ; Final ; -; Logic utilization (in ALMs) ; 48 / 29,080 ( < 1 % ) ; +; Logic utilization (in ALMs) ; 21 / 29,080 ( < 1 % ) ; ; Total registers ; 0 ; -; Total pins ; 30 / 364 ( 8 % ) ; +; Total pins ; 17 / 364 ( 5 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; ; Total RAM Blocks ; 0 / 446 ( 0 % ) ; @@ -147,28 +148,41 @@ on the Quartus Prime software download page. ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.01 ; +; Average used ; 1.00 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.6% ; +; Processor 2 ; 0.3% ; +----------------------------+-------------+ -+--------------------------------------------------------------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+---------------------+--------------------+----------------------------+--------------------------+ -; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; -+---------------------+--------------------+----------------------------+--------------------------+ -; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 146 ) ; 0.00 % ( 0 / 146 ) ; 0.00 % ( 0 / 146 ) ; -; -- Achieved ; 0.00 % ( 0 / 146 ) ; 0.00 % ( 0 / 146 ) ; 0.00 % ( 0 / 146 ) ; -; ; ; ; ; -; Routing (by net) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; -; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; -+---------------------+--------------------+----------------------------+--------------------------+ ++--------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; I/O Standard ; shifter ; ; A ; 1.2 V ; QSF Assignment ; +; I/O Standard ; shifter ; ; C ; 1.2 V ; QSF Assignment ; +; I/O Standard ; shifter ; ; C[2] ; 1.2 V ; QSF Assignment ; +; I/O Standard ; shifter ; ; C[3] ; 1.2 V ; QSF Assignment ; +; I/O Standard ; shifter ; ; op ; 1.2 V ; QSF Assignment ; ++--------------+----------------+--------------+------------+---------------+----------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 67 ) ; 0.00 % ( 0 / 67 ) ; 0.00 % ( 0 / 67 ) ; +; -- Achieved ; 0.00 % ( 0 / 67 ) ; 0.00 % ( 0 / 67 ) ; 0.00 % ( 0 / 67 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -186,7 +200,7 @@ on the Quartus Prime software download page. +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 146 ) ; N/A ; Source File ; N/A ; ; +; Top ; 0.00 % ( 0 / 67 ) ; N/A ; Source File ; N/A ; ; ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ @@ -202,14 +216,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------------------------------------------------------------+--------------------+-------+ ; Resource ; Usage ; % ; +-------------------------------------------------------------+--------------------+-------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 48 / 29,080 ; < 1 % ; -; ALMs needed [=A-B+C] ; 48 ; ; -; [A] ALMs used in final placement [=a+b+c+d] ; 50 / 29,080 ; < 1 % ; +; Logic utilization (ALMs needed / total ALMs on device) ; 21 / 29,080 ; < 1 % ; +; ALMs needed [=A-B+C] ; 21 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 21 / 29,080 ; < 1 % ; ; [a] ALMs used for LUT logic and registers ; 0 ; ; -; [b] ALMs used for LUT logic ; 50 ; ; +; [b] ALMs used for LUT logic ; 21 ; ; ; [c] ALMs used for registers ; 0 ; ; ; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; -; [B] Estimate of ALMs recoverable by dense packing ; 2 / 29,080 ; < 1 % ; +; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ; ; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29,080 ; 0 % ; ; [a] Due to location constrained logic ; 0 ; ; ; [b] Due to LAB-wide signal conflicts ; 0 ; ; @@ -218,16 +232,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; ; ; ; ; Difficulty packing design ; Low ; ; ; ; ; ; -; Total LABs: partially or completely used ; 7 / 2,908 ; < 1 % ; -; -- Logic LABs ; 7 ; ; +; Total LABs: partially or completely used ; 3 / 2,908 ; < 1 % ; +; -- Logic LABs ; 3 ; ; ; -- Memory LABs (up to half of total LABs) ; 0 ; ; ; ; ; ; -; Combinational ALUT usage for logic ; 86 ; ; -; -- 7 input functions ; 3 ; ; -; -- 6 input functions ; 23 ; ; -; -- 5 input functions ; 41 ; ; -; -- 4 input functions ; 9 ; ; -; -- <=3 input functions ; 10 ; ; +; Combinational ALUT usage for logic ; 33 ; ; +; -- 7 input functions ; 1 ; ; +; -- 6 input functions ; 13 ; ; +; -- 5 input functions ; 5 ; ; +; -- 4 input functions ; 6 ; ; +; -- <=3 input functions ; 8 ; ; ; Combinational ALUT usage for route-throughs ; 0 ; ; ; ; ; ; ; Dedicated logic registers ; 0 ; ; @@ -239,7 +253,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- Routing optimization registers ; 0 ; ; ; ; ; ; ; Virtual pins ; 0 ; ; -; I/O pins ; 30 / 364 ; 8 % ; +; I/O pins ; 17 / 364 ; 5 % ; ; -- Clock pins ; 2 / 14 ; 14 % ; ; -- Dedicated input pins ; 0 / 23 ; 0 % ; ; ; ; ; @@ -270,12 +284,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Channel PLLs ; 0 / 6 ; 0 % ; ; Impedance control blocks ; 0 / 3 ; 0 % ; ; Hard Memory Controllers ; 0 / 2 ; 0 % ; -; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; -; Peak interconnect usage (total/H/V) ; 1.0% / 0.9% / 1.3% ; ; -; Maximum fan-out ; 29 ; ; -; Highest non-global fan-out ; 29 ; ; -; Total fan-out ; 462 ; ; -; Average fan-out ; 3.16 ; ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; ; +; Peak interconnect usage (total/H/V) ; 0.4% / 0.4% / 0.5% ; ; +; Maximum fan-out ; 15 ; ; +; Highest non-global fan-out ; 15 ; ; +; Total fan-out ; 173 ; ; +; Average fan-out ; 2.58 ; ; +-------------------------------------------------------------+--------------------+-------+ @@ -284,14 +298,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------------------------------------------------------------+----------------------+--------------------------------+ ; Statistic ; Top ; hard_block:auto_generated_inst ; +-------------------------------------------------------------+----------------------+--------------------------------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 48 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; -; ALMs needed [=A-B+C] ; 48 ; 0 ; -; [A] ALMs used in final placement [=a+b+c+d] ; 50 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; Logic utilization (ALMs needed / total ALMs on device) ; 21 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 21 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 21 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; ; [a] ALMs used for LUT logic and registers ; 0 ; 0 ; -; [b] ALMs used for LUT logic ; 50 ; 0 ; +; [b] ALMs used for LUT logic ; 21 ; 0 ; ; [c] ALMs used for registers ; 0 ; 0 ; ; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; -; [B] Estimate of ALMs recoverable by dense packing ; 2 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; ; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; ; [a] Due to location constrained logic ; 0 ; 0 ; ; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; @@ -300,16 +314,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; ; ; ; ; Difficulty packing design ; Low ; Low ; ; ; ; ; -; Total LABs: partially or completely used ; 7 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ; -; -- Logic LABs ; 7 ; 0 ; +; Total LABs: partially or completely used ; 3 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ; +; -- Logic LABs ; 3 ; 0 ; ; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; ; ; ; ; -; Combinational ALUT usage for logic ; 86 ; 0 ; -; -- 7 input functions ; 3 ; 0 ; -; -- 6 input functions ; 23 ; 0 ; -; -- 5 input functions ; 41 ; 0 ; -; -- 4 input functions ; 9 ; 0 ; -; -- <=3 input functions ; 10 ; 0 ; +; Combinational ALUT usage for logic ; 33 ; 0 ; +; -- 7 input functions ; 1 ; 0 ; +; -- 6 input functions ; 13 ; 0 ; +; -- 5 input functions ; 5 ; 0 ; +; -- 4 input functions ; 6 ; 0 ; +; -- <=3 input functions ; 8 ; 0 ; ; Combinational ALUT usage for route-throughs ; 0 ; 0 ; ; Memory ALUT usage ; 0 ; 0 ; ; -- 64-address deep ; 0 ; 0 ; @@ -325,7 +339,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; ; ; ; ; ; ; ; ; Virtual pins ; 0 ; 0 ; -; I/O pins ; 30 ; 0 ; +; I/O pins ; 17 ; 0 ; ; I/O registers ; 0 ; 0 ; ; Total block memory bits ; 0 ; 0 ; ; Total block memory implementation bits ; 0 ; 0 ; @@ -337,7 +351,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- Registered Output Connections ; 0 ; 0 ; ; ; ; ; ; Internal Connections ; ; ; -; -- Total Connections ; 462 ; 0 ; +; -- Total Connections ; 173 ; 0 ; ; -- Registered Connections ; 0 ; 0 ; ; ; ; ; ; External Connections ; ; ; @@ -345,8 +359,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; -- hard_block:auto_generated_inst ; 0 ; 0 ; ; ; ; ; ; Partition Interface ; ; ; -; -- Input Ports ; 22 ; 0 ; -; -- Output Ports ; 8 ; 0 ; +; -- Input Ports ; 13 ; 0 ; +; -- Output Ports ; 4 ; 0 ; ; -- Bidir Ports ; 0 ; 0 ; ; ; ; ; ; Registered Ports ; ; ; @@ -370,28 +384,19 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ -; A[0] ; N24 ; 6A ; 68 ; 33 ; 3 ; 11 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[1] ; R26 ; 5B ; 68 ; 24 ; 20 ; 11 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[2] ; H25 ; 6A ; 68 ; 35 ; 54 ; 11 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[3] ; AB26 ; 5B ; 68 ; 22 ; 77 ; 13 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[4] ; Y26 ; 5B ; 68 ; 24 ; 54 ; 13 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[5] ; W25 ; 5B ; 68 ; 26 ; 37 ; 13 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[6] ; Y25 ; 5B ; 68 ; 24 ; 37 ; 15 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[7] ; N25 ; 5B ; 68 ; 27 ; 3 ; 24 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; B[0] ; U25 ; 5B ; 68 ; 27 ; 37 ; 18 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; B[1] ; M24 ; 6A ; 68 ; 33 ; 20 ; 19 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; B[2] ; AA26 ; 5B ; 68 ; 22 ; 94 ; 22 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; C[0] ; W26 ; 5B ; 68 ; 26 ; 54 ; 15 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; C[1] ; G26 ; 6A ; 68 ; 33 ; 54 ; 16 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; C[2] ; P21 ; 5B ; 68 ; 26 ; 3 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; C[3] ; G25 ; 6A ; 68 ; 35 ; 37 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; C[4] ; J25 ; 6A ; 68 ; 32 ; 77 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; C[5] ; G24 ; 6A ; 68 ; 41 ; 54 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; C[6] ; R20 ; 5B ; 68 ; 22 ; 43 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; C[7] ; M21 ; 6A ; 68 ; 32 ; 60 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[0] ; P26 ; 5B ; 68 ; 27 ; 20 ; 18 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[1] ; J26 ; 6A ; 68 ; 32 ; 94 ; 14 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[2] ; P22 ; 5B ; 68 ; 26 ; 20 ; 29 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[0] ; P11 ; 3B ; 21 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; A[1] ; P12 ; 3B ; 21 ; 0 ; 17 ; 12 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; A[2] ; Y15 ; 4A ; 46 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; A[3] ; Y16 ; 4A ; 46 ; 0 ; 17 ; 15 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; B[0] ; AD13 ; 4A ; 34 ; 0 ; 34 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; B[1] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; B[2] ; AF6 ; 3B ; 21 ; 0 ; 51 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; Fitter ; no ; +; B[3] ; AE6 ; 3B ; 21 ; 0 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; Fitter ; no ; +; C[0] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 10 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; C[1] ; AE10 ; 4A ; 36 ; 0 ; 51 ; 10 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; op[0] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; op[1] ; Y11 ; 3B ; 10 ; 0 ; 57 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +; op[2] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ; +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ @@ -400,33 +405,29 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; +----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ -; OUT_1[0] ; F26 ; 6A ; 68 ; 33 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[1] ; N23 ; 6A ; 68 ; 35 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[2] ; D26 ; 6A ; 68 ; 37 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[3] ; U26 ; 5B ; 68 ; 27 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[4] ; N20 ; 6A ; 68 ; 32 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[5] ; M25 ; 6A ; 68 ; 37 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[6] ; T26 ; 5B ; 68 ; 24 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[7] ; M22 ; 6A ; 68 ; 35 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; OUT_1[1] ; F6 ; 8A ; 15 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; OUT_1[2] ; G6 ; 8A ; 15 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; OUT_1[3] ; G7 ; 8A ; 14 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ -+----------------------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+---------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; -+----------+------------------+---------------+--------------+---------------+ -; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 3B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 5B ; 15 / 32 ( 47 % ) ; 2.5V ; -- ; 2.5V ; -; 6A ; 15 / 48 ( 31 % ) ; 2.5V ; -- ; 2.5V ; -; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; -+----------+------------------+---------------+--------------+---------------+ ++---------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+-----------------+---------------+--------------+---------------+ +; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 8 / 32 ( 25 % ) ; 1.2V ; -- ; 2.5V ; +; 4A ; 5 / 80 ( 6 % ) ; 1.2V ; -- ; 2.5V ; +; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 4 / 32 ( 13 % ) ; 2.5V ; -- ; 2.5V ; ++----------+-----------------+---------------+--------------+---------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -467,7 +468,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; -; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA10 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -477,13 +478,13 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA20 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; AA24 ; 187 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; AA25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA26 ; 201 ; 5B ; B[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; AA26 ; 201 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; AB1 ; 21 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; ; AB2 ; 20 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; ; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -496,7 +497,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB13 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -509,7 +510,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AB23 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AB24 ; 176 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; AB25 ; 189 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB26 ; 199 ; 5B ; A[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; AB26 ; 199 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AC3 ; 18 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; @@ -517,15 +518,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; -; AC8 ; 62 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC9 ; 64 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC10 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC8 ; 62 ; 3B ; B[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; AC9 ; 64 ; 3B ; C[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; AC10 ; 59 ; 3B ; op[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; ; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC16 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -544,17 +545,17 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD9 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD13 ; 93 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD13 ; 93 ; 4A ; B[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AD15 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; ; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD19 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -567,23 +568,23 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; AE4 ; 23 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; AE5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AE6 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE6 ; 85 ; 3B ; B[3] ; input ; 1.2 V ; ; Column I/O ; N ; no ; Off ; ; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE10 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; 94 ; 4A ; C[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE12 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AE18 ; 117 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 125 ; 4A ; op[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE22 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -592,7 +593,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AF5 ; 37 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; -; AF6 ; 83 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF6 ; 83 ; 3B ; B[2] ; input ; 1.2 V ; ; Column I/O ; N ; no ; Off ; ; AF7 ; 80 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF8 ; 78 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF9 ; 75 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -601,7 +602,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF15 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -689,7 +690,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; D23 ; 262 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; ; D24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; D25 ; 251 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D26 ; 227 ; 6A ; OUT_1[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; D26 ; 227 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; E1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; E3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; @@ -721,8 +722,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; F5 ; 398 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; F6 ; 360 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F7 ; 366 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F6 ; 360 ; 8A ; OUT_1[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F7 ; 366 ; 8A ; OUT_1[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; ; F8 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; ; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -741,14 +742,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; F23 ; 243 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; F24 ; 235 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; F25 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; F26 ; 219 ; 6A ; OUT_1[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F26 ; 219 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; G1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; G2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; G3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; G4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; G5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; G6 ; 362 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G7 ; 364 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G6 ; 362 ; 8A ; OUT_1[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G7 ; 364 ; 8A ; OUT_1[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; ; G8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; G9 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; G10 ; 357 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -765,9 +766,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; G21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; G22 ; 245 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; G23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; G24 ; 237 ; 6A ; C[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; G25 ; 223 ; 6A ; C[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; G26 ; 221 ; 6A ; C[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G24 ; 237 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G25 ; 223 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 221 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; H1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; H2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -792,7 +793,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; H22 ; 242 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; H23 ; 239 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; H24 ; 241 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H25 ; 225 ; 6A ; A[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H25 ; 225 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; H26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -818,8 +819,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; J22 ; ; 6A ; VCCPD6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; J23 ; 244 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; J24 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J25 ; 215 ; 6A ; C[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; J26 ; 217 ; 6A ; op[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J25 ; 215 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 217 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; K1 ; 2 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; K2 ; 3 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -892,11 +893,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; M18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M20 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; -; M21 ; 216 ; 6A ; C[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M22 ; 224 ; 6A ; OUT_1[7] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M21 ; 216 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 224 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; M23 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; M24 ; 220 ; 6A ; B[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M25 ; 226 ; 6A ; OUT_1[5] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M24 ; 220 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M25 ; 226 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; M26 ; 228 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -917,12 +918,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; N17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; N18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; -; N20 ; 214 ; 6A ; OUT_1[4] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N20 ; 214 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; N21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N22 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; N23 ; 222 ; 6A ; OUT_1[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N24 ; 218 ; 6A ; A[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N25 ; 210 ; 5B ; A[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N23 ; 222 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N24 ; 218 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N25 ; 210 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; N26 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; P1 ; 6 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; P2 ; 7 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; @@ -934,8 +935,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; P8 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; P10 ; 74 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; P11 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; P12 ; 82 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 84 ; 3B ; A[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; P12 ; 82 ; 3B ; A[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; P14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; P15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -944,12 +945,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; P18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; P20 ; 200 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P21 ; 206 ; 5B ; C[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; P22 ; 208 ; 5B ; op[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; P21 ; 206 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 208 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; P23 ; 192 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; P24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; P25 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; -; P26 ; 212 ; 5B ; op[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; P26 ; 212 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; R3 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -969,13 +970,13 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; R17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; R18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; R19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; -; R20 ; 198 ; 5B ; C[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; R20 ; 198 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; R21 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; R22 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; R23 ; 190 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; R24 ; 194 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; R25 ; 196 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R26 ; 204 ; 5B ; A[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; R26 ; 204 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; T1 ; 9 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; ; T2 ; 8 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; ; T3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -1001,7 +1002,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; T23 ; 186 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; T24 ; 188 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; T25 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; T26 ; 202 ; 5B ; OUT_1[6] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; T26 ; 202 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; U3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; @@ -1009,7 +1010,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; ; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U8 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1019,15 +1020,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U18 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; U22 ; 177 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; U24 ; 195 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U25 ; 211 ; 5B ; B[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; U26 ; 213 ; 5B ; OUT_1[3] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; U25 ; 211 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; 213 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; V1 ; 13 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; ; V2 ; 12 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; ; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -1038,7 +1039,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V11 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1067,7 +1068,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W14 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1078,8 +1079,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; W22 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; ; W23 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; ; W24 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W25 ; 207 ; 5B ; A[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; W26 ; 209 ; 5B ; C[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; W25 ; 207 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W26 ; 209 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; Y1 ; 17 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; ; Y2 ; 16 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; ; Y3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -1090,13 +1091,13 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 55 ; 3B ; op[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; ; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y15 ; 116 ; 4A ; A[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; Y16 ; 114 ; 4A ; A[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ; +; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1104,8 +1105,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; Y24 ; 180 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y25 ; 203 ; 5B ; A[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; Y26 ; 205 ; 5B ; A[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; Y25 ; 203 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y26 ; 205 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. @@ -1119,62 +1120,8 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; OUT_1[1] ; Incomplete set of assignments ; ; OUT_1[2] ; Incomplete set of assignments ; ; OUT_1[3] ; Incomplete set of assignments ; -; OUT_1[4] ; Incomplete set of assignments ; -; OUT_1[5] ; Incomplete set of assignments ; -; OUT_1[6] ; Incomplete set of assignments ; -; OUT_1[7] ; Incomplete set of assignments ; -; op[0] ; Incomplete set of assignments ; -; A[0] ; Incomplete set of assignments ; -; op[2] ; Incomplete set of assignments ; -; op[1] ; Incomplete set of assignments ; -; C[2] ; Incomplete set of assignments ; -; C[3] ; Incomplete set of assignments ; -; C[4] ; Incomplete set of assignments ; -; C[5] ; Incomplete set of assignments ; -; C[6] ; Incomplete set of assignments ; -; C[7] ; Incomplete set of assignments ; -; A[7] ; Incomplete set of assignments ; -; C[0] ; Incomplete set of assignments ; -; C[1] ; Incomplete set of assignments ; -; A[6] ; Incomplete set of assignments ; -; A[4] ; Incomplete set of assignments ; -; A[5] ; Incomplete set of assignments ; -; A[2] ; Incomplete set of assignments ; -; A[1] ; Incomplete set of assignments ; -; A[3] ; Incomplete set of assignments ; -; B[2] ; Incomplete set of assignments ; -; B[0] ; Incomplete set of assignments ; -; B[1] ; Incomplete set of assignments ; -; OUT_1[0] ; Missing location assignment ; -; OUT_1[1] ; Missing location assignment ; -; OUT_1[2] ; Missing location assignment ; -; OUT_1[3] ; Missing location assignment ; -; OUT_1[4] ; Missing location assignment ; -; OUT_1[5] ; Missing location assignment ; -; OUT_1[6] ; Missing location assignment ; -; OUT_1[7] ; Missing location assignment ; -; op[0] ; Missing location assignment ; -; A[0] ; Missing location assignment ; -; op[2] ; Missing location assignment ; -; op[1] ; Missing location assignment ; -; C[2] ; Missing location assignment ; -; C[3] ; Missing location assignment ; -; C[4] ; Missing location assignment ; -; C[5] ; Missing location assignment ; -; C[6] ; Missing location assignment ; -; C[7] ; Missing location assignment ; -; A[7] ; Missing location assignment ; -; C[0] ; Missing location assignment ; -; C[1] ; Missing location assignment ; -; A[6] ; Missing location assignment ; -; A[4] ; Missing location assignment ; -; A[5] ; Missing location assignment ; -; A[2] ; Missing location assignment ; -; A[1] ; Missing location assignment ; -; A[3] ; Missing location assignment ; ; B[2] ; Missing location assignment ; -; B[0] ; Missing location assignment ; -; B[1] ; Missing location assignment ; +; B[3] ; Missing location assignment ; +----------+-------------------------------+ @@ -1183,7 +1130,7 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ -; |shifter ; 48.0 (48.0) ; 50.0 (50.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 86 (86) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 30 ; 0 ; |shifter ; shifter ; work ; +; |shifter ; 20.5 (20.5) ; 20.5 (20.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 17 ; 0 ; |shifter ; shifter ; work ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -1197,32 +1144,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; OUT_1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; OUT_1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; OUT_1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; OUT_1[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; A[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; op[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; op[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; C[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; C[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; C[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; C[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; C[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; C[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; C[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; C[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ @@ -1231,336 +1165,164 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------+-------------------+---------+ ; Source Pin / Fanout ; Pad To Core Index ; Setting ; +----------------------+-------------------+---------+ -; op[0] ; ; ; -; - Mux3~2 ; 0 ; 0 ; -; - Mux4~2 ; 0 ; 0 ; -; - Mux7~2 ; 0 ; 0 ; -; - Mux5~1 ; 0 ; 0 ; -; - Mux5~2 ; 0 ; 0 ; -; - Mux5~3 ; 0 ; 0 ; -; - Mux5~4 ; 0 ; 0 ; -; - Mux5~5 ; 0 ; 0 ; -; - Mux6~1 ; 0 ; 0 ; -; - Mux4~1 ; 0 ; 0 ; -; - Mux3~1 ; 0 ; 0 ; -; - Mux1~0 ; 0 ; 0 ; -; - Mux1~2 ; 0 ; 0 ; -; - Mux1~3 ; 0 ; 0 ; -; - Mux1~4 ; 0 ; 0 ; -; - Mux1~5 ; 0 ; 0 ; -; - Mux1~6 ; 0 ; 0 ; -; - Mux0~0 ; 0 ; 0 ; ; A[0] ; ; ; -; - ShiftRight1~1 ; 0 ; 0 ; -; - ShiftRight3~1 ; 0 ; 0 ; -; - Mux7~2 ; 0 ; 0 ; -; - ShiftLeft1~0 ; 0 ; 0 ; -; - ShiftLeft0~1 ; 0 ; 0 ; -; - ShiftLeft1~1 ; 0 ; 0 ; -; - ShiftLeft0~2 ; 0 ; 0 ; -; - ShiftLeft0~3 ; 0 ; 0 ; -; - ShiftLeft1~2 ; 0 ; 0 ; -; - ShiftLeft0~5 ; 0 ; 0 ; -; - ShiftLeft1~5 ; 0 ; 0 ; -; op[2] ; ; ; +; - ShiftRight3~0 ; 0 ; 0 ; +; - ShiftRight1~0 ; 0 ; 0 ; ; - Mux3~2 ; 0 ; 0 ; -; - Mux4~2 ; 0 ; 0 ; -; - Mux7~3 ; 0 ; 0 ; -; - Mux7~2 ; 0 ; 0 ; -; - Mux5~0 ; 0 ; 0 ; -; - Mux5~1 ; 0 ; 0 ; -; - Mux5~2 ; 0 ; 0 ; -; - Mux5~3 ; 0 ; 0 ; -; - Mux5~4 ; 0 ; 0 ; -; - Mux5~5 ; 0 ; 0 ; -; - Mux6~1 ; 0 ; 0 ; -; - Mux5~6 ; 0 ; 0 ; -; - Mux5~7 ; 0 ; 0 ; -; - Mux6~3 ; 0 ; 0 ; -; - Mux6~4 ; 0 ; 0 ; -; - Mux5~10 ; 0 ; 0 ; -; - Mux5~11 ; 0 ; 0 ; -; - Mux4~0 ; 0 ; 0 ; -; - Mux3~0 ; 0 ; 0 ; +; - ShiftLeft0~0 ; 0 ; 0 ; +; - ShiftLeft1~1 ; 0 ; 0 ; +; - ShiftLeft0~1 ; 0 ; 0 ; +; - ShiftLeft1~2 ; 0 ; 0 ; +; - ShiftLeft0~2 ; 0 ; 0 ; +; - ShiftLeft1~3 ; 0 ; 0 ; +; op[0] ; ; ; +; - Mux0~2 ; 0 ; 0 ; +; - Mux3~1 ; 0 ; 0 ; +; - Mux3~2 ; 0 ; 0 ; +; - Mux2~0 ; 0 ; 0 ; +; - Mux2~4 ; 0 ; 0 ; +; - Mux2~5 ; 0 ; 0 ; ; - Mux1~0 ; 0 ; 0 ; ; - Mux1~1 ; 0 ; 0 ; -; - Mux1~2 ; 0 ; 0 ; -; - Mux1~3 ; 0 ; 0 ; -; - Mux1~4 ; 0 ; 0 ; -; - Mux1~5 ; 0 ; 0 ; -; - Mux1~6 ; 0 ; 0 ; -; - Mux2~2 ; 0 ; 0 ; -; - Mux1~9 ; 0 ; 0 ; -; - Mux0~0 ; 0 ; 0 ; -; op[1] ; ; ; -; - Mux7~3 ; 1 ; 0 ; -; - Mux7~0 ; 1 ; 0 ; -; - Mux5~1 ; 1 ; 0 ; -; - Mux5~4 ; 1 ; 0 ; -; - Mux5~5 ; 1 ; 0 ; -; - Mux6~1 ; 1 ; 0 ; -; - Mux4~1 ; 1 ; 0 ; -; - Mux3~1 ; 1 ; 0 ; -; - Mux1~0 ; 1 ; 0 ; -; - Mux1~1 ; 1 ; 0 ; -; - Mux1~4 ; 1 ; 0 ; -; - Mux1~5 ; 1 ; 0 ; -; - Mux1~6 ; 1 ; 0 ; -; - Mux0~1 ; 1 ; 0 ; -; C[2] ; ; ; -; - Mux7~0 ; 1 ; 0 ; -; - ShiftRight0~0 ; 1 ; 0 ; -; - Mux5~2 ; 1 ; 0 ; -; - Mux5~3 ; 1 ; 0 ; -; - ShiftRight0~3 ; 1 ; 0 ; -; - ShiftLeft0~5 ; 1 ; 0 ; -; - Mux1~2 ; 1 ; 0 ; -; - Mux1~3 ; 1 ; 0 ; -; - ShiftLeft0~7 ; 1 ; 0 ; -; C[3] ; ; ; -; - ShiftLeft0~0 ; 1 ; 0 ; -; - ShiftRight0~0 ; 1 ; 0 ; -; C[4] ; ; ; -; - ShiftLeft0~0 ; 1 ; 0 ; -; - ShiftRight0~0 ; 1 ; 0 ; -; C[5] ; ; ; -; - ShiftLeft0~0 ; 1 ; 0 ; -; - ShiftRight0~0 ; 1 ; 0 ; -; C[6] ; ; ; -; - ShiftLeft0~0 ; 1 ; 0 ; -; - ShiftRight0~0 ; 1 ; 0 ; -; C[7] ; ; ; -; - ShiftLeft0~0 ; 0 ; 0 ; -; - ShiftRight0~0 ; 0 ; 0 ; -; A[7] ; ; ; -; - ShiftRight1~0 ; 0 ; 0 ; -; - Mux7~0 ; 0 ; 0 ; -; - ShiftRight3~0 ; 0 ; 0 ; -; - ShiftRight0~1 ; 0 ; 0 ; -; - ShiftRight2~0 ; 0 ; 0 ; -; - Mux6~3 ; 0 ; 0 ; -; - ShiftRight1~3 ; 0 ; 0 ; -; - Mux6~4 ; 0 ; 0 ; -; - ShiftRight0~2 ; 0 ; 0 ; -; - ShiftRight2~1 ; 0 ; 0 ; -; - Mux5~10 ; 0 ; 0 ; -; - ShiftRight1~4 ; 0 ; 0 ; -; - Mux5~11 ; 0 ; 0 ; -; - ShiftRight0~3 ; 0 ; 0 ; -; - ShiftRight2~2 ; 0 ; 0 ; -; - Mux4~0 ; 0 ; 0 ; -; - Mux3~0 ; 0 ; 0 ; -; - Mux2~2 ; 0 ; 0 ; -; - Mux1~9 ; 0 ; 0 ; -; - ShiftLeft0~6 ; 0 ; 0 ; -; - ShiftRight0~4 ; 0 ; 0 ; -; - ShiftLeft1~6 ; 0 ; 0 ; -; - ShiftRight2~4 ; 0 ; 0 ; -; - Mux0~1 ; 0 ; 0 ; -; C[0] ; ; ; -; - ShiftRight1~0 ; 1 ; 0 ; -; - ShiftRight1~1 ; 1 ; 0 ; -; - ShiftRight1~2 ; 1 ; 0 ; -; - Mux5~0 ; 1 ; 0 ; -; - ShiftRight0~1 ; 1 ; 0 ; -; - ShiftLeft0~1 ; 1 ; 0 ; -; - Mux5~7 ; 1 ; 0 ; -; - ShiftRight1~3 ; 1 ; 0 ; -; - ShiftRight0~2 ; 1 ; 0 ; -; - ShiftLeft0~2 ; 1 ; 0 ; -; - ShiftRight1~4 ; 1 ; 0 ; -; - ShiftLeft0~3 ; 1 ; 0 ; -; - ShiftRight1~5 ; 1 ; 0 ; -; - ShiftLeft0~4 ; 1 ; 0 ; -; - ShiftLeft0~6 ; 1 ; 0 ; -; C[1] ; ; ; -; - ShiftRight1~0 ; 1 ; 0 ; -; - ShiftRight1~1 ; 1 ; 0 ; -; - ShiftRight1~2 ; 1 ; 0 ; -; - Mux5~0 ; 1 ; 0 ; -; - ShiftRight0~1 ; 1 ; 0 ; -; - ShiftLeft0~1 ; 1 ; 0 ; -; - Mux5~6 ; 1 ; 0 ; -; - ShiftRight1~3 ; 1 ; 0 ; -; - ShiftRight0~2 ; 1 ; 0 ; -; - ShiftLeft0~2 ; 1 ; 0 ; -; - ShiftRight1~4 ; 1 ; 0 ; -; - ShiftLeft0~3 ; 1 ; 0 ; -; - ShiftRight1~5 ; 1 ; 0 ; -; - ShiftLeft0~4 ; 1 ; 0 ; -; - Mux1~0 ; 1 ; 0 ; -; - ShiftLeft0~6 ; 1 ; 0 ; -; A[6] ; ; ; -; - ShiftRight1~0 ; 1 ; 0 ; -; - ShiftRight3~0 ; 1 ; 0 ; -; - ShiftRight0~1 ; 1 ; 0 ; -; - ShiftRight2~0 ; 1 ; 0 ; -; - Mux6~3 ; 1 ; 0 ; -; - ShiftRight1~3 ; 1 ; 0 ; -; - ShiftRight0~2 ; 1 ; 0 ; -; - ShiftRight2~1 ; 1 ; 0 ; -; - Mux5~10 ; 1 ; 0 ; -; - ShiftRight1~4 ; 1 ; 0 ; -; - ShiftRight1~5 ; 1 ; 0 ; -; - ShiftRight3~2 ; 1 ; 0 ; -; - Mux1~11 ; 1 ; 0 ; -; - ShiftLeft0~6 ; 1 ; 0 ; -; - ShiftLeft1~6 ; 1 ; 0 ; -; A[4] ; ; ; -; - ShiftRight1~0 ; 1 ; 0 ; -; - ShiftRight3~0 ; 1 ; 0 ; -; - Mux6~2 ; 1 ; 0 ; -; - Mux5~9 ; 1 ; 0 ; -; - ShiftRight1~5 ; 1 ; 0 ; -; - ShiftRight3~2 ; 1 ; 0 ; -; - ShiftLeft0~4 ; 1 ; 0 ; -; - ShiftLeft1~4 ; 1 ; 0 ; -; - Mux3~1 ; 1 ; 0 ; -; - Mux2~1 ; 1 ; 0 ; -; - Mux1~8 ; 1 ; 0 ; -; - ShiftLeft0~6 ; 1 ; 0 ; -; - ShiftLeft1~6 ; 1 ; 0 ; -; A[5] ; ; ; -; - ShiftRight1~0 ; 1 ; 0 ; -; - ShiftRight3~0 ; 1 ; 0 ; -; - ShiftRight0~1 ; 1 ; 0 ; -; - ShiftRight2~0 ; 1 ; 0 ; -; - Mux6~3 ; 1 ; 0 ; -; - ShiftRight1~3 ; 1 ; 0 ; -; - Mux5~9 ; 1 ; 0 ; -; - ShiftRight1~5 ; 1 ; 0 ; -; - ShiftRight3~2 ; 1 ; 0 ; -; - Mux2~4 ; 1 ; 0 ; -; - Mux1~8 ; 1 ; 0 ; -; - ShiftLeft0~6 ; 1 ; 0 ; -; - ShiftLeft1~6 ; 1 ; 0 ; -; A[2] ; ; ; -; - ShiftRight1~1 ; 1 ; 0 ; -; - ShiftRight3~1 ; 1 ; 0 ; -; - Mux6~2 ; 1 ; 0 ; -; - ShiftLeft1~1 ; 1 ; 0 ; -; - ShiftLeft0~2 ; 1 ; 0 ; -; - Mux5~13 ; 1 ; 0 ; -; - ShiftLeft0~3 ; 1 ; 0 ; -; - ShiftLeft1~2 ; 1 ; 0 ; -; - ShiftLeft0~4 ; 1 ; 0 ; -; - ShiftLeft1~4 ; 1 ; 0 ; -; - Mux2~1 ; 1 ; 0 ; -; A[1] ; ; ; -; - ShiftRight1~1 ; 0 ; 0 ; -; - ShiftRight3~1 ; 0 ; 0 ; -; - ShiftLeft1~0 ; 0 ; 0 ; -; - ShiftLeft0~1 ; 0 ; 0 ; -; - Mux6~6 ; 0 ; 0 ; -; - ShiftLeft1~1 ; 0 ; 0 ; -; - ShiftLeft0~2 ; 0 ; 0 ; -; - ShiftLeft0~3 ; 0 ; 0 ; -; - ShiftLeft1~2 ; 0 ; 0 ; -; - ShiftLeft0~4 ; 0 ; 0 ; -; - ShiftLeft1~4 ; 0 ; 0 ; -; A[3] ; ; ; -; - ShiftRight1~1 ; 1 ; 0 ; -; - ShiftRight3~1 ; 1 ; 0 ; -; - Mux6~2 ; 1 ; 0 ; -; - Mux5~9 ; 1 ; 0 ; -; - ShiftLeft0~3 ; 1 ; 0 ; -; - ShiftRight1~5 ; 1 ; 0 ; -; - ShiftLeft1~2 ; 1 ; 0 ; -; - ShiftRight3~2 ; 1 ; 0 ; -; - Mux4~1 ; 1 ; 0 ; -; - ShiftLeft0~4 ; 1 ; 0 ; -; - ShiftLeft1~4 ; 1 ; 0 ; -; - Mux2~1 ; 1 ; 0 ; -; - Mux1~8 ; 1 ; 0 ; -; B[2] ; ; ; -; - Mux7~1 ; 1 ; 0 ; -; - Mux5~1 ; 1 ; 0 ; -; - Mux5~3 ; 1 ; 0 ; -; - Mux5~4 ; 1 ; 0 ; -; - Mux5~5 ; 1 ; 0 ; -; - Mux6~1 ; 1 ; 0 ; -; - ShiftLeft1~3 ; 1 ; 0 ; -; - ShiftRight2~2 ; 1 ; 0 ; -; - Mux4~0 ; 1 ; 0 ; -; - ShiftLeft1~5 ; 1 ; 0 ; -; - ShiftRight2~3 ; 1 ; 0 ; +; op[2] ; ; ; +; - Mux0~2 ; 1 ; 0 ; ; - Mux3~0 ; 1 ; 0 ; +; - Mux3~1 ; 1 ; 0 ; +; - Mux2~0 ; 1 ; 0 ; +; - Mux2~3 ; 1 ; 0 ; +; - Mux2~4 ; 1 ; 0 ; +; - Mux1~0 ; 1 ; 0 ; ; - Mux1~1 ; 1 ; 0 ; -; - Mux1~2 ; 1 ; 0 ; -; - Mux1~4 ; 1 ; 0 ; -; - Mux1~5 ; 1 ; 0 ; -; - Mux1~6 ; 1 ; 0 ; -; - Mux2~2 ; 1 ; 0 ; -; - Mux1~9 ; 1 ; 0 ; -; - ShiftLeft1~7 ; 1 ; 0 ; -; - ShiftRight2~4 ; 1 ; 0 ; -; - Mux7~3 ; 1 ; 0 ; -; B[0] ; ; ; -; - Mux7~3 ; 1 ; 0 ; -; - ShiftRight3~0 ; 1 ; 0 ; -; - ShiftRight3~1 ; 1 ; 0 ; -; - Mux5~0 ; 1 ; 0 ; -; - ShiftLeft1~0 ; 1 ; 0 ; +; op[1] ; ; ; +; - Mux3~0 ; 0 ; 0 ; +; - Mux0~0 ; 0 ; 0 ; +; - Mux2~5 ; 0 ; 0 ; +; - Mux1~2 ; 0 ; 0 ; +; - Mux0~1 ; 0 ; 0 ; +; C[1] ; ; ; +; - ShiftRight0~0 ; 0 ; 0 ; +; - ShiftRight1~0 ; 0 ; 0 ; +; - ShiftLeft0~0 ; 0 ; 0 ; +; - ShiftRight0~1 ; 0 ; 0 ; +; - Mux2~1 ; 0 ; 0 ; +; - Mux2~4 ; 0 ; 0 ; +; - ShiftLeft0~1 ; 0 ; 0 ; +; - ShiftRight0~2 ; 0 ; 0 ; +; - ShiftLeft0~2 ; 0 ; 0 ; +; - ShiftRight0~3 ; 0 ; 0 ; +; C[0] ; ; ; +; - ShiftRight0~0 ; 1 ; 0 ; +; - ShiftRight1~0 ; 1 ; 0 ; +; - ShiftLeft0~0 ; 1 ; 0 ; +; - ShiftRight0~1 ; 1 ; 0 ; +; - Mux2~1 ; 1 ; 0 ; +; - Mux2~4 ; 1 ; 0 ; +; - ShiftLeft0~1 ; 1 ; 0 ; +; - ShiftRight0~2 ; 1 ; 0 ; +; - ShiftLeft0~2 ; 1 ; 0 ; +; - ShiftRight0~3 ; 1 ; 0 ; +; B[2] ; ; ; ; - ShiftRight2~0 ; 1 ; 0 ; -; - Mux5~7 ; 1 ; 0 ; -; - Mux6~3 ; 1 ; 0 ; +; - ShiftLeft1~0 ; 1 ; 0 ; ; - ShiftLeft1~1 ; 1 ; 0 ; -; - ShiftRight2~1 ; 1 ; 0 ; -; - Mux5~10 ; 1 ; 0 ; -; - ShiftLeft1~2 ; 1 ; 0 ; -; - ShiftRight3~2 ; 1 ; 0 ; ; - ShiftRight2~2 ; 1 ; 0 ; -; - ShiftLeft1~4 ; 1 ; 0 ; -; - ShiftLeft1~5 ; 1 ; 0 ; -; - ShiftLeft1~6 ; 1 ; 0 ; -; - ShiftRight2~4 ; 1 ; 0 ; +; - ShiftRight2~3 ; 1 ; 0 ; +; B[3] ; ; ; +; - ShiftRight2~0 ; 1 ; 0 ; +; - ShiftLeft1~0 ; 1 ; 0 ; +; - ShiftLeft1~1 ; 1 ; 0 ; +; - ShiftRight2~2 ; 1 ; 0 ; +; - ShiftRight2~3 ; 1 ; 0 ; ; B[1] ; ; ; -; - Mux7~3 ; 0 ; 0 ; -; - ShiftRight3~0 ; 0 ; 0 ; -; - ShiftRight3~1 ; 0 ; 0 ; -; - Mux5~0 ; 0 ; 0 ; -; - ShiftLeft1~0 ; 0 ; 0 ; ; - ShiftRight2~0 ; 0 ; 0 ; -; - Mux5~6 ; 0 ; 0 ; -; - Mux6~3 ; 0 ; 0 ; +; - ShiftRight3~0 ; 0 ; 0 ; ; - ShiftLeft1~1 ; 0 ; 0 ; ; - ShiftRight2~1 ; 0 ; 0 ; -; - Mux5~10 ; 0 ; 0 ; +; - Mux2~3 ; 0 ; 0 ; ; - ShiftLeft1~2 ; 0 ; 0 ; -; - ShiftRight3~2 ; 0 ; 0 ; ; - ShiftRight2~2 ; 0 ; 0 ; -; - ShiftLeft1~4 ; 0 ; 0 ; -; - ShiftLeft1~5 ; 0 ; 0 ; -; - Mux1~0 ; 0 ; 0 ; -; - ShiftLeft1~6 ; 0 ; 0 ; -; - ShiftRight2~4 ; 0 ; 0 ; +; - ShiftLeft1~3 ; 0 ; 0 ; +; - ShiftRight2~3 ; 0 ; 0 ; +; B[0] ; ; ; +; - ShiftRight2~0 ; 1 ; 0 ; +; - ShiftRight3~0 ; 1 ; 0 ; +; - ShiftLeft1~1 ; 1 ; 0 ; +; - ShiftRight2~1 ; 1 ; 0 ; +; - Mux2~2 ; 1 ; 0 ; +; - ShiftLeft1~2 ; 1 ; 0 ; +; - ShiftRight2~2 ; 1 ; 0 ; +; - ShiftLeft1~3 ; 1 ; 0 ; +; - ShiftRight2~3 ; 1 ; 0 ; +; A[2] ; ; ; +; - ShiftRight3~0 ; 1 ; 0 ; +; - ShiftRight1~0 ; 1 ; 0 ; +; - ShiftRight0~1 ; 1 ; 0 ; +; - ShiftRight2~1 ; 1 ; 0 ; +; - Mux2~1 ; 1 ; 0 ; +; - Mux2~2 ; 1 ; 0 ; +; - ShiftLeft0~1 ; 1 ; 0 ; +; - ShiftRight0~2 ; 1 ; 0 ; +; - ShiftLeft1~2 ; 1 ; 0 ; +; - ShiftRight2~2 ; 1 ; 0 ; +; - Mux1~1 ; 1 ; 0 ; +; - ShiftLeft0~2 ; 1 ; 0 ; +; - ShiftLeft1~3 ; 1 ; 0 ; +; A[1] ; ; ; +; - ShiftRight3~0 ; 1 ; 0 ; +; - ShiftRight1~0 ; 1 ; 0 ; +; - ShiftLeft0~0 ; 1 ; 0 ; +; - ShiftRight0~1 ; 1 ; 0 ; +; - ShiftLeft1~1 ; 1 ; 0 ; +; - ShiftRight2~1 ; 1 ; 0 ; +; - Mux2~2 ; 1 ; 0 ; +; - Mux2~4 ; 1 ; 0 ; +; - ShiftLeft0~1 ; 1 ; 0 ; +; - ShiftLeft1~2 ; 1 ; 0 ; +; - ShiftLeft0~2 ; 1 ; 0 ; +; - ShiftLeft1~3 ; 1 ; 0 ; +; A[3] ; ; ; +; - ShiftRight3~0 ; 0 ; 0 ; +; - ShiftRight1~0 ; 0 ; 0 ; +; - Mux0~0 ; 0 ; 0 ; +; - ShiftRight0~1 ; 0 ; 0 ; +; - ShiftRight2~1 ; 0 ; 0 ; +; - Mux2~1 ; 0 ; 0 ; +; - Mux2~3 ; 0 ; 0 ; +; - ShiftRight0~2 ; 0 ; 0 ; +; - ShiftRight2~2 ; 0 ; 0 ; +; - Mux1~1 ; 0 ; 0 ; +; - ShiftLeft0~2 ; 0 ; 0 ; +; - ShiftRight0~3 ; 0 ; 0 ; +; - ShiftLeft1~3 ; 0 ; 0 ; +; - ShiftRight2~3 ; 0 ; 0 ; +; - Mux0~1 ; 0 ; 0 ; +----------------------+-------------------+---------+ -+--------------------------------------------------------+ -; Routing Usage Summary ; -+------------------------------+-------------------------+ -; Routing Resource Type ; Usage ; -+------------------------------+-------------------------+ -; Block interconnects ; 142 / 217,884 ( < 1 % ) ; -; C12 interconnects ; 3 / 10,080 ( < 1 % ) ; -; C2 interconnects ; 44 / 87,208 ( < 1 % ) ; -; C4 interconnects ; 22 / 41,360 ( < 1 % ) ; -; DQS bus muxes ; 0 / 21 ( 0 % ) ; -; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; -; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; -; Direct links ; 18 / 217,884 ( < 1 % ) ; -; Global clocks ; 0 / 16 ( 0 % ) ; -; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; -; Local interconnects ; 36 / 58,160 ( < 1 % ) ; -; Quadrant clocks ; 0 / 88 ( 0 % ) ; -; R14 interconnects ; 10 / 9,228 ( < 1 % ) ; -; R14/C12 interconnect drivers ; 3 / 15,096 ( < 1 % ) ; -; R3 interconnects ; 66 / 94,896 ( < 1 % ) ; -; R6 interconnects ; 49 / 194,640 ( < 1 % ) ; -; Spine clocks ; 0 / 180 ( 0 % ) ; -; Wire stub REs ; 0 / 11,606 ( 0 % ) ; -+------------------------------+-------------------------+ ++-------------------------------------------------------+ +; Routing Usage Summary ; ++------------------------------+------------------------+ +; Routing Resource Type ; Usage ; ++------------------------------+------------------------+ +; Block interconnects ; 42 / 217,884 ( < 1 % ) ; +; C12 interconnects ; 8 / 10,080 ( < 1 % ) ; +; C2 interconnects ; 9 / 87,208 ( < 1 % ) ; +; C4 interconnects ; 57 / 41,360 ( < 1 % ) ; +; DQS bus muxes ; 0 / 21 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; +; Direct links ; 0 / 217,884 ( 0 % ) ; +; Global clocks ; 0 / 16 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; +; Local interconnects ; 22 / 58,160 ( < 1 % ) ; +; Quadrant clocks ; 0 / 88 ( 0 % ) ; +; R14 interconnects ; 10 / 9,228 ( < 1 % ) ; +; R14/C12 interconnect drivers ; 15 / 15,096 ( < 1 % ) ; +; R3 interconnects ; 24 / 94,896 ( < 1 % ) ; +; R6 interconnects ; 23 / 194,640 ( < 1 % ) ; +; Spine clocks ; 0 / 180 ( 0 % ) ; +; Wire stub REs ; 0 / 11,606 ( 0 % ) ; ++------------------------------+------------------------+ +------------------------------------------+ @@ -1569,10 +1331,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; I/O Rules Statistic ; Total ; +----------------------------------+-------+ ; Total I/O Rules ; 28 ; -; Number of I/O Rules Passed ; 6 ; +; Number of I/O Rules Passed ; 9 ; ; Number of I/O Rules Failed ; 0 ; ; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 22 ; +; Number of I/O Rules Inapplicable ; 19 ; +----------------------------------+-------+ @@ -1582,12 +1344,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ ; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; -; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; -; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; ; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; ; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; ; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; ; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; ; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; ; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; @@ -1618,40 +1380,27 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ ; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ -; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 30 ; 30 ; 0 ; +; Total Pass ; 0 ; 15 ; 15 ; 0 ; 0 ; 17 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 17 ; 17 ; 0 ; ; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 30 ; 30 ; 30 ; 30 ; 30 ; 0 ; 30 ; 30 ; 30 ; 30 ; 30 ; 30 ; 30 ; 22 ; 30 ; 30 ; 30 ; 30 ; 22 ; 30 ; 30 ; 30 ; 30 ; 22 ; 30 ; 0 ; 0 ; 30 ; +; Total Inapplicable ; 17 ; 2 ; 2 ; 17 ; 17 ; 0 ; 2 ; 17 ; 17 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 17 ; 17 ; 17 ; 13 ; 17 ; 0 ; 0 ; 17 ; ; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; OUT_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; OUT_1[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; C[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ @@ -1709,13 +1458,13 @@ Info (21077): High junction temperature is 85 degrees C Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Critical Warning (169085): No exact pin location assignment(s) for 30 pins of 30 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Critical Warning (169085): No exact pin location assignment(s) for 2 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. Info (184020): Starting Fitter periphery placement operations Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks -Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07 +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08 Critical Warning (332012): Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. @@ -1725,13 +1474,13 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. Info (170189): Fitter placement preparation operations beginning Info (14951): The Fitter is using Advanced Physical Optimization. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:04 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources - Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36 + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped @@ -1742,10 +1491,11 @@ Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 -Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 1347 megabytes - Info: Processing ended: Tue Sep 15 10:06:42 2026 - Info: Elapsed time: 00:00:32 - Info: Total CPU time (on all processors): 00:00:48 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info: Quartus Prime Fitter was successful. 0 errors, 7 warnings + Info: Peak virtual memory: 1379 megabytes + Info: Processing ended: Tue Sep 15 19:39:25 2026 + Info: Elapsed time: 00:00:36 + Info: Total CPU time (on all processors): 00:00:50 diff --git a/Quartus/A1_Q5/output_files/shifter.fit.smsg b/Quartus/A1_Q5/output_files/shifter.fit.smsg new file mode 100644 index 0000000..9302919 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.fit.smsg @@ -0,0 +1,6 @@ +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density +Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks diff --git a/Quartus/A1_Q5/output_files/shifter.fit.summary b/Quartus/A1_Q5/output_files/shifter.fit.summary index 32518c6..a92456d 100644 --- a/Quartus/A1_Q5/output_files/shifter.fit.summary +++ b/Quartus/A1_Q5/output_files/shifter.fit.summary @@ -1,13 +1,13 @@ -Fitter Status : Successful - Tue Sep 15 10:06:41 2026 +Fitter Status : Successful - Tue Sep 15 19:39:25 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : shifter Top-level Entity Name : shifter Family : Cyclone V Device : 5CGXFC5C6F27C7 Timing Models : Final -Logic utilization (in ALMs) : 48 / 29,080 ( < 1 % ) +Logic utilization (in ALMs) : 21 / 29,080 ( < 1 % ) Total registers : 0 -Total pins : 30 / 364 ( 8 % ) +Total pins : 17 / 364 ( 5 % ) Total virtual pins : 0 Total block memory bits : 0 / 4,567,040 ( 0 % ) Total RAM Blocks : 0 / 446 ( 0 % ) diff --git a/Quartus/A1_Q5/output_files/shifter.flow.rpt b/Quartus/A1_Q5/output_files/shifter.flow.rpt index 0ddbe7f..1c1dd35 100644 --- a/Quartus/A1_Q5/output_files/shifter.flow.rpt +++ b/Quartus/A1_Q5/output_files/shifter.flow.rpt @@ -1,5 +1,5 @@ Flow report for shifter -Tue Sep 15 10:06:57 2026 +Tue Sep 15 19:39:43 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,16 +41,16 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Sep 15 10:06:57 2026 ; +; Flow Status ; Successful - Tue Sep 15 19:39:43 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; ; Family ; Cyclone V ; ; Device ; 5CGXFC5C6F27C7 ; ; Timing Models ; Final ; -; Logic utilization (in ALMs) ; 48 / 29,080 ( < 1 % ) ; +; Logic utilization (in ALMs) ; 21 / 29,080 ( < 1 % ) ; ; Total registers ; 0 ; -; Total pins ; 30 / 364 ( 8 % ) ; +; Total pins ; 17 / 364 ( 5 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; ; Total DSP Blocks ; 0 / 150 ( 0 % ) ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/15/2026 10:05:58 ; +; Start date & time ; 09/15/2026 19:38:37 ; ; Main task ; Compilation ; ; Revision Name ; shifter ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 253029099468756.178943075805931 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 268883478169649.178946511707335 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,12 +101,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 413 MB ; 00:00:25 ; -; Fitter ; 00:00:31 ; 1.0 ; 1347 MB ; 00:00:48 ; -; Assembler ; 00:00:05 ; 1.0 ; 518 MB ; 00:00:05 ; -; Timing Analyzer ; 00:00:06 ; 1.0 ; 750 MB ; 00:00:05 ; -; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ; -; Total ; 00:00:55 ; -- ; -- ; 00:01:24 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ; +; Fitter ; 00:00:36 ; 1.0 ; 1379 MB ; 00:00:50 ; +; Assembler ; 00:00:06 ; 1.0 ; 507 MB ; 00:00:06 ; +; Timing Analyzer ; 00:00:06 ; 1.0 ; 777 MB ; 00:00:06 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ; +; Total ; 00:01:00 ; -- ; -- ; 00:01:27 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A1_Q5/output_files/shifter.map.rpt b/Quartus/A1_Q5/output_files/shifter.map.rpt index 15eac32..b988f60 100644 --- a/Quartus/A1_Q5/output_files/shifter.map.rpt +++ b/Quartus/A1_Q5/output_files/shifter.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for shifter -Tue Sep 15 10:06:09 2026 +Tue Sep 15 19:38:48 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -14,11 +14,10 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity 8. General Register Statistics - 9. Multiplexer Restructuring Statistics (Restructuring Performed) - 10. Parameter Settings for User Entity Instance: Top-level Entity: |shifter - 11. Post-Synthesis Netlist Statistics for Top Partition - 12. Elapsed Time Per Partition - 13. Analysis & Synthesis Messages + 9. Parameter Settings for User Entity Instance: Top-level Entity: |shifter + 10. Post-Synthesis Netlist Statistics for Top Partition + 11. Elapsed Time Per Partition + 12. Analysis & Synthesis Messages @@ -45,14 +44,14 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:06:09 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:38:48 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; shifter ; ; Top-level Entity Name ; shifter ; ; Family ; Cyclone V ; ; Logic utilization (in ALMs) ; N/A ; ; Total registers ; 0 ; -; Total pins ; 30 ; +; Total pins ; 17 ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 ; ; Total DSP Blocks ; 0 ; @@ -177,31 +176,31 @@ on the Quartus Prime software download page. +----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+ -+-----------------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------------+ -; Resource ; Usage ; -+---------------------------------------------+-------------+ -; Estimate of Logic utilization (ALMs needed) ; 56 ; -; ; ; -; Combinational ALUT usage for logic ; 85 ; -; -- 7 input functions ; 3 ; -; -- 6 input functions ; 23 ; -; -- 5 input functions ; 41 ; -; -- 4 input functions ; 9 ; -; -- <=3 input functions ; 9 ; -; ; ; -; Dedicated logic registers ; 0 ; -; ; ; -; I/O pins ; 30 ; -; ; ; -; Total DSP Blocks ; 0 ; -; ; ; -; Maximum fan-out node ; op[2]~input ; -; Maximum fan-out ; 29 ; -; Total fan-out ; 462 ; -; Average fan-out ; 3.19 ; -+---------------------------------------------+-------------+ ++----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+------------+ +; Resource ; Usage ; ++---------------------------------------------+------------+ +; Estimate of Logic utilization (ALMs needed) ; 23 ; +; ; ; +; Combinational ALUT usage for logic ; 32 ; +; -- 7 input functions ; 1 ; +; -- 6 input functions ; 13 ; +; -- 5 input functions ; 5 ; +; -- 4 input functions ; 6 ; +; -- <=3 input functions ; 7 ; +; ; ; +; Dedicated logic registers ; 0 ; +; ; ; +; I/O pins ; 17 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; A[3]~input ; +; Maximum fan-out ; 15 ; +; Total fan-out ; 173 ; +; Average fan-out ; 2.62 ; ++---------------------------------------------+------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -209,7 +208,7 @@ on the Quartus Prime software download page. +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ -; |shifter ; 85 (85) ; 0 (0) ; 0 ; 0 ; 30 ; 0 ; |shifter ; shifter ; work ; +; |shifter ; 32 (32) ; 0 (0) ; 0 ; 0 ; 17 ; 0 ; |shifter ; shifter ; work ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -229,24 +228,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ -+------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |shifter|ShiftLeft0 ; -; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |shifter|ShiftRight2 ; -; 23:1 ; 2 bits ; 30 LEs ; 20 LEs ; 10 LEs ; No ; |shifter|Mux1 ; -; 21:1 ; 2 bits ; 28 LEs ; 20 LEs ; 8 LEs ; No ; |shifter|Mux5 ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ - - +-------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: Top-level Entity: |shifter ; +----------------+-------+------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------+ -; width ; 8 ; Signed Integer ; +; width ; 2 ; Signed Integer ; +----------------+-------+------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". @@ -256,19 +243,19 @@ Note: In order to hide this table in the UI and the text report file, please set +-----------------------+-----------------------------+ ; Type ; Count ; +-----------------------+-----------------------------+ -; arriav_lcell_comb ; 85 ; -; extend ; 3 ; -; 7 data inputs ; 3 ; -; normal ; 82 ; +; arriav_lcell_comb ; 32 ; +; extend ; 1 ; +; 7 data inputs ; 1 ; +; normal ; 31 ; ; 2 data inputs ; 3 ; -; 3 data inputs ; 6 ; -; 4 data inputs ; 9 ; -; 5 data inputs ; 41 ; -; 6 data inputs ; 23 ; -; boundary_port ; 30 ; +; 3 data inputs ; 4 ; +; 4 data inputs ; 6 ; +; 5 data inputs ; 5 ; +; 6 data inputs ; 13 ; +; boundary_port ; 17 ; ; ; ; ; Max LUT depth ; 4.00 ; -; Average LUT depth ; 3.75 ; +; Average LUT depth ; 3.13 ; +-----------------------+-----------------------------+ @@ -277,7 +264,7 @@ Note: In order to hide this table in the UI and the text report file, please set +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ -; Top ; 00:00:01 ; +; Top ; 00:00:00 ; +----------------+--------------+ @@ -287,7 +274,7 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:05:57 2026 + Info: Processing started: Tue Sep 15 19:38:37 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -297,14 +284,14 @@ Info (12127): Elaborating entity "shifter" for the top level hierarchy Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 115 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 22 input pins - Info (21059): Implemented 8 output pins - Info (21061): Implemented 85 logic cells +Info (21057): Implemented 49 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 13 input pins + Info (21059): Implemented 4 output pins + Info (21061): Implemented 32 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning - Info: Peak virtual memory: 430 megabytes - Info: Processing ended: Tue Sep 15 10:06:09 2026 - Info: Elapsed time: 00:00:12 - Info: Total CPU time (on all processors): 00:00:25 + Info: Peak virtual memory: 433 megabytes + Info: Processing ended: Tue Sep 15 19:38:48 2026 + Info: Elapsed time: 00:00:11 + Info: Total CPU time (on all processors): 00:00:24 diff --git a/Quartus/A1_Q5/output_files/shifter.map.summary b/Quartus/A1_Q5/output_files/shifter.map.summary index ed8ac4b..dc60e32 100644 --- a/Quartus/A1_Q5/output_files/shifter.map.summary +++ b/Quartus/A1_Q5/output_files/shifter.map.summary @@ -1,11 +1,11 @@ -Analysis & Synthesis Status : Successful - Tue Sep 15 10:06:09 2026 +Analysis & Synthesis Status : Successful - Tue Sep 15 19:38:48 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : shifter Top-level Entity Name : shifter Family : Cyclone V Logic utilization (in ALMs) : N/A Total registers : 0 -Total pins : 30 +Total pins : 17 Total virtual pins : 0 Total block memory bits : 0 Total DSP Blocks : 0 diff --git a/Quartus/A1_Q5/output_files/shifter.pin b/Quartus/A1_Q5/output_files/shifter.pin index 39bcb45..d468975 100644 --- a/Quartus/A1_Q5/output_files/shifter.pin +++ b/Quartus/A1_Q5/output_files/shifter.pin @@ -29,8 +29,8 @@ -- VCCIO : Dedicated power pin, which MUST be connected to VCC -- of its bank. -- Bank 3A: 2.5V - -- Bank 3B: 2.5V - -- Bank 4A: 2.5V + -- Bank 3B: 1.2V + -- Bank 4A: 1.2V -- Bank 5A: 2.5V -- Bank 5B: 2.5V -- Bank 6A: 2.5V @@ -109,7 +109,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A : VCC_AUX : AA8 : power : : 2.5V : : VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : : -VCCIO3B : AA10 : power : : 2.5V : 3B : +VCCIO3B : AA10 : power : : 1.2V : 3B : VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A : NC : AA12 : : : : : VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A : @@ -119,13 +119,13 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A : -VCCIO4A : AA20 : power : : 2.5V : 4A : +VCCIO4A : AA20 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5B : GND : AA25 : gnd : : : : -B[2] : AA26 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B : GND : AB1 : : : : B0L : GND : AB2 : : : : B0L : GND : AB3 : gnd : : : : @@ -138,7 +138,7 @@ VCCPD3A : AB9 : power : : 2.5V RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B : -VCCIO4A : AB13 : power : : 2.5V : 4A : +VCCIO4A : AB13 : power : : 1.2V : 4A : VCC_AUX : AB14 : power : : 2.5V : : RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A : @@ -151,7 +151,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : VCCIO5A : AB23 : power : : 2.5V : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B : -A[3] : AB26 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5B : GND : AC1 : gnd : : : : GND : AC2 : gnd : : : : GXB_NC : AC3 : : : : B0L : @@ -159,15 +159,15 @@ GXB_NC : AC4 : : : GND : AC5 : gnd : : : : VCCIO3A : AC6 : power : : 2.5V : 3A : VREFB3AN0 : AC7 : power : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B : +B[1] : AC8 : input : 1.2 V : : 3B : Y +C[0] : AC9 : input : 1.2 V : : 3B : Y +op[0] : AC10 : input : 1.2 V : : 3B : Y GND : AC11 : gnd : : : : VREFB3BN0 : AC12 : power : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A : -VCCIO4A : AC16 : power : : 2.5V : 4A : +VCCIO4A : AC16 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A : @@ -186,17 +186,17 @@ AS_DATA1, DATA1 : AD5 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B : -VCCIO3B : AD9 : power : : 2.5V : 3B : +VCCIO3B : AD9 : power : : 1.2V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 4A : +B[0] : AD13 : input : 1.2 V : : 4A : Y GND : AD14 : gnd : : : : VREFB4AN0 : AD15 : power : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A : -VCCIO4A : AD19 : power : : 2.5V : 4A : +VCCIO4A : AD19 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A : @@ -209,23 +209,23 @@ GND : AE2 : gnd : : GXB_NC : AE3 : : : : B0L : GXB_NC : AE4 : : : : B0L : GND : AE5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3B : +B[3] : AE6 : input : 1.2 V : : 3B : N GND : AE7 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A : +C[1] : AE10 : input : 1.2 V : : 4A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A : -VCCIO4A : AE12 : power : : 2.5V : 4A : +VCCIO4A : AE12 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A : GND : AE17 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A : +op[2] : AE19 : input : 1.2 V : : 4A : Y RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A : -VCCIO4A : AE22 : power : : 2.5V : 4A : +VCCIO4A : AE22 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A : @@ -234,7 +234,7 @@ GND : AF2 : gnd : : GND : AF3 : gnd : : : : GND : AF4 : gnd : : : : AS_DATA0, ASDO, DATA0 : AF5 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B : +B[2] : AF6 : input : 1.2 V : : 3B : N RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B : @@ -243,7 +243,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A : -VCCIO4A : AF15 : power : : 2.5V : 4A : +VCCIO4A : AF15 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : @@ -331,7 +331,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : GND : D23 : : : : 7A : GND : D24 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 6A : -OUT_1[2] : D26 : output : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6A : GND : E1 : gnd : : : : GND : E2 : gnd : : : : NC : E3 : : : : : @@ -363,8 +363,8 @@ NC : F2 : : : GND : F3 : gnd : : : : GND : F4 : gnd : : : : nCONFIG : F5 : : : : 9A : -RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A : -RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A : +OUT_1[1] : F6 : output : 2.5 V : : 8A : Y +OUT_1[0] : F7 : output : 2.5 V : : 8A : Y VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : : VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A : GND : F10 : gnd : : : : @@ -383,14 +383,14 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : F23 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6A : VCCIO6A : F25 : power : : 2.5V : 6A : -OUT_1[0] : F26 : output : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A : GND : G1 : gnd : : : : GND : G2 : gnd : : : : NC : G3 : : : : : NC : G4 : : : : : GND : G5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8A : -RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A : +OUT_1[2] : G6 : output : 2.5 V : : 8A : Y +OUT_1[3] : G7 : output : 2.5 V : : 8A : Y VCCIO8A : G8 : power : : 2.5V : 8A : VCC_AUX : G9 : power : : 2.5V : : RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A : @@ -407,9 +407,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : VCCA_FPLL : G21 : power : : 2.5V : : RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6A : GND : G23 : gnd : : : : -C[5] : G24 : input : 2.5 V : : 6A : N -C[3] : G25 : input : 2.5 V : : 6A : N -C[1] : G26 : input : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A : NC : H1 : : : : : NC : H2 : : : : : GND : H3 : gnd : : : : @@ -434,7 +434,7 @@ VCCIO6A : H21 : power : : 2.5V RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A : -A[2] : H25 : input : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A : GND : H26 : gnd : : : : GND : J1 : gnd : : : : GND : J2 : gnd : : : : @@ -460,8 +460,8 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : VCCPD6A : J22 : power : : 2.5V : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A : VCCIO6A : J24 : power : : 2.5V : 6A : -C[4] : J25 : input : 2.5 V : : 6A : N -op[1] : J26 : input : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A : GXB_NC : K1 : : : : B1L : GXB_NC : K2 : : : : B1L : GND : K3 : gnd : : : : @@ -534,11 +534,11 @@ GND : M17 : gnd : : VCC : M18 : power : : 1.1V : : GND : M19 : gnd : : : : VCC : M20 : power : : 1.1V : : -C[7] : M21 : input : 2.5 V : : 6A : N -OUT_1[7] : M22 : output : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A : VCCIO6A : M23 : power : : 2.5V : 6A : -B[1] : M24 : input : 2.5 V : : 6A : N -OUT_1[5] : M25 : output : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A : GND : N1 : gnd : : : : GND : N2 : gnd : : : : @@ -559,12 +559,12 @@ GND : N16 : gnd : : VCC : N17 : power : : 1.1V : : GND : N18 : gnd : : : : VCC : N19 : power : : 1.1V : : -OUT_1[4] : N20 : output : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6A : GND : N21 : gnd : : : : VCCPD5B : N22 : power : : 2.5V : 5B : -OUT_1[1] : N23 : output : 2.5 V : : 6A : N -A[0] : N24 : input : 2.5 V : : 6A : N -A[7] : N25 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 5B : VCCIO5B : N26 : power : : 2.5V : 5B : GXB_NC : P1 : : : : B1L : GXB_NC : P2 : : : : B1L : @@ -576,8 +576,8 @@ GND : P7 : gnd : : RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3A : GND : P9 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3B : +A[0] : P11 : input : 1.2 V : : 3B : Y +A[1] : P12 : input : 1.2 V : : 3B : Y GND : P13 : gnd : : : : VCC : P14 : power : : 1.1V : : GND : P15 : gnd : : : : @@ -586,12 +586,12 @@ GND : P17 : gnd : : VCC : P18 : power : : 1.1V : : GND : P19 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5B : -C[2] : P21 : input : 2.5 V : : 5B : N -op[2] : P22 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : P23 : : : : 5B : GND : P24 : gnd : : : : VREFB5BN0 : P25 : power : : : 5B : -op[0] : P26 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 5B : GND : R1 : gnd : : : : GND : R2 : gnd : : : : VCCH_GXBL : R3 : power : : 2.5V : : @@ -611,13 +611,13 @@ GND : R16 : gnd : : VCC : R17 : power : : 1.1V : : GND : R18 : gnd : : : : VCC : R19 : power : : 1.1V : : -C[6] : R20 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5B : VCCPD5B : R21 : power : : 2.5V : 5B : VCCIO5B : R22 : power : : 2.5V : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5B : -A[1] : R26 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5B : GND : T1 : : : : B1L : GND : T2 : : : : B1L : GND : T3 : gnd : : : : @@ -643,7 +643,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 5B : VCCIO5B : T25 : power : : 2.5V : 5B : -OUT_1[6] : T26 : output : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5B : GND : U1 : gnd : : : : GND : U2 : gnd : : : : VCCL_GXBL : U3 : power : : 1.1V : : @@ -651,7 +651,7 @@ GND : U4 : gnd : : VCCE_GXBL : U5 : power : : 1.1V : : AS_DATA3, DATA3 : U6 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A : -VCCIO3B : U8 : power : : 2.5V : 3B : +VCCIO3B : U8 : power : : 1.2V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B : @@ -661,15 +661,15 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A : -VCCIO4A : U18 : power : : 2.5V : 4A : +VCCIO4A : U18 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A : VCCPD5A : U21 : power : : 2.5V : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A : GND : U23 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5B : -B[0] : U25 : input : 2.5 V : : 5B : N -OUT_1[3] : U26 : output : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5B : GND : V1 : : : : B1L : GND : V2 : : : : B1L : GND : V3 : gnd : : : : @@ -680,7 +680,7 @@ TDO : V7 : output : : RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B : -VCCIO3B : V11 : power : : 2.5V : 3B : +VCCIO3B : V11 : power : : 1.2V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A : @@ -709,7 +709,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A : -VCCIO4A : W14 : power : : 2.5V : 4A : +VCCIO4A : W14 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A : @@ -720,8 +720,8 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : : VREFB5AN0 : W23 : power : : : 5A : VCCIO5B : W24 : power : : 2.5V : 5B : -A[5] : W25 : input : 2.5 V : : 5B : N -C[0] : W26 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5B : GND : Y1 : : : : B0L : GND : Y2 : : : : B0L : GND : Y3 : gnd : : : : @@ -732,13 +732,13 @@ VCCIO3A : Y7 : power : : 2.5V RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B : +op[1] : Y11 : input : 1.2 V : : 3B : Y GND : Y12 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A : -VCCIO4A : Y17 : power : : 2.5V : 4A : +A[2] : Y15 : input : 1.2 V : : 4A : Y +A[3] : Y16 : input : 1.2 V : : 4A : Y +VCCIO4A : Y17 : power : : 1.2V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A : @@ -746,5 +746,5 @@ VCCA_FPLL : Y21 : power : : 2.5V GND : Y22 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A : -A[6] : Y25 : input : 2.5 V : : 5B : N -A[4] : Y26 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B : diff --git a/Quartus/A1_Q5/output_files/shifter.sof b/Quartus/A1_Q5/output_files/shifter.sof index bfcdd4d..6bb17cb 100644 Binary files a/Quartus/A1_Q5/output_files/shifter.sof and b/Quartus/A1_Q5/output_files/shifter.sof differ diff --git a/Quartus/A1_Q5/output_files/shifter.sta.rpt b/Quartus/A1_Q5/output_files/shifter.sta.rpt index acdc45e..e106151 100644 --- a/Quartus/A1_Q5/output_files/shifter.sta.rpt +++ b/Quartus/A1_Q5/output_files/shifter.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for shifter -Tue Sep 15 10:06:55 2026 +Tue Sep 15 19:39:40 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -98,12 +98,12 @@ on the Quartus Prime software download page. ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.05 ; +; Average used ; 1.03 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 5.0% ; +; Processor 2 ; 3.0% ; +----------------------------+-------------+ @@ -294,10 +294,6 @@ No synchronizer chains to report. ; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; OUT_1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; OUT_1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; OUT_1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; OUT_1[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ @@ -306,28 +302,19 @@ No synchronizer chains to report. +-------+--------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +-------+--------------+-----------------+-----------------+ -; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; C[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; C[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; C[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; C[5] ; 2.5 V ; 2000 ps ; 2000 ps ; -; C[6] ; 2.5 V ; 2000 ps ; 2000 ps ; -; C[7] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[7] ; 2.5 V ; 2000 ps ; 2000 ps ; -; C[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; C[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[6] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[5] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; B[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; B[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; B[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[0] ; 1.2 V ; 960 ps ; 960 ps ; +; op[0] ; 1.2 V ; 960 ps ; 960 ps ; +; op[2] ; 1.2 V ; 960 ps ; 960 ps ; +; op[1] ; 1.2 V ; 960 ps ; 960 ps ; +; C[1] ; 1.2 V ; 960 ps ; 960 ps ; +; C[0] ; 1.2 V ; 960 ps ; 960 ps ; +; B[2] ; 1.2 V ; 960 ps ; 960 ps ; +; B[3] ; 1.2 V ; 960 ps ; 960 ps ; +; B[1] ; 1.2 V ; 960 ps ; 960 ps ; +; B[0] ; 1.2 V ; 960 ps ; 960 ps ; +; A[2] ; 1.2 V ; 960 ps ; 960 ps ; +; A[1] ; 1.2 V ; 960 ps ; 960 ps ; +; A[3] ; 1.2 V ; 960 ps ; 960 ps ; +-------+--------------+-----------------+-----------------+ @@ -336,14 +323,10 @@ No synchronizer chains to report. +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; -; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; -; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; -; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -352,14 +335,10 @@ No synchronizer chains to report. +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; -; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; -; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; -; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -368,14 +347,10 @@ No synchronizer chains to report. +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; -; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; -; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; -; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -384,14 +359,10 @@ No synchronizer chains to report. +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; -; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; -; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; -; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; -; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -420,10 +391,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 22 ; 22 ; -; Unconstrained Input Port Paths ; 176 ; 176 ; -; Unconstrained Output Ports ; 8 ; 8 ; -; Unconstrained Output Port Paths ; 176 ; 176 ; +; Unconstrained Input Ports ; 13 ; 13 ; +; Unconstrained Input Port Paths ; 52 ; 52 ; +; Unconstrained Output Ports ; 4 ; 4 ; +; Unconstrained Output Port Paths ; 52 ; 52 ; +---------------------------------+-------+------+ @@ -436,21 +407,12 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; A[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; A[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; A[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; A[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; C[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; C[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; @@ -466,10 +428,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ @@ -482,21 +440,12 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; A[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; A[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; A[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; A[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; C[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; C[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; C[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; @@ -512,10 +461,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; OUT_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ @@ -525,7 +470,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Sep 15 10:06:49 2026 + Info: Processing started: Tue Sep 15 19:39:34 2026 Info: Command: quartus_sta A1_Q5 -c shifter Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -585,9 +530,9 @@ Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 750 megabytes - Info: Processing ended: Tue Sep 15 10:06:55 2026 + Info: Peak virtual memory: 777 megabytes + Info: Processing ended: Tue Sep 15 19:39:40 2026 Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:05 + Info: Total CPU time (on all processors): 00:00:06 diff --git a/Quartus/A1_Q5/shifter.qsf b/Quartus/A1_Q5/shifter.qsf index ce8183c..2d2d6f9 100644 --- a/Quartus/A1_Q5/shifter.qsf +++ b/Quartus/A1_Q5/shifter.qsf @@ -55,7 +55,39 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_F7 -to OUT_1[0] +set_location_assignment PIN_F6 -to OUT_1[1] +set_location_assignment PIN_G6 -to OUT_1[2] +set_location_assignment PIN_G7 -to OUT_1[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to C[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to C[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to C[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to C[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to C +set_instance_assignment -name IO_STANDARD "1.2 V" -to B[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to B[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to B +set_instance_assignment -name IO_STANDARD "1.2 V" -to A[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to A[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to A[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to A[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to A +set_instance_assignment -name IO_STANDARD "1.2 V" -to op[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to op[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to op[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to op +set_location_assignment PIN_AE19 -to op[2] +set_location_assignment PIN_Y11 -to op[1] +set_location_assignment PIN_AC10 -to op[0] +set_location_assignment PIN_AC9 -to C[0] +set_location_assignment PIN_AE10 -to C[1] +set_location_assignment PIN_AD13 -to B[0] +set_location_assignment PIN_AC8 -to B[1] +set_location_assignment PIN_P11 -to A[0] +set_location_assignment PIN_P12 -to A[1] +set_location_assignment PIN_Y15 -to A[2] +set_location_assignment PIN_Y16 -to A[3] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/A1_Q5/shifter.qws b/Quartus/A1_Q5/shifter.qws deleted file mode 100644 index a133cfb..0000000 Binary files a/Quartus/A1_Q5/shifter.qws and /dev/null differ diff --git a/Quartus/A1_Q5/simulation/questa/shifter.svo b/Quartus/A1_Q5/simulation/questa/shifter.svo index 1e491dc..4c3c5f6 100644 --- a/Quartus/A1_Q5/simulation/questa/shifter.svo +++ b/Quartus/A1_Q5/simulation/questa/shifter.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "09/15/2026 10:06:57" +// DATE "09/15/2026 19:39:43" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 @@ -32,46 +32,33 @@ module shifter ( op, A, - C, B, + C, OUT_1); input logic [2:0] op ; -input logic [7:0] A ; -input logic [7:0] C ; -input logic [2:0] B ; -output logic [7:0] OUT_1 ; +input logic [3:0] A ; +input logic [3:0] B ; +input logic [1:0] C ; +output logic [3:0] OUT_1 ; // Design Ports Information -// OUT_1[0] => Location: PIN_F26, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[1] => Location: PIN_N23, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[2] => Location: PIN_D26, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[3] => Location: PIN_U26, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[4] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[5] => Location: PIN_M25, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[6] => Location: PIN_T26, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[7] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default -// op[0] => Location: PIN_P26, I/O Standard: 2.5 V, Current Strength: Default -// A[0] => Location: PIN_N24, I/O Standard: 2.5 V, Current Strength: Default -// op[2] => Location: PIN_P22, I/O Standard: 2.5 V, Current Strength: Default -// op[1] => Location: PIN_J26, I/O Standard: 2.5 V, Current Strength: Default -// C[2] => Location: PIN_P21, I/O Standard: 2.5 V, Current Strength: Default -// C[3] => Location: PIN_G25, I/O Standard: 2.5 V, Current Strength: Default -// C[4] => Location: PIN_J25, I/O Standard: 2.5 V, Current Strength: Default -// C[5] => Location: PIN_G24, I/O Standard: 2.5 V, Current Strength: Default -// C[6] => Location: PIN_R20, I/O Standard: 2.5 V, Current Strength: Default -// C[7] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default -// A[7] => Location: PIN_N25, I/O Standard: 2.5 V, Current Strength: Default -// C[0] => Location: PIN_W26, I/O Standard: 2.5 V, Current Strength: Default -// C[1] => Location: PIN_G26, I/O Standard: 2.5 V, Current Strength: Default -// A[6] => Location: PIN_Y25, I/O Standard: 2.5 V, Current Strength: Default -// A[4] => Location: PIN_Y26, I/O Standard: 2.5 V, Current Strength: Default -// A[5] => Location: PIN_W25, I/O Standard: 2.5 V, Current Strength: Default -// A[2] => Location: PIN_H25, I/O Standard: 2.5 V, Current Strength: Default -// A[1] => Location: PIN_R26, I/O Standard: 2.5 V, Current Strength: Default -// A[3] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default -// B[2] => Location: PIN_AA26, I/O Standard: 2.5 V, Current Strength: Default -// B[0] => Location: PIN_U25, I/O Standard: 2.5 V, Current Strength: Default -// B[1] => Location: PIN_M24, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[1] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[2] => Location: PIN_G6, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[3] => Location: PIN_G7, I/O Standard: 2.5 V, Current Strength: Default +// A[0] => Location: PIN_P11, I/O Standard: 1.2 V, Current Strength: Default +// op[0] => Location: PIN_AC10, I/O Standard: 1.2 V, Current Strength: Default +// op[2] => Location: PIN_AE19, I/O Standard: 1.2 V, Current Strength: Default +// op[1] => Location: PIN_Y11, I/O Standard: 1.2 V, Current Strength: Default +// C[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default +// C[0] => Location: PIN_AC9, I/O Standard: 1.2 V, Current Strength: Default +// B[2] => Location: PIN_AF6, I/O Standard: 1.2 V, Current Strength: Default +// B[3] => Location: PIN_AE6, I/O Standard: 1.2 V, Current Strength: Default +// B[1] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default +// B[0] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default +// A[2] => Location: PIN_Y15, I/O Standard: 1.2 V, Current Strength: Default +// A[1] => Location: PIN_P12, I/O Standard: 1.2 V, Current Strength: Default +// A[3] => Location: PIN_Y16, I/O Standard: 1.2 V, Current Strength: Default wire gnd; @@ -86,118 +73,56 @@ tri1 devclrn; tri1 devpor; tri1 devoe; wire \~QUARTUS_CREATED_GND~I_combout ; +wire \C[1]~input_o ; +wire \C[0]~input_o ; +wire \ShiftRight0~0_combout ; +wire \op[1]~input_o ; +wire \B[3]~input_o ; wire \B[2]~input_o ; +wire \B[0]~input_o ; +wire \B[1]~input_o ; +wire \ShiftRight2~0_combout ; +wire \op[2]~input_o ; +wire \Mux3~0_combout ; +wire \op[0]~input_o ; wire \A[3]~input_o ; +wire \Mux0~0_combout ; wire \A[1]~input_o ; wire \A[0]~input_o ; wire \A[2]~input_o ; -wire \B[1]~input_o ; -wire \B[0]~input_o ; -wire \ShiftRight3~1_combout ; -wire \A[5]~input_o ; -wire \A[6]~input_o ; -wire \A[4]~input_o ; -wire \A[7]~input_o ; -wire \ShiftRight3~0_combout ; -wire \Mux7~1_combout ; -wire \C[1]~input_o ; -wire \C[0]~input_o ; -wire \ShiftRight1~1_combout ; -wire \C[2]~input_o ; -wire \C[4]~input_o ; -wire \C[5]~input_o ; -wire \C[6]~input_o ; -wire \C[7]~input_o ; -wire \C[3]~input_o ; -wire \ShiftLeft0~0_combout ; wire \ShiftRight1~0_combout ; -wire \op[1]~input_o ; -wire \Mux7~0_combout ; -wire \ShiftRight1~2_combout ; -wire \op[2]~input_o ; -wire \ShiftRight0~0_combout ; -wire \Mux7~3_combout ; -wire \op[0]~input_o ; -wire \Mux7~2_combout ; -wire \Mux5~4_combout ; -wire \Mux5~0_combout ; -wire \Mux5~1_combout ; wire \ShiftLeft1~0_combout ; -wire \ShiftRight2~0_combout ; -wire \Mux5~2_combout ; -wire \Mux5~3_combout ; -wire \ShiftRight0~1_combout ; -wire \Mux6~0_combout ; -wire \Mux5~5_combout ; -wire \Mux6~1_combout ; -wire \ShiftLeft0~1_combout ; -wire \Mux5~6_combout ; -wire \Mux5~7_combout ; -wire \Mux6~2_combout ; -wire \Mux6~3_combout ; -wire \ShiftRight1~3_combout ; -wire \Mux6~4_combout ; -wire \Mux6~5_combout ; -wire \Mux6~6_combout ; -wire \ShiftRight0~2_combout ; -wire \ShiftRight2~1_combout ; -wire \ShiftLeft1~1_combout ; -wire \Mux5~8_combout ; -wire \ShiftLeft0~2_combout ; -wire \ShiftRight1~4_combout ; -wire \Mux5~10_combout ; -wire \Mux5~11_combout ; -wire \Mux5~9_combout ; -wire \Mux5~12_combout ; -wire \Mux5~13_combout ; -wire \ShiftRight1~5_combout ; -wire \ShiftRight0~3_combout ; -wire \ShiftLeft0~3_combout ; -wire \ShiftLeft1~2_combout ; -wire \ShiftLeft1~3_combout ; -wire \ShiftRight3~2_combout ; -wire \ShiftRight2~2_combout ; -wire \Mux4~2_combout ; -wire \Mux4~0_combout ; -wire \Mux4~1_combout ; -wire \ShiftLeft0~4_combout ; -wire \ShiftLeft0~5_combout ; -wire \ShiftLeft1~4_combout ; -wire \ShiftLeft1~5_combout ; -wire \ShiftRight2~3_combout ; -wire \Mux3~2_combout ; -wire \Mux3~0_combout ; +wire \ShiftRight3~0_combout ; wire \Mux3~1_combout ; -wire \Mux1~4_combout ; -wire \Mux1~0_combout ; -wire \Mux1~1_combout ; -wire \Mux1~6_combout ; -wire \Mux1~5_combout ; -wire \Mux2~2_combout ; -wire \Mux2~1_combout ; -wire \Mux2~3_combout ; -wire \Mux1~3_combout ; -wire \Mux1~2_combout ; -wire \Mux2~0_combout ; +wire \Mux3~2_combout ; wire \Mux2~4_combout ; -wire \Mux1~9_combout ; -wire \Mux1~8_combout ; -wire \Mux1~10_combout ; -wire \Mux1~7_combout ; -wire \Mux1~11_combout ; -wire \ShiftRight2~4_combout ; -wire \ShiftLeft1~6_combout ; -wire \ShiftLeft1~7_combout ; -wire \ShiftRight0~4_combout ; -wire \ShiftLeft0~6_combout ; -wire \ShiftLeft0~7_combout ; -wire \Mux0~0_combout ; +wire \Mux2~1_combout ; +wire \Mux2~2_combout ; +wire \Mux2~3_combout ; +wire \ShiftLeft1~1_combout ; +wire \ShiftRight2~1_combout ; +wire \ShiftLeft0~0_combout ; +wire \ShiftRight0~1_combout ; +wire \Mux2~0_combout ; +wire \Mux2~5_combout ; +wire \Mux1~1_combout ; +wire \ShiftRight2~2_combout ; +wire \ShiftLeft0~1_combout ; +wire \ShiftLeft1~2_combout ; +wire \ShiftRight0~2_combout ; +wire \Mux1~0_combout ; +wire \Mux1~2_combout ; +wire \ShiftRight0~3_combout ; +wire \ShiftRight2~3_combout ; +wire \ShiftLeft1~3_combout ; +wire \ShiftLeft0~2_combout ; +wire \Mux0~2_combout ; wire \Mux0~1_combout ; -// Location: IOOBUF_X68_Y33_N39 +// Location: IOOBUF_X14_Y61_N53 cyclonev_io_obuf \OUT_1[0]~output ( - .i(\Mux7~2_combout ), + .i(\Mux3~2_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -211,9 +136,9 @@ defparam \OUT_1[0]~output .open_drain_output = "false"; defparam \OUT_1[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X68_Y35_N5 +// Location: IOOBUF_X15_Y61_N36 cyclonev_io_obuf \OUT_1[1]~output ( - .i(\Mux6~6_combout ), + .i(\Mux2~5_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -227,9 +152,9 @@ defparam \OUT_1[1]~output .open_drain_output = "false"; defparam \OUT_1[1]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X68_Y37_N39 +// Location: IOOBUF_X15_Y61_N53 cyclonev_io_obuf \OUT_1[2]~output ( - .i(\Mux5~13_combout ), + .i(\Mux1~2_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -243,9 +168,9 @@ defparam \OUT_1[2]~output .open_drain_output = "false"; defparam \OUT_1[2]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X68_Y27_N56 +// Location: IOOBUF_X14_Y61_N36 cyclonev_io_obuf \OUT_1[3]~output ( - .i(\Mux4~1_combout ), + .i(\Mux0~1_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -259,266 +184,7 @@ defparam \OUT_1[3]~output .open_drain_output = "false"; defparam \OUT_1[3]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X68_Y32_N45 -cyclonev_io_obuf \OUT_1[4]~output ( - .i(\Mux3~1_combout ), - .oe(vcc), - .dynamicterminationcontrol(gnd), - .seriesterminationcontrol(16'b0000000000000000), - .parallelterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(OUT_1[4]), - .obar()); -// synopsys translate_off -defparam \OUT_1[4]~output .bus_hold = "false"; -defparam \OUT_1[4]~output .open_drain_output = "false"; -defparam \OUT_1[4]~output .shift_series_termination_control = "false"; -// synopsys translate_on - -// Location: IOOBUF_X68_Y37_N5 -cyclonev_io_obuf \OUT_1[5]~output ( - .i(\Mux2~4_combout ), - .oe(vcc), - .dynamicterminationcontrol(gnd), - .seriesterminationcontrol(16'b0000000000000000), - .parallelterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(OUT_1[5]), - .obar()); -// synopsys translate_off -defparam \OUT_1[5]~output .bus_hold = "false"; -defparam \OUT_1[5]~output .open_drain_output = "false"; -defparam \OUT_1[5]~output .shift_series_termination_control = "false"; -// synopsys translate_on - -// Location: IOOBUF_X68_Y24_N5 -cyclonev_io_obuf \OUT_1[6]~output ( - .i(\Mux1~11_combout ), - .oe(vcc), - .dynamicterminationcontrol(gnd), - .seriesterminationcontrol(16'b0000000000000000), - .parallelterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(OUT_1[6]), - .obar()); -// synopsys translate_off -defparam \OUT_1[6]~output .bus_hold = "false"; -defparam \OUT_1[6]~output .open_drain_output = "false"; -defparam \OUT_1[6]~output .shift_series_termination_control = "false"; -// synopsys translate_on - -// Location: IOOBUF_X68_Y35_N22 -cyclonev_io_obuf \OUT_1[7]~output ( - .i(\Mux0~1_combout ), - .oe(vcc), - .dynamicterminationcontrol(gnd), - .seriesterminationcontrol(16'b0000000000000000), - .parallelterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(OUT_1[7]), - .obar()); -// synopsys translate_off -defparam \OUT_1[7]~output .bus_hold = "false"; -defparam \OUT_1[7]~output .open_drain_output = "false"; -defparam \OUT_1[7]~output .shift_series_termination_control = "false"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y22_N95 -cyclonev_io_ibuf \B[2]~input ( - .i(B[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[2]~input_o )); -// synopsys translate_off -defparam \B[2]~input .bus_hold = "false"; -defparam \B[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y22_N78 -cyclonev_io_ibuf \A[3]~input ( - .i(A[3]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[3]~input_o )); -// synopsys translate_off -defparam \A[3]~input .bus_hold = "false"; -defparam \A[3]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y24_N21 -cyclonev_io_ibuf \A[1]~input ( - .i(A[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[1]~input_o )); -// synopsys translate_off -defparam \A[1]~input .bus_hold = "false"; -defparam \A[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y33_N4 -cyclonev_io_ibuf \A[0]~input ( - .i(A[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[0]~input_o )); -// synopsys translate_off -defparam \A[0]~input .bus_hold = "false"; -defparam \A[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y35_N55 -cyclonev_io_ibuf \A[2]~input ( - .i(A[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[2]~input_o )); -// synopsys translate_off -defparam \A[2]~input .bus_hold = "false"; -defparam \A[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y33_N21 -cyclonev_io_ibuf \B[1]~input ( - .i(B[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[1]~input_o )); -// synopsys translate_off -defparam \B[1]~input .bus_hold = "false"; -defparam \B[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y27_N38 -cyclonev_io_ibuf \B[0]~input ( - .i(B[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[0]~input_o )); -// synopsys translate_off -defparam \B[0]~input .bus_hold = "false"; -defparam \B[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N33 -cyclonev_lcell_comb \ShiftRight3~1 ( -// Equation(s): -// \ShiftRight3~1_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[3]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[1]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o -// & ( \A[0]~input_o ) ) ) - - .dataa(!\A[3]~input_o ), - .datab(!\A[1]~input_o ), - .datac(!\A[0]~input_o ), - .datad(!\A[2]~input_o ), - .datae(!\B[1]~input_o ), - .dataf(!\B[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight3~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight3~1 .extended_lut = "off"; -defparam \ShiftRight3~1 .lut_mask = 64'h0F0F00FF33335555; -defparam \ShiftRight3~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y26_N38 -cyclonev_io_ibuf \A[5]~input ( - .i(A[5]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[5]~input_o )); -// synopsys translate_off -defparam \A[5]~input .bus_hold = "false"; -defparam \A[5]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y24_N38 -cyclonev_io_ibuf \A[6]~input ( - .i(A[6]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[6]~input_o )); -// synopsys translate_off -defparam \A[6]~input .bus_hold = "false"; -defparam \A[6]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y24_N55 -cyclonev_io_ibuf \A[4]~input ( - .i(A[4]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[4]~input_o )); -// synopsys translate_off -defparam \A[4]~input .bus_hold = "false"; -defparam \A[4]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y27_N4 -cyclonev_io_ibuf \A[7]~input ( - .i(A[7]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[7]~input_o )); -// synopsys translate_off -defparam \A[7]~input .bus_hold = "false"; -defparam \A[7]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N15 -cyclonev_lcell_comb \ShiftRight3~0 ( -// Equation(s): -// \ShiftRight3~0_combout = ( \B[0]~input_o & ( \B[1]~input_o & ( \A[7]~input_o ) ) ) # ( !\B[0]~input_o & ( \B[1]~input_o & ( \A[6]~input_o ) ) ) # ( \B[0]~input_o & ( !\B[1]~input_o & ( \A[5]~input_o ) ) ) # ( !\B[0]~input_o & ( !\B[1]~input_o -// & ( \A[4]~input_o ) ) ) - - .dataa(!\A[5]~input_o ), - .datab(!\A[6]~input_o ), - .datac(!\A[4]~input_o ), - .datad(!\A[7]~input_o ), - .datae(!\B[0]~input_o ), - .dataf(!\B[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight3~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight3~0 .extended_lut = "off"; -defparam \ShiftRight3~0 .lut_mask = 64'h0F0F5555333300FF; -defparam \ShiftRight3~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y28_N51 -cyclonev_lcell_comb \Mux7~1 ( -// Equation(s): -// \Mux7~1_combout = ( \ShiftRight3~0_combout & ( (\ShiftRight3~1_combout ) # (\B[2]~input_o ) ) ) # ( !\ShiftRight3~0_combout & ( (!\B[2]~input_o & \ShiftRight3~1_combout ) ) ) - - .dataa(gnd), - .datab(!\B[2]~input_o ), - .datac(!\ShiftRight3~1_combout ), - .datad(gnd), - .datae(gnd), - .dataf(!\ShiftRight3~0_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux7~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux7~1 .extended_lut = "off"; -defparam \Mux7~1 .lut_mask = 64'h0C0C0C0C3F3F3F3F; -defparam \Mux7~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y33_N55 +// Location: IOIBUF_X36_Y0_N52 cyclonev_io_ibuf \C[1]~input ( .i(C[1]), .ibar(gnd), @@ -529,7 +195,7 @@ defparam \C[1]~input .bus_hold = "false"; defparam \C[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: IOIBUF_X68_Y26_N55 +// Location: IOIBUF_X14_Y0_N35 cyclonev_io_ibuf \C[0]~input ( .i(C[0]), .ibar(gnd), @@ -540,147 +206,31 @@ defparam \C[0]~input .bus_hold = "false"; defparam \C[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X64_Y27_N30 -cyclonev_lcell_comb \ShiftRight1~1 ( +// Location: MLABCELL_X19_Y4_N36 +cyclonev_lcell_comb \ShiftRight0~0 ( // Equation(s): -// \ShiftRight1~1_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[3]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[1]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o -// & ( \A[0]~input_o ) ) ) +// \ShiftRight0~0_combout = (!\C[1]~input_o & !\C[0]~input_o ) - .dataa(!\A[3]~input_o ), - .datab(!\A[1]~input_o ), - .datac(!\A[2]~input_o ), - .datad(!\A[0]~input_o ), - .datae(!\C[1]~input_o ), - .dataf(!\C[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight1~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight1~1 .extended_lut = "off"; -defparam \ShiftRight1~1 .lut_mask = 64'h00FF0F0F33335555; -defparam \ShiftRight1~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y26_N4 -cyclonev_io_ibuf \C[2]~input ( - .i(C[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\C[2]~input_o )); -// synopsys translate_off -defparam \C[2]~input .bus_hold = "false"; -defparam \C[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y32_N78 -cyclonev_io_ibuf \C[4]~input ( - .i(C[4]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\C[4]~input_o )); -// synopsys translate_off -defparam \C[4]~input .bus_hold = "false"; -defparam \C[4]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y41_N55 -cyclonev_io_ibuf \C[5]~input ( - .i(C[5]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\C[5]~input_o )); -// synopsys translate_off -defparam \C[5]~input .bus_hold = "false"; -defparam \C[5]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y22_N44 -cyclonev_io_ibuf \C[6]~input ( - .i(C[6]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\C[6]~input_o )); -// synopsys translate_off -defparam \C[6]~input .bus_hold = "false"; -defparam \C[6]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y32_N61 -cyclonev_io_ibuf \C[7]~input ( - .i(C[7]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\C[7]~input_o )); -// synopsys translate_off -defparam \C[7]~input .bus_hold = "false"; -defparam \C[7]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y35_N38 -cyclonev_io_ibuf \C[3]~input ( - .i(C[3]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\C[3]~input_o )); -// synopsys translate_off -defparam \C[3]~input .bus_hold = "false"; -defparam \C[3]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N36 -cyclonev_lcell_comb \ShiftLeft0~0 ( -// Equation(s): -// \ShiftLeft0~0_combout = ( !\C[7]~input_o & ( !\C[3]~input_o & ( (!\C[4]~input_o & (!\C[5]~input_o & !\C[6]~input_o )) ) ) ) - - .dataa(!\C[4]~input_o ), - .datab(!\C[5]~input_o ), - .datac(!\C[6]~input_o ), + .dataa(gnd), + .datab(!\C[1]~input_o ), + .datac(!\C[0]~input_o ), .datad(gnd), - .datae(!\C[7]~input_o ), - .dataf(!\C[3]~input_o ), + .datae(gnd), + .dataf(gnd), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\ShiftLeft0~0_combout ), + .combout(\ShiftRight0~0_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \ShiftLeft0~0 .extended_lut = "off"; -defparam \ShiftLeft0~0 .lut_mask = 64'h8080000000000000; -defparam \ShiftLeft0~0 .shared_arith = "off"; +defparam \ShiftRight0~0 .extended_lut = "off"; +defparam \ShiftRight0~0 .lut_mask = 64'hC0C0C0C0C0C0C0C0; +defparam \ShiftRight0~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X64_Y28_N12 -cyclonev_lcell_comb \ShiftRight1~0 ( -// Equation(s): -// \ShiftRight1~0_combout = ( \C[0]~input_o & ( \C[1]~input_o & ( \A[7]~input_o ) ) ) # ( !\C[0]~input_o & ( \C[1]~input_o & ( \A[6]~input_o ) ) ) # ( \C[0]~input_o & ( !\C[1]~input_o & ( \A[5]~input_o ) ) ) # ( !\C[0]~input_o & ( !\C[1]~input_o -// & ( \A[4]~input_o ) ) ) - - .dataa(!\A[5]~input_o ), - .datab(!\A[6]~input_o ), - .datac(!\A[7]~input_o ), - .datad(!\A[4]~input_o ), - .datae(!\C[0]~input_o ), - .dataf(!\C[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight1~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight1~0 .extended_lut = "off"; -defparam \ShiftRight1~0 .lut_mask = 64'h00FF555533330F0F; -defparam \ShiftRight1~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y32_N95 +// Location: IOIBUF_X10_Y0_N58 cyclonev_io_ibuf \op[1]~input ( .i(op[1]), .ibar(gnd), @@ -691,57 +241,75 @@ defparam \op[1]~input .bus_hold = "false"; defparam \op[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X65_Y28_N42 -cyclonev_lcell_comb \Mux7~0 ( -// Equation(s): -// \Mux7~0_combout = ( \ShiftRight1~0_combout & ( \op[1]~input_o & ( (!\ShiftLeft0~0_combout & (((\A[7]~input_o )))) # (\ShiftLeft0~0_combout & (((\C[2]~input_o )) # (\ShiftRight1~1_combout ))) ) ) ) # ( !\ShiftRight1~0_combout & ( \op[1]~input_o & ( -// (!\ShiftLeft0~0_combout & (((\A[7]~input_o )))) # (\ShiftLeft0~0_combout & (\ShiftRight1~1_combout & (!\C[2]~input_o ))) ) ) ) # ( \ShiftRight1~0_combout & ( !\op[1]~input_o & ( (\ShiftLeft0~0_combout & ((\C[2]~input_o ) # (\ShiftRight1~1_combout -// ))) ) ) ) # ( !\ShiftRight1~0_combout & ( !\op[1]~input_o & ( (\ShiftRight1~1_combout & (!\C[2]~input_o & \ShiftLeft0~0_combout )) ) ) ) +// Location: IOIBUF_X21_Y0_N35 +cyclonev_io_ibuf \B[3]~input ( + .i(B[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[3]~input_o )); +// synopsys translate_off +defparam \B[3]~input .bus_hold = "false"; +defparam \B[3]~input .simulate_z_as = "z"; +// synopsys translate_on - .dataa(!\ShiftRight1~1_combout ), - .datab(!\C[2]~input_o ), - .datac(!\ShiftLeft0~0_combout ), - .datad(!\A[7]~input_o ), - .datae(!\ShiftRight1~0_combout ), - .dataf(!\op[1]~input_o ), +// Location: IOIBUF_X21_Y0_N52 +cyclonev_io_ibuf \B[2]~input ( + .i(B[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[2]~input_o )); +// synopsys translate_off +defparam \B[2]~input .bus_hold = "false"; +defparam \B[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y0_N35 +cyclonev_io_ibuf \B[0]~input ( + .i(B[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[0]~input_o )); +// synopsys translate_off +defparam \B[0]~input .bus_hold = "false"; +defparam \B[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N52 +cyclonev_io_ibuf \B[1]~input ( + .i(B[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[1]~input_o )); +// synopsys translate_off +defparam \B[1]~input .bus_hold = "false"; +defparam \B[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X21_Y4_N0 +cyclonev_lcell_comb \ShiftRight2~0 ( +// Equation(s): +// \ShiftRight2~0_combout = (!\B[3]~input_o & (!\B[2]~input_o & (!\B[0]~input_o & !\B[1]~input_o ))) + + .dataa(!\B[3]~input_o ), + .datab(!\B[2]~input_o ), + .datac(!\B[0]~input_o ), + .datad(!\B[1]~input_o ), + .datae(gnd), + .dataf(gnd), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\Mux7~0_combout ), + .combout(\ShiftRight2~0_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \Mux7~0 .extended_lut = "off"; -defparam \Mux7~0 .lut_mask = 64'h0404070704F407F7; -defparam \Mux7~0 .shared_arith = "off"; +defparam \ShiftRight2~0 .extended_lut = "off"; +defparam \ShiftRight2~0 .lut_mask = 64'h8000800080008000; +defparam \ShiftRight2~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X64_Y28_N27 -cyclonev_lcell_comb \ShiftRight1~2 ( -// Equation(s): -// \ShiftRight1~2_combout = ( !\C[0]~input_o & ( !\C[1]~input_o ) ) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .datae(!\C[0]~input_o ), - .dataf(!\C[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight1~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight1~2 .extended_lut = "off"; -defparam \ShiftRight1~2 .lut_mask = 64'hFFFF000000000000; -defparam \ShiftRight1~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y26_N21 +// Location: IOIBUF_X50_Y0_N35 cyclonev_io_ibuf \op[2]~input ( .i(op[2]), .ibar(gnd), @@ -752,55 +320,31 @@ defparam \op[2]~input .bus_hold = "false"; defparam \op[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X64_Y28_N48 -cyclonev_lcell_comb \ShiftRight0~0 ( +// Location: MLABCELL_X19_Y4_N39 +cyclonev_lcell_comb \Mux3~0 ( // Equation(s): -// \ShiftRight0~0_combout = ( !\C[7]~input_o & ( !\C[3]~input_o & ( (!\C[2]~input_o & (!\C[5]~input_o & (!\C[4]~input_o & !\C[6]~input_o ))) ) ) ) +// \Mux3~0_combout = ( \op[2]~input_o & ( (!\op[1]~input_o & !\ShiftRight2~0_combout ) ) ) # ( !\op[2]~input_o & ( (!\ShiftRight0~0_combout & !\op[1]~input_o ) ) ) - .dataa(!\C[2]~input_o ), - .datab(!\C[5]~input_o ), - .datac(!\C[4]~input_o ), - .datad(!\C[6]~input_o ), - .datae(!\C[7]~input_o ), - .dataf(!\C[3]~input_o ), + .dataa(!\ShiftRight0~0_combout ), + .datab(gnd), + .datac(!\op[1]~input_o ), + .datad(!\ShiftRight2~0_combout ), + .datae(gnd), + .dataf(!\op[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\ShiftRight0~0_combout ), + .combout(\Mux3~0_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \ShiftRight0~0 .extended_lut = "off"; -defparam \ShiftRight0~0 .lut_mask = 64'h8000000000000000; -defparam \ShiftRight0~0 .shared_arith = "off"; +defparam \Mux3~0 .extended_lut = "off"; +defparam \Mux3~0 .lut_mask = 64'hA0A0A0A0F000F000; +defparam \Mux3~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y28_N36 -cyclonev_lcell_comb \Mux7~3 ( -// Equation(s): -// \Mux7~3_combout = ( !\op[2]~input_o & ( (((\ShiftRight1~2_combout & (\ShiftRight0~0_combout ))) # (\op[1]~input_o )) ) ) # ( \op[2]~input_o & ( (((!\B[0]~input_o & (!\B[2]~input_o & !\B[1]~input_o ))) # (\op[1]~input_o )) ) ) - - .dataa(!\ShiftRight1~2_combout ), - .datab(!\B[0]~input_o ), - .datac(!\B[2]~input_o ), - .datad(!\op[1]~input_o ), - .datae(!\op[2]~input_o ), - .dataf(!\B[1]~input_o ), - .datag(!\ShiftRight0~0_combout ), - .cin(gnd), - .sharein(gnd), - .combout(\Mux7~3_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux7~3 .extended_lut = "on"; -defparam \Mux7~3 .lut_mask = 64'h05FFC0FF05FF00FF; -defparam \Mux7~3 .shared_arith = "off"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y27_N21 +// Location: IOIBUF_X12_Y0_N52 cyclonev_io_ibuf \op[0]~input ( .i(op[0]), .ibar(gnd), @@ -811,116 +355,110 @@ defparam \op[0]~input .bus_hold = "false"; defparam \op[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X65_Y28_N54 -cyclonev_lcell_comb \Mux7~2 ( -// Equation(s): -// \Mux7~2_combout = ( \op[2]~input_o & ( \A[0]~input_o & ( (!\op[0]~input_o & ((\Mux7~3_combout ))) # (\op[0]~input_o & (\Mux7~1_combout )) ) ) ) # ( !\op[2]~input_o & ( \A[0]~input_o & ( (!\op[0]~input_o & ((\Mux7~3_combout ))) # (\op[0]~input_o & -// (\Mux7~0_combout )) ) ) ) # ( \op[2]~input_o & ( !\A[0]~input_o & ( (\Mux7~1_combout & \op[0]~input_o ) ) ) ) # ( !\op[2]~input_o & ( !\A[0]~input_o & ( (\Mux7~0_combout & \op[0]~input_o ) ) ) ) - - .dataa(!\Mux7~1_combout ), - .datab(!\Mux7~0_combout ), - .datac(!\Mux7~3_combout ), - .datad(!\op[0]~input_o ), - .datae(!\op[2]~input_o ), - .dataf(!\A[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux7~2_combout ), - .sumout(), - .cout(), - .shareout()); +// Location: IOIBUF_X46_Y0_N18 +cyclonev_io_ibuf \A[3]~input ( + .i(A[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[3]~input_o )); // synopsys translate_off -defparam \Mux7~2 .extended_lut = "off"; -defparam \Mux7~2 .lut_mask = 64'h003300550F330F55; -defparam \Mux7~2 .shared_arith = "off"; +defparam \A[3]~input .bus_hold = "false"; +defparam \A[3]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X64_Y28_N33 -cyclonev_lcell_comb \Mux5~4 ( +// Location: MLABCELL_X19_Y4_N21 +cyclonev_lcell_comb \Mux0~0 ( // Equation(s): -// \Mux5~4_combout = ( \ShiftRight0~0_combout & ( (!\op[1]~input_o & (\op[2]~input_o & ((!\op[0]~input_o ) # (\B[2]~input_o )))) ) ) # ( !\ShiftRight0~0_combout & ( (!\op[1]~input_o & ((!\op[0]~input_o ) # ((!\op[2]~input_o ) # (\B[2]~input_o )))) ) ) - - .dataa(!\op[0]~input_o ), - .datab(!\op[1]~input_o ), - .datac(!\B[2]~input_o ), - .datad(!\op[2]~input_o ), - .datae(gnd), - .dataf(!\ShiftRight0~0_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~4_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~4 .extended_lut = "off"; -defparam \Mux5~4 .lut_mask = 64'hCC8CCC8C008C008C; -defparam \Mux5~4 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N9 -cyclonev_lcell_comb \Mux5~0 ( -// Equation(s): -// \Mux5~0_combout = ( \B[1]~input_o & ( (!\op[2]~input_o & (!\C[0]~input_o & !\C[1]~input_o )) ) ) # ( !\B[1]~input_o & ( (!\op[2]~input_o & (((!\C[0]~input_o & !\C[1]~input_o )))) # (\op[2]~input_o & (!\B[0]~input_o )) ) ) - - .dataa(!\op[2]~input_o ), - .datab(!\B[0]~input_o ), - .datac(!\C[0]~input_o ), - .datad(!\C[1]~input_o ), - .datae(gnd), - .dataf(!\B[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~0 .extended_lut = "off"; -defparam \Mux5~0 .lut_mask = 64'hE444E444A000A000; -defparam \Mux5~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N42 -cyclonev_lcell_comb \Mux5~1 ( -// Equation(s): -// \Mux5~1_combout = ( \ShiftRight0~0_combout & ( \op[1]~input_o & ( (!\op[0]~input_o ) # ((\Mux5~0_combout & ((!\op[2]~input_o ) # (!\B[2]~input_o )))) ) ) ) # ( !\ShiftRight0~0_combout & ( \op[1]~input_o & ( (!\op[0]~input_o ) # ((\op[2]~input_o & -// (\Mux5~0_combout & !\B[2]~input_o ))) ) ) ) # ( \ShiftRight0~0_combout & ( !\op[1]~input_o & ( (\Mux5~0_combout & (\op[0]~input_o & ((!\op[2]~input_o ) # (!\B[2]~input_o )))) ) ) ) # ( !\ShiftRight0~0_combout & ( !\op[1]~input_o & ( (\op[2]~input_o -// & (\Mux5~0_combout & (!\B[2]~input_o & \op[0]~input_o ))) ) ) ) - - .dataa(!\op[2]~input_o ), - .datab(!\Mux5~0_combout ), - .datac(!\B[2]~input_o ), - .datad(!\op[0]~input_o ), - .datae(!\ShiftRight0~0_combout ), - .dataf(!\op[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~1 .extended_lut = "off"; -defparam \Mux5~1 .lut_mask = 64'h00100032FF10FF32; -defparam \Mux5~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N6 -cyclonev_lcell_comb \ShiftLeft1~0 ( -// Equation(s): -// \ShiftLeft1~0_combout = ( \A[0]~input_o & ( (!\B[1]~input_o & ((\A[1]~input_o ) # (\B[0]~input_o ))) ) ) # ( !\A[0]~input_o & ( (!\B[0]~input_o & (!\B[1]~input_o & \A[1]~input_o )) ) ) +// \Mux0~0_combout = ( \A[3]~input_o & ( \op[1]~input_o ) ) .dataa(gnd), - .datab(!\B[0]~input_o ), - .datac(!\B[1]~input_o ), - .datad(!\A[1]~input_o ), + .datab(gnd), + .datac(!\op[1]~input_o ), + .datad(gnd), .datae(gnd), - .dataf(!\A[0]~input_o ), + .dataf(!\A[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux0~0 .extended_lut = "off"; +defparam \Mux0~0 .lut_mask = 64'h000000000F0F0F0F; +defparam \Mux0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N18 +cyclonev_io_ibuf \A[1]~input ( + .i(A[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[1]~input_o )); +// synopsys translate_off +defparam \A[1]~input .bus_hold = "false"; +defparam \A[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N1 +cyclonev_io_ibuf \A[0]~input ( + .i(A[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[0]~input_o )); +// synopsys translate_off +defparam \A[0]~input .bus_hold = "false"; +defparam \A[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X46_Y0_N1 +cyclonev_io_ibuf \A[2]~input ( + .i(A[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[2]~input_o )); +// synopsys translate_off +defparam \A[2]~input .bus_hold = "false"; +defparam \A[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N12 +cyclonev_lcell_comb \ShiftRight1~0 ( +// Equation(s): +// \ShiftRight1~0_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[3]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[1]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o +// & ( \A[0]~input_o ) ) ) + + .dataa(!\A[1]~input_o ), + .datab(!\A[0]~input_o ), + .datac(!\A[3]~input_o ), + .datad(!\A[2]~input_o ), + .datae(!\C[1]~input_o ), + .dataf(!\C[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight1~0 .extended_lut = "off"; +defparam \ShiftRight1~0 .lut_mask = 64'h333300FF55550F0F; +defparam \ShiftRight1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X21_Y4_N3 +cyclonev_lcell_comb \ShiftLeft1~0 ( +// Equation(s): +// \ShiftLeft1~0_combout = (\B[2]~input_o ) # (\B[3]~input_o ) + + .dataa(!\B[3]~input_o ), + .datab(!\B[2]~input_o ), + .datac(gnd), + .datad(gnd), + .datae(gnd), + .dataf(gnd), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -930,1106 +468,48 @@ cyclonev_lcell_comb \ShiftLeft1~0 ( .shareout()); // synopsys translate_off defparam \ShiftLeft1~0 .extended_lut = "off"; -defparam \ShiftLeft1~0 .lut_mask = 64'h00C000C030F030F0; +defparam \ShiftLeft1~0 .lut_mask = 64'h7777777777777777; defparam \ShiftLeft1~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X63_Y27_N45 -cyclonev_lcell_comb \ShiftRight2~0 ( +// Location: MLABCELL_X19_Y4_N15 +cyclonev_lcell_comb \ShiftRight3~0 ( // Equation(s): -// \ShiftRight2~0_combout = ( \A[5]~input_o & ( \B[1]~input_o & ( (!\B[0]~input_o & \A[7]~input_o ) ) ) ) # ( !\A[5]~input_o & ( \B[1]~input_o & ( (!\B[0]~input_o & \A[7]~input_o ) ) ) ) # ( \A[5]~input_o & ( !\B[1]~input_o & ( (!\B[0]~input_o ) # -// (\A[6]~input_o ) ) ) ) # ( !\A[5]~input_o & ( !\B[1]~input_o & ( (\A[6]~input_o & \B[0]~input_o ) ) ) ) +// \ShiftRight3~0_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[3]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[1]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o +// & ( \A[0]~input_o ) ) ) - .dataa(!\A[6]~input_o ), - .datab(!\B[0]~input_o ), - .datac(!\A[7]~input_o ), - .datad(gnd), - .datae(!\A[5]~input_o ), - .dataf(!\B[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight2~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight2~0 .extended_lut = "off"; -defparam \ShiftRight2~0 .lut_mask = 64'h1111DDDD0C0C0C0C; -defparam \ShiftRight2~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N0 -cyclonev_lcell_comb \Mux5~2 ( -// Equation(s): -// \Mux5~2_combout = ( \C[2]~input_o & ( (\op[0]~input_o & ((\ShiftLeft0~0_combout ) # (\op[2]~input_o ))) ) ) # ( !\C[2]~input_o & ( (!\op[2]~input_o & ((\ShiftLeft0~0_combout ))) # (\op[2]~input_o & (\op[0]~input_o )) ) ) - - .dataa(!\op[0]~input_o ), - .datab(gnd), - .datac(!\op[2]~input_o ), - .datad(!\ShiftLeft0~0_combout ), - .datae(gnd), - .dataf(!\C[2]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~2 .extended_lut = "off"; -defparam \Mux5~2 .lut_mask = 64'h05F505F505550555; -defparam \Mux5~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N3 -cyclonev_lcell_comb \Mux5~3 ( -// Equation(s): -// \Mux5~3_combout = ( \C[2]~input_o & ( (!\op[0]~input_o & (((\op[2]~input_o & !\B[2]~input_o )))) # (\op[0]~input_o & (\ShiftLeft0~0_combout & (!\op[2]~input_o ))) ) ) # ( !\C[2]~input_o & ( (!\op[2]~input_o & (((\ShiftLeft0~0_combout )))) # -// (\op[2]~input_o & (!\op[0]~input_o & ((!\B[2]~input_o )))) ) ) - - .dataa(!\op[0]~input_o ), - .datab(!\ShiftLeft0~0_combout ), - .datac(!\op[2]~input_o ), - .datad(!\B[2]~input_o ), - .datae(gnd), - .dataf(!\C[2]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~3_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~3 .extended_lut = "off"; -defparam \Mux5~3 .lut_mask = 64'h3A303A301A101A10; -defparam \Mux5~3 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N36 -cyclonev_lcell_comb \ShiftRight0~1 ( -// Equation(s): -// \ShiftRight0~1_combout = ( \C[1]~input_o & ( (\A[7]~input_o & !\C[0]~input_o ) ) ) # ( !\C[1]~input_o & ( (!\C[0]~input_o & ((\A[5]~input_o ))) # (\C[0]~input_o & (\A[6]~input_o )) ) ) - - .dataa(!\A[6]~input_o ), - .datab(!\A[7]~input_o ), - .datac(!\A[5]~input_o ), - .datad(!\C[0]~input_o ), - .datae(gnd), - .dataf(!\C[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight0~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight0~1 .extended_lut = "off"; -defparam \ShiftRight0~1 .lut_mask = 64'h0F550F5533003300; -defparam \ShiftRight0~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N18 -cyclonev_lcell_comb \Mux6~0 ( -// Equation(s): -// \Mux6~0_combout = ( \ShiftRight0~1_combout & ( (!\Mux5~2_combout & (\ShiftLeft1~0_combout & ((\Mux5~3_combout )))) # (\Mux5~2_combout & (((\Mux5~3_combout ) # (\ShiftRight2~0_combout )))) ) ) # ( !\ShiftRight0~1_combout & ( (!\Mux5~2_combout & -// (\ShiftLeft1~0_combout & ((\Mux5~3_combout )))) # (\Mux5~2_combout & (((\ShiftRight2~0_combout & !\Mux5~3_combout )))) ) ) - - .dataa(!\ShiftLeft1~0_combout ), - .datab(!\ShiftRight2~0_combout ), - .datac(!\Mux5~2_combout ), - .datad(!\Mux5~3_combout ), - .datae(gnd), - .dataf(!\ShiftRight0~1_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux6~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux6~0 .extended_lut = "off"; -defparam \Mux6~0 .lut_mask = 64'h03500350035F035F; -defparam \Mux6~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N30 -cyclonev_lcell_comb \Mux5~5 ( -// Equation(s): -// \Mux5~5_combout = ( \op[1]~input_o & ( (!\op[0]~input_o ) # ((!\op[2]~input_o & ((!\ShiftRight0~0_combout ))) # (\op[2]~input_o & (\B[2]~input_o ))) ) ) # ( !\op[1]~input_o & ( (!\op[2]~input_o & (\ShiftRight0~0_combout & !\op[0]~input_o )) ) ) - - .dataa(!\op[2]~input_o ), - .datab(!\B[2]~input_o ), - .datac(!\ShiftRight0~0_combout ), - .datad(!\op[0]~input_o ), - .datae(gnd), - .dataf(!\op[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~5_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~5 .extended_lut = "off"; -defparam \Mux5~5 .lut_mask = 64'h0A000A00FFB1FFB1; -defparam \Mux5~5 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N33 -cyclonev_lcell_comb \Mux6~1 ( -// Equation(s): -// \Mux6~1_combout = ( !\op[1]~input_o & ( (!\op[0]~input_o ) # ((!\op[2]~input_o & ((!\ShiftRight0~0_combout ))) # (\op[2]~input_o & (\B[2]~input_o ))) ) ) - - .dataa(!\op[2]~input_o ), - .datab(!\B[2]~input_o ), - .datac(!\ShiftRight0~0_combout ), - .datad(!\op[0]~input_o ), - .datae(gnd), - .dataf(!\op[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux6~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux6~1 .extended_lut = "off"; -defparam \Mux6~1 .lut_mask = 64'hFFB1FFB100000000; -defparam \Mux6~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N51 -cyclonev_lcell_comb \ShiftLeft0~1 ( -// Equation(s): -// \ShiftLeft0~1_combout = ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o & ( \A[1]~input_o ) ) ) - - .dataa(gnd), + .dataa(!\A[1]~input_o ), .datab(!\A[0]~input_o ), - .datac(!\A[1]~input_o ), - .datad(gnd), - .datae(!\C[1]~input_o ), - .dataf(!\C[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft0~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft0~1 .extended_lut = "off"; -defparam \ShiftLeft0~1 .lut_mask = 64'h0F0F000033330000; -defparam \ShiftLeft0~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N24 -cyclonev_lcell_comb \Mux5~6 ( -// Equation(s): -// \Mux5~6_combout = ( \C[1]~input_o & ( (!\op[2]~input_o ) # (\B[1]~input_o ) ) ) # ( !\C[1]~input_o & ( (\B[1]~input_o & \op[2]~input_o ) ) ) - - .dataa(!\B[1]~input_o ), - .datab(gnd), - .datac(!\op[2]~input_o ), - .datad(gnd), - .datae(gnd), - .dataf(!\C[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~6_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~6 .extended_lut = "off"; -defparam \Mux5~6 .lut_mask = 64'h05050505F5F5F5F5; -defparam \Mux5~6 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N27 -cyclonev_lcell_comb \Mux5~7 ( -// Equation(s): -// \Mux5~7_combout = ( \B[0]~input_o & ( (\op[2]~input_o ) # (\C[0]~input_o ) ) ) # ( !\B[0]~input_o & ( (\C[0]~input_o & !\op[2]~input_o ) ) ) - - .dataa(gnd), - .datab(gnd), - .datac(!\C[0]~input_o ), - .datad(!\op[2]~input_o ), - .datae(gnd), - .dataf(!\B[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~7_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~7 .extended_lut = "off"; -defparam \Mux5~7 .lut_mask = 64'h0F000F000FFF0FFF; -defparam \Mux5~7 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N36 -cyclonev_lcell_comb \Mux6~2 ( -// Equation(s): -// \Mux6~2_combout = ( \A[3]~input_o & ( (!\Mux5~7_combout ) # ((!\Mux5~6_combout & ((\A[2]~input_o ))) # (\Mux5~6_combout & (\A[4]~input_o ))) ) ) # ( !\A[3]~input_o & ( (\Mux5~7_combout & ((!\Mux5~6_combout & ((\A[2]~input_o ))) # (\Mux5~6_combout -// & (\A[4]~input_o )))) ) ) - - .dataa(!\A[4]~input_o ), - .datab(!\Mux5~6_combout ), .datac(!\A[2]~input_o ), - .datad(!\Mux5~7_combout ), - .datae(gnd), - .dataf(!\A[3]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux6~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux6~2 .extended_lut = "off"; -defparam \Mux6~2 .lut_mask = 64'h001D001DFF1DFF1D; -defparam \Mux6~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N30 -cyclonev_lcell_comb \Mux6~3 ( -// Equation(s): -// \Mux6~3_combout = ( \A[7]~input_o & ( \B[1]~input_o & ( \op[2]~input_o ) ) ) # ( \A[7]~input_o & ( !\B[1]~input_o & ( (\op[2]~input_o & ((!\B[0]~input_o & (\A[5]~input_o )) # (\B[0]~input_o & ((\A[6]~input_o ))))) ) ) ) # ( !\A[7]~input_o & ( -// !\B[1]~input_o & ( (\op[2]~input_o & ((!\B[0]~input_o & (\A[5]~input_o )) # (\B[0]~input_o & ((\A[6]~input_o ))))) ) ) ) - - .dataa(!\A[5]~input_o ), - .datab(!\op[2]~input_o ), - .datac(!\A[6]~input_o ), - .datad(!\B[0]~input_o ), - .datae(!\A[7]~input_o ), - .dataf(!\B[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux6~3_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux6~3 .extended_lut = "off"; -defparam \Mux6~3 .lut_mask = 64'h1103110300003333; -defparam \Mux6~3 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N9 -cyclonev_lcell_comb \ShiftRight1~3 ( -// Equation(s): -// \ShiftRight1~3_combout = ( \C[1]~input_o & ( \A[7]~input_o ) ) # ( !\C[1]~input_o & ( (!\C[0]~input_o & ((\A[5]~input_o ))) # (\C[0]~input_o & (\A[6]~input_o )) ) ) - - .dataa(!\A[6]~input_o ), - .datab(!\A[7]~input_o ), - .datac(!\A[5]~input_o ), - .datad(!\C[0]~input_o ), - .datae(gnd), - .dataf(!\C[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight1~3_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight1~3 .extended_lut = "off"; -defparam \ShiftRight1~3 .lut_mask = 64'h0F550F5533333333; -defparam \ShiftRight1~3 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N12 -cyclonev_lcell_comb \Mux6~4 ( -// Equation(s): -// \Mux6~4_combout = ( \ShiftRight1~3_combout & ( (!\Mux6~3_combout & (((!\A[7]~input_o & !\ShiftLeft0~0_combout )) # (\op[2]~input_o ))) ) ) # ( !\ShiftRight1~3_combout & ( (!\Mux6~3_combout & (((!\A[7]~input_o ) # (\ShiftLeft0~0_combout )) # -// (\op[2]~input_o ))) ) ) - - .dataa(!\op[2]~input_o ), - .datab(!\A[7]~input_o ), - .datac(!\ShiftLeft0~0_combout ), - .datad(!\Mux6~3_combout ), - .datae(gnd), - .dataf(!\ShiftRight1~3_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux6~4_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux6~4 .extended_lut = "off"; -defparam \Mux6~4 .lut_mask = 64'hDF00DF00D500D500; -defparam \Mux6~4 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N51 -cyclonev_lcell_comb \Mux6~5 ( -// Equation(s): -// \Mux6~5_combout = ( \Mux6~4_combout & ( (!\Mux6~1_combout & (!\Mux5~5_combout & ((\Mux6~2_combout )))) # (\Mux6~1_combout & (((\ShiftLeft0~1_combout )))) ) ) # ( !\Mux6~4_combout & ( (!\Mux6~1_combout & (((\Mux6~2_combout )) # (\Mux5~5_combout ))) -// # (\Mux6~1_combout & (((\ShiftLeft0~1_combout )))) ) ) - - .dataa(!\Mux5~5_combout ), - .datab(!\Mux6~1_combout ), - .datac(!\ShiftLeft0~1_combout ), - .datad(!\Mux6~2_combout ), - .datae(gnd), - .dataf(!\Mux6~4_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux6~5_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux6~5 .extended_lut = "off"; -defparam \Mux6~5 .lut_mask = 64'h47CF47CF038B038B; -defparam \Mux6~5 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N0 -cyclonev_lcell_comb \Mux6~6 ( -// Equation(s): -// \Mux6~6_combout = ( \Mux6~5_combout & ( (!\Mux5~1_combout & ((!\Mux5~4_combout ) # ((\Mux6~0_combout )))) # (\Mux5~1_combout & (((\A[1]~input_o )))) ) ) # ( !\Mux6~5_combout & ( (!\Mux5~1_combout & (\Mux5~4_combout & (\Mux6~0_combout ))) # -// (\Mux5~1_combout & (((\A[1]~input_o )))) ) ) - - .dataa(!\Mux5~4_combout ), - .datab(!\Mux5~1_combout ), - .datac(!\Mux6~0_combout ), - .datad(!\A[1]~input_o ), - .datae(gnd), - .dataf(!\Mux6~5_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux6~6_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux6~6 .extended_lut = "off"; -defparam \Mux6~6 .lut_mask = 64'h043704378CBF8CBF; -defparam \Mux6~6 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N6 -cyclonev_lcell_comb \ShiftRight0~2 ( -// Equation(s): -// \ShiftRight0~2_combout = ( !\C[1]~input_o & ( (!\C[0]~input_o & (\A[6]~input_o )) # (\C[0]~input_o & ((\A[7]~input_o ))) ) ) - - .dataa(!\A[6]~input_o ), - .datab(!\A[7]~input_o ), - .datac(gnd), - .datad(!\C[0]~input_o ), - .datae(gnd), - .dataf(!\C[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight0~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight0~2 .extended_lut = "off"; -defparam \ShiftRight0~2 .lut_mask = 64'h5533553300000000; -defparam \ShiftRight0~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N15 -cyclonev_lcell_comb \ShiftRight2~1 ( -// Equation(s): -// \ShiftRight2~1_combout = ( !\B[1]~input_o & ( (!\B[0]~input_o & (\A[6]~input_o )) # (\B[0]~input_o & ((\A[7]~input_o ))) ) ) - - .dataa(!\A[6]~input_o ), - .datab(!\A[7]~input_o ), - .datac(!\B[0]~input_o ), - .datad(gnd), - .datae(gnd), - .dataf(!\B[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight2~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight2~1 .extended_lut = "off"; -defparam \ShiftRight2~1 .lut_mask = 64'h5353535300000000; -defparam \ShiftRight2~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N39 -cyclonev_lcell_comb \ShiftLeft1~1 ( -// Equation(s): -// \ShiftLeft1~1_combout = ( \B[0]~input_o & ( (!\B[1]~input_o & \A[1]~input_o ) ) ) # ( !\B[0]~input_o & ( (!\B[1]~input_o & ((\A[2]~input_o ))) # (\B[1]~input_o & (\A[0]~input_o )) ) ) - - .dataa(!\B[1]~input_o ), - .datab(!\A[0]~input_o ), - .datac(!\A[1]~input_o ), - .datad(!\A[2]~input_o ), - .datae(gnd), - .dataf(!\B[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft1~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft1~1 .extended_lut = "off"; -defparam \ShiftLeft1~1 .lut_mask = 64'h11BB11BB0A0A0A0A; -defparam \ShiftLeft1~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N48 -cyclonev_lcell_comb \Mux5~8 ( -// Equation(s): -// \Mux5~8_combout = ( \ShiftLeft1~1_combout & ( (!\Mux5~2_combout & (((\Mux5~3_combout )))) # (\Mux5~2_combout & ((!\Mux5~3_combout & ((\ShiftRight2~1_combout ))) # (\Mux5~3_combout & (\ShiftRight0~2_combout )))) ) ) # ( !\ShiftLeft1~1_combout & ( -// (\Mux5~2_combout & ((!\Mux5~3_combout & ((\ShiftRight2~1_combout ))) # (\Mux5~3_combout & (\ShiftRight0~2_combout )))) ) ) - - .dataa(!\ShiftRight0~2_combout ), - .datab(!\ShiftRight2~1_combout ), - .datac(!\Mux5~2_combout ), - .datad(!\Mux5~3_combout ), - .datae(gnd), - .dataf(!\ShiftLeft1~1_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~8_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~8 .extended_lut = "off"; -defparam \Mux5~8 .lut_mask = 64'h0305030503F503F5; -defparam \Mux5~8 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N12 -cyclonev_lcell_comb \ShiftLeft0~2 ( -// Equation(s): -// \ShiftLeft0~2_combout = ( \A[2]~input_o & ( \A[0]~input_o & ( (!\C[0]~input_o ) # ((\A[1]~input_o & !\C[1]~input_o )) ) ) ) # ( !\A[2]~input_o & ( \A[0]~input_o & ( (!\C[1]~input_o & (\A[1]~input_o & \C[0]~input_o )) # (\C[1]~input_o & -// ((!\C[0]~input_o ))) ) ) ) # ( \A[2]~input_o & ( !\A[0]~input_o & ( (!\C[1]~input_o & ((!\C[0]~input_o ) # (\A[1]~input_o ))) ) ) ) # ( !\A[2]~input_o & ( !\A[0]~input_o & ( (\A[1]~input_o & (!\C[1]~input_o & \C[0]~input_o )) ) ) ) - - .dataa(gnd), - .datab(!\A[1]~input_o ), - .datac(!\C[1]~input_o ), - .datad(!\C[0]~input_o ), - .datae(!\A[2]~input_o ), - .dataf(!\A[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft0~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft0~2 .extended_lut = "off"; -defparam \ShiftLeft0~2 .lut_mask = 64'h0030F0300F30FF30; -defparam \ShiftLeft0~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N12 -cyclonev_lcell_comb \ShiftRight1~4 ( -// Equation(s): -// \ShiftRight1~4_combout = ( \C[1]~input_o & ( \A[7]~input_o ) ) # ( !\C[1]~input_o & ( (!\C[0]~input_o & (\A[6]~input_o )) # (\C[0]~input_o & ((\A[7]~input_o ))) ) ) - - .dataa(!\A[6]~input_o ), - .datab(!\A[7]~input_o ), - .datac(gnd), - .datad(!\C[0]~input_o ), - .datae(gnd), - .dataf(!\C[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight1~4_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight1~4 .extended_lut = "off"; -defparam \ShiftRight1~4 .lut_mask = 64'h5533553333333333; -defparam \ShiftRight1~4 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N39 -cyclonev_lcell_comb \Mux5~10 ( -// Equation(s): -// \Mux5~10_combout = ( \B[1]~input_o & ( (\A[7]~input_o & \op[2]~input_o ) ) ) # ( !\B[1]~input_o & ( (\op[2]~input_o & ((!\B[0]~input_o & (\A[6]~input_o )) # (\B[0]~input_o & ((\A[7]~input_o ))))) ) ) - - .dataa(!\A[6]~input_o ), - .datab(!\A[7]~input_o ), - .datac(!\B[0]~input_o ), - .datad(!\op[2]~input_o ), - .datae(gnd), - .dataf(!\B[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~10_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~10 .extended_lut = "off"; -defparam \Mux5~10 .lut_mask = 64'h0053005300330033; -defparam \Mux5~10 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N15 -cyclonev_lcell_comb \Mux5~11 ( -// Equation(s): -// \Mux5~11_combout = ( \ShiftLeft0~0_combout & ( (!\Mux5~10_combout & ((!\ShiftRight1~4_combout ) # (\op[2]~input_o ))) ) ) # ( !\ShiftLeft0~0_combout & ( (!\Mux5~10_combout & ((!\A[7]~input_o ) # (\op[2]~input_o ))) ) ) - - .dataa(!\op[2]~input_o ), - .datab(!\A[7]~input_o ), - .datac(!\ShiftRight1~4_combout ), - .datad(!\Mux5~10_combout ), - .datae(gnd), - .dataf(!\ShiftLeft0~0_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~11_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~11 .extended_lut = "off"; -defparam \Mux5~11 .lut_mask = 64'hDD00DD00F500F500; -defparam \Mux5~11 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N39 -cyclonev_lcell_comb \Mux5~9 ( -// Equation(s): -// \Mux5~9_combout = ( \A[5]~input_o & ( (!\Mux5~7_combout & (\A[4]~input_o )) # (\Mux5~7_combout & (((\A[3]~input_o ) # (\Mux5~6_combout )))) ) ) # ( !\A[5]~input_o & ( (!\Mux5~7_combout & (\A[4]~input_o )) # (\Mux5~7_combout & (((!\Mux5~6_combout & -// \A[3]~input_o )))) ) ) - - .dataa(!\A[4]~input_o ), - .datab(!\Mux5~6_combout ), - .datac(!\A[3]~input_o ), - .datad(!\Mux5~7_combout ), - .datae(gnd), - .dataf(!\A[5]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~9_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~9 .extended_lut = "off"; -defparam \Mux5~9 .lut_mask = 64'h550C550C553F553F; -defparam \Mux5~9 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N48 -cyclonev_lcell_comb \Mux5~12 ( -// Equation(s): -// \Mux5~12_combout = ( \Mux5~9_combout & ( (!\Mux6~1_combout & ((!\Mux5~5_combout ) # ((!\Mux5~11_combout )))) # (\Mux6~1_combout & (((\ShiftLeft0~2_combout )))) ) ) # ( !\Mux5~9_combout & ( (!\Mux6~1_combout & (\Mux5~5_combout & ((!\Mux5~11_combout -// )))) # (\Mux6~1_combout & (((\ShiftLeft0~2_combout )))) ) ) - - .dataa(!\Mux5~5_combout ), - .datab(!\Mux6~1_combout ), - .datac(!\ShiftLeft0~2_combout ), - .datad(!\Mux5~11_combout ), - .datae(gnd), - .dataf(!\Mux5~9_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~12_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~12 .extended_lut = "off"; -defparam \Mux5~12 .lut_mask = 64'h47034703CF8BCF8B; -defparam \Mux5~12 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N3 -cyclonev_lcell_comb \Mux5~13 ( -// Equation(s): -// \Mux5~13_combout = ( \Mux5~12_combout & ( (!\Mux5~1_combout & ((!\Mux5~4_combout ) # ((\Mux5~8_combout )))) # (\Mux5~1_combout & (((\A[2]~input_o )))) ) ) # ( !\Mux5~12_combout & ( (!\Mux5~1_combout & (\Mux5~4_combout & (\Mux5~8_combout ))) # -// (\Mux5~1_combout & (((\A[2]~input_o )))) ) ) - - .dataa(!\Mux5~4_combout ), - .datab(!\Mux5~1_combout ), - .datac(!\Mux5~8_combout ), - .datad(!\A[2]~input_o ), - .datae(gnd), - .dataf(!\Mux5~12_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~13_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~13 .extended_lut = "off"; -defparam \Mux5~13 .lut_mask = 64'h043704378CBF8CBF; -defparam \Mux5~13 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N6 -cyclonev_lcell_comb \ShiftRight1~5 ( -// Equation(s): -// \ShiftRight1~5_combout = ( \C[0]~input_o & ( \C[1]~input_o & ( \A[6]~input_o ) ) ) # ( !\C[0]~input_o & ( \C[1]~input_o & ( \A[5]~input_o ) ) ) # ( \C[0]~input_o & ( !\C[1]~input_o & ( \A[4]~input_o ) ) ) # ( !\C[0]~input_o & ( !\C[1]~input_o -// & ( \A[3]~input_o ) ) ) - - .dataa(!\A[4]~input_o ), - .datab(!\A[3]~input_o ), - .datac(!\A[5]~input_o ), - .datad(!\A[6]~input_o ), - .datae(!\C[0]~input_o ), - .dataf(!\C[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight1~5_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight1~5 .extended_lut = "off"; -defparam \ShiftRight1~5 .lut_mask = 64'h333355550F0F00FF; -defparam \ShiftRight1~5 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y28_N0 -cyclonev_lcell_comb \ShiftRight0~3 ( -// Equation(s): -// \ShiftRight0~3_combout = ( \A[7]~input_o & ( (\ShiftLeft0~0_combout & ((!\C[2]~input_o & (\ShiftRight1~5_combout )) # (\C[2]~input_o & ((\ShiftRight1~2_combout ))))) ) ) # ( !\A[7]~input_o & ( (\ShiftRight1~5_combout & (!\C[2]~input_o & -// \ShiftLeft0~0_combout )) ) ) - - .dataa(!\ShiftRight1~5_combout ), - .datab(!\C[2]~input_o ), - .datac(!\ShiftLeft0~0_combout ), - .datad(!\ShiftRight1~2_combout ), - .datae(gnd), - .dataf(!\A[7]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight0~3_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight0~3 .extended_lut = "off"; -defparam \ShiftRight0~3 .lut_mask = 64'h0404040404070407; -defparam \ShiftRight0~3 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N18 -cyclonev_lcell_comb \ShiftLeft0~3 ( -// Equation(s): -// \ShiftLeft0~3_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[2]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o & -// ( \A[3]~input_o ) ) ) - - .dataa(!\A[3]~input_o ), - .datab(!\A[1]~input_o ), - .datac(!\A[2]~input_o ), - .datad(!\A[0]~input_o ), - .datae(!\C[1]~input_o ), - .dataf(!\C[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft0~3_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft0~3 .extended_lut = "off"; -defparam \ShiftLeft0~3 .lut_mask = 64'h555533330F0F00FF; -defparam \ShiftLeft0~3 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N21 -cyclonev_lcell_comb \ShiftLeft1~2 ( -// Equation(s): -// \ShiftLeft1~2_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[2]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o & -// ( \A[3]~input_o ) ) ) - - .dataa(!\A[3]~input_o ), - .datab(!\A[1]~input_o ), - .datac(!\A[0]~input_o ), - .datad(!\A[2]~input_o ), + .datad(!\A[3]~input_o ), .datae(!\B[1]~input_o ), .dataf(!\B[0]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\ShiftLeft1~2_combout ), + .combout(\ShiftRight3~0_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \ShiftLeft1~2 .extended_lut = "off"; -defparam \ShiftLeft1~2 .lut_mask = 64'h5555333300FF0F0F; -defparam \ShiftLeft1~2 .shared_arith = "off"; +defparam \ShiftRight3~0 .extended_lut = "off"; +defparam \ShiftRight3~0 .lut_mask = 64'h33330F0F555500FF; +defparam \ShiftRight3~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y28_N3 -cyclonev_lcell_comb \ShiftLeft1~3 ( -// Equation(s): -// \ShiftLeft1~3_combout = ( !\B[2]~input_o & ( \ShiftLeft1~2_combout ) ) - - .dataa(gnd), - .datab(gnd), - .datac(!\ShiftLeft1~2_combout ), - .datad(gnd), - .datae(gnd), - .dataf(!\B[2]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft1~3_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft1~3 .extended_lut = "off"; -defparam \ShiftLeft1~3 .lut_mask = 64'h0F0F0F0F00000000; -defparam \ShiftLeft1~3 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N9 -cyclonev_lcell_comb \ShiftRight3~2 ( -// Equation(s): -// \ShiftRight3~2_combout = ( \B[0]~input_o & ( \B[1]~input_o & ( \A[6]~input_o ) ) ) # ( !\B[0]~input_o & ( \B[1]~input_o & ( \A[5]~input_o ) ) ) # ( \B[0]~input_o & ( !\B[1]~input_o & ( \A[4]~input_o ) ) ) # ( !\B[0]~input_o & ( !\B[1]~input_o -// & ( \A[3]~input_o ) ) ) - - .dataa(!\A[4]~input_o ), - .datab(!\A[3]~input_o ), - .datac(!\A[6]~input_o ), - .datad(!\A[5]~input_o ), - .datae(!\B[0]~input_o ), - .dataf(!\B[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight3~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight3~2 .extended_lut = "off"; -defparam \ShiftRight3~2 .lut_mask = 64'h3333555500FF0F0F; -defparam \ShiftRight3~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X67_Y28_N33 -cyclonev_lcell_comb \ShiftRight2~2 ( -// Equation(s): -// \ShiftRight2~2_combout = ( \B[2]~input_o & ( (!\B[0]~input_o & (\A[7]~input_o & !\B[1]~input_o )) ) ) # ( !\B[2]~input_o & ( \ShiftRight3~2_combout ) ) - - .dataa(!\ShiftRight3~2_combout ), - .datab(!\B[0]~input_o ), - .datac(!\A[7]~input_o ), - .datad(!\B[1]~input_o ), - .datae(!\B[2]~input_o ), - .dataf(gnd), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight2~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight2~2 .extended_lut = "off"; -defparam \ShiftRight2~2 .lut_mask = 64'h55550C0055550C00; -defparam \ShiftRight2~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y28_N30 -cyclonev_lcell_comb \Mux4~2 ( -// Equation(s): -// \Mux4~2_combout = ( !\op[2]~input_o & ( ((!\op[0]~input_o & (((\ShiftLeft0~3_combout & \ShiftRight0~0_combout )))) # (\op[0]~input_o & (\ShiftRight0~3_combout ))) ) ) # ( \op[2]~input_o & ( (((!\op[0]~input_o & (\ShiftLeft1~3_combout )) # -// (\op[0]~input_o & ((\ShiftRight2~2_combout ))))) ) ) - - .dataa(!\ShiftRight0~3_combout ), - .datab(!\ShiftLeft0~3_combout ), - .datac(!\ShiftLeft1~3_combout ), - .datad(!\ShiftRight2~2_combout ), - .datae(!\op[2]~input_o ), - .dataf(!\op[0]~input_o ), - .datag(!\ShiftRight0~0_combout ), - .cin(gnd), - .sharein(gnd), - .combout(\Mux4~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux4~2 .extended_lut = "on"; -defparam \Mux4~2 .lut_mask = 64'h03030F0F555500FF; -defparam \Mux4~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N45 -cyclonev_lcell_comb \Mux4~0 ( -// Equation(s): -// \Mux4~0_combout = ( \ShiftRight1~5_combout & ( \ShiftRight3~2_combout & ( ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) # (\A[7]~input_o ) ) ) ) # ( !\ShiftRight1~5_combout & ( \ShiftRight3~2_combout & ( -// (!\op[2]~input_o & (!\ShiftRight0~0_combout & ((\A[7]~input_o )))) # (\op[2]~input_o & (((!\B[2]~input_o ) # (\A[7]~input_o )))) ) ) ) # ( \ShiftRight1~5_combout & ( !\ShiftRight3~2_combout & ( (!\op[2]~input_o & (((\A[7]~input_o )) # -// (\ShiftRight0~0_combout ))) # (\op[2]~input_o & (((\B[2]~input_o & \A[7]~input_o )))) ) ) ) # ( !\ShiftRight1~5_combout & ( !\ShiftRight3~2_combout & ( (\A[7]~input_o & ((!\op[2]~input_o & (!\ShiftRight0~0_combout )) # (\op[2]~input_o & -// ((\B[2]~input_o ))))) ) ) ) - - .dataa(!\ShiftRight0~0_combout ), - .datab(!\op[2]~input_o ), - .datac(!\B[2]~input_o ), - .datad(!\A[7]~input_o ), - .datae(!\ShiftRight1~5_combout ), - .dataf(!\ShiftRight3~2_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux4~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux4~0 .extended_lut = "off"; -defparam \Mux4~0 .lut_mask = 64'h008B44CF30BB74FF; -defparam \Mux4~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N24 -cyclonev_lcell_comb \Mux4~1 ( -// Equation(s): -// \Mux4~1_combout = ( \op[1]~input_o & ( (!\op[0]~input_o & (\A[3]~input_o )) # (\op[0]~input_o & ((\Mux4~0_combout ))) ) ) # ( !\op[1]~input_o & ( \Mux4~2_combout ) ) - - .dataa(!\A[3]~input_o ), - .datab(!\Mux4~2_combout ), - .datac(!\Mux4~0_combout ), - .datad(!\op[0]~input_o ), - .datae(gnd), - .dataf(!\op[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux4~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux4~1 .extended_lut = "off"; -defparam \Mux4~1 .lut_mask = 64'h33333333550F550F; -defparam \Mux4~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N54 -cyclonev_lcell_comb \ShiftLeft0~4 ( -// Equation(s): -// \ShiftLeft0~4_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[3]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o & -// ( \A[4]~input_o ) ) ) - - .dataa(!\A[3]~input_o ), - .datab(!\A[4]~input_o ), - .datac(!\A[2]~input_o ), - .datad(!\A[1]~input_o ), - .datae(!\C[1]~input_o ), - .dataf(!\C[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft0~4_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft0~4 .extended_lut = "off"; -defparam \ShiftLeft0~4 .lut_mask = 64'h33330F0F555500FF; -defparam \ShiftLeft0~4 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N18 -cyclonev_lcell_comb \ShiftLeft0~5 ( -// Equation(s): -// \ShiftLeft0~5_combout = ( \C[2]~input_o & ( (\ShiftLeft0~0_combout & (\A[0]~input_o & \ShiftRight1~2_combout )) ) ) # ( !\C[2]~input_o & ( (\ShiftLeft0~0_combout & \ShiftLeft0~4_combout ) ) ) - - .dataa(!\ShiftLeft0~0_combout ), - .datab(!\A[0]~input_o ), - .datac(!\ShiftLeft0~4_combout ), - .datad(!\ShiftRight1~2_combout ), - .datae(gnd), - .dataf(!\C[2]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft0~5_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft0~5 .extended_lut = "off"; -defparam \ShiftLeft0~5 .lut_mask = 64'h0505050500110011; -defparam \ShiftLeft0~5 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N57 -cyclonev_lcell_comb \ShiftLeft1~4 ( -// Equation(s): -// \ShiftLeft1~4_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[3]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o & -// ( \A[4]~input_o ) ) ) - - .dataa(!\A[3]~input_o ), - .datab(!\A[4]~input_o ), - .datac(!\A[1]~input_o ), - .datad(!\A[2]~input_o ), - .datae(!\B[1]~input_o ), - .dataf(!\B[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft1~4_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft1~4 .extended_lut = "off"; -defparam \ShiftLeft1~4 .lut_mask = 64'h333300FF55550F0F; -defparam \ShiftLeft1~4 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y27_N36 -cyclonev_lcell_comb \ShiftLeft1~5 ( -// Equation(s): -// \ShiftLeft1~5_combout = ( \B[0]~input_o & ( (!\B[2]~input_o & \ShiftLeft1~4_combout ) ) ) # ( !\B[0]~input_o & ( (!\B[2]~input_o & (((\ShiftLeft1~4_combout )))) # (\B[2]~input_o & (!\B[1]~input_o & (\A[0]~input_o ))) ) ) - - .dataa(!\B[1]~input_o ), - .datab(!\A[0]~input_o ), - .datac(!\B[2]~input_o ), - .datad(!\ShiftLeft1~4_combout ), - .datae(gnd), - .dataf(!\B[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft1~5_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft1~5 .extended_lut = "off"; -defparam \ShiftLeft1~5 .lut_mask = 64'h02F202F200F000F0; -defparam \ShiftLeft1~5 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N21 -cyclonev_lcell_comb \ShiftRight2~3 ( -// Equation(s): -// \ShiftRight2~3_combout = ( \ShiftRight3~0_combout & ( !\B[2]~input_o ) ) - - .dataa(gnd), - .datab(gnd), - .datac(!\B[2]~input_o ), - .datad(gnd), - .datae(gnd), - .dataf(!\ShiftRight3~0_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight2~3_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight2~3 .extended_lut = "off"; -defparam \ShiftRight2~3 .lut_mask = 64'h00000000F0F0F0F0; -defparam \ShiftRight2~3 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N0 -cyclonev_lcell_comb \Mux3~2 ( -// Equation(s): -// \Mux3~2_combout = ( !\op[2]~input_o & ( ((!\op[0]~input_o & (\ShiftLeft0~5_combout )) # (\op[0]~input_o & (((\ShiftRight1~0_combout & \ShiftRight0~0_combout ))))) ) ) # ( \op[2]~input_o & ( (((!\op[0]~input_o & (\ShiftLeft1~5_combout )) # -// (\op[0]~input_o & ((\ShiftRight2~3_combout ))))) ) ) - - .dataa(!\ShiftLeft0~5_combout ), - .datab(!\ShiftRight1~0_combout ), - .datac(!\ShiftLeft1~5_combout ), - .datad(!\ShiftRight2~3_combout ), - .datae(!\op[2]~input_o ), - .dataf(!\op[0]~input_o ), - .datag(!\ShiftRight0~0_combout ), - .cin(gnd), - .sharein(gnd), - .combout(\Mux3~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux3~2 .extended_lut = "on"; -defparam \Mux3~2 .lut_mask = 64'h55550F0F030300FF; -defparam \Mux3~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N42 -cyclonev_lcell_comb \Mux3~0 ( -// Equation(s): -// \Mux3~0_combout = ( \ShiftRight1~0_combout & ( \ShiftRight3~0_combout & ( ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) # (\A[7]~input_o ) ) ) ) # ( !\ShiftRight1~0_combout & ( \ShiftRight3~0_combout & ( -// (!\op[2]~input_o & (!\ShiftRight0~0_combout & (\A[7]~input_o ))) # (\op[2]~input_o & (((!\B[2]~input_o ) # (\A[7]~input_o )))) ) ) ) # ( \ShiftRight1~0_combout & ( !\ShiftRight3~0_combout & ( (!\op[2]~input_o & (((\A[7]~input_o )) # -// (\ShiftRight0~0_combout ))) # (\op[2]~input_o & (((\A[7]~input_o & \B[2]~input_o )))) ) ) ) # ( !\ShiftRight1~0_combout & ( !\ShiftRight3~0_combout & ( (\A[7]~input_o & ((!\op[2]~input_o & (!\ShiftRight0~0_combout )) # (\op[2]~input_o & -// ((\B[2]~input_o ))))) ) ) ) - - .dataa(!\ShiftRight0~0_combout ), - .datab(!\op[2]~input_o ), - .datac(!\A[7]~input_o ), - .datad(!\B[2]~input_o ), - .datae(!\ShiftRight1~0_combout ), - .dataf(!\ShiftRight3~0_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux3~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux3~0 .extended_lut = "off"; -defparam \Mux3~0 .lut_mask = 64'h080B4C4F3B0B7F4F; -defparam \Mux3~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N30 +// Location: MLABCELL_X19_Y4_N54 cyclonev_lcell_comb \Mux3~1 ( // Equation(s): -// \Mux3~1_combout = ( \Mux3~0_combout & ( (!\op[1]~input_o & (((\Mux3~2_combout )))) # (\op[1]~input_o & (((\A[4]~input_o )) # (\op[0]~input_o ))) ) ) # ( !\Mux3~0_combout & ( (!\op[1]~input_o & (((\Mux3~2_combout )))) # (\op[1]~input_o & -// (!\op[0]~input_o & ((\A[4]~input_o )))) ) ) +// \Mux3~1_combout = ( \ShiftLeft1~0_combout & ( \ShiftRight3~0_combout & ( (\op[0]~input_o & ((!\op[2]~input_o & ((\ShiftRight1~0_combout ))) # (\op[2]~input_o & (\Mux0~0_combout )))) ) ) ) # ( !\ShiftLeft1~0_combout & ( \ShiftRight3~0_combout & ( +// (\op[0]~input_o & ((\ShiftRight1~0_combout ) # (\op[2]~input_o ))) ) ) ) # ( \ShiftLeft1~0_combout & ( !\ShiftRight3~0_combout & ( (\op[0]~input_o & ((!\op[2]~input_o & ((\ShiftRight1~0_combout ))) # (\op[2]~input_o & (\Mux0~0_combout )))) ) ) ) # ( +// !\ShiftLeft1~0_combout & ( !\ShiftRight3~0_combout & ( (!\op[2]~input_o & (\op[0]~input_o & \ShiftRight1~0_combout )) ) ) ) - .dataa(!\op[0]~input_o ), - .datab(!\op[1]~input_o ), - .datac(!\Mux3~2_combout ), - .datad(!\A[4]~input_o ), - .datae(gnd), - .dataf(!\Mux3~0_combout ), + .dataa(!\op[2]~input_o ), + .datab(!\op[0]~input_o ), + .datac(!\Mux0~0_combout ), + .datad(!\ShiftRight1~0_combout ), + .datae(!\ShiftLeft1~0_combout ), + .dataf(!\ShiftRight3~0_combout ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -2039,166 +519,67 @@ cyclonev_lcell_comb \Mux3~1 ( .shareout()); // synopsys translate_off defparam \Mux3~1 .extended_lut = "off"; -defparam \Mux3~1 .lut_mask = 64'h0C2E0C2E1D3F1D3F; +defparam \Mux3~1 .lut_mask = 64'h0022012311330123; defparam \Mux3~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y27_N3 -cyclonev_lcell_comb \Mux1~4 ( +// Location: MLABCELL_X19_Y4_N18 +cyclonev_lcell_comb \Mux3~2 ( // Equation(s): -// \Mux1~4_combout = ( \ShiftLeft0~0_combout & ( (!\op[1]~input_o & (((\op[2]~input_o & \B[2]~input_o )) # (\op[0]~input_o ))) ) ) # ( !\ShiftLeft0~0_combout & ( (!\op[1]~input_o & ((!\op[2]~input_o ) # ((\op[0]~input_o ) # (\B[2]~input_o )))) ) ) +// \Mux3~2_combout = ( \A[0]~input_o & ( ((!\Mux3~0_combout & !\op[0]~input_o )) # (\Mux3~1_combout ) ) ) # ( !\A[0]~input_o & ( \Mux3~1_combout ) ) - .dataa(!\op[2]~input_o ), - .datab(!\op[1]~input_o ), - .datac(!\B[2]~input_o ), + .dataa(gnd), + .datab(!\Mux3~0_combout ), + .datac(!\Mux3~1_combout ), .datad(!\op[0]~input_o ), .datae(gnd), - .dataf(!\ShiftLeft0~0_combout ), + .dataf(!\A[0]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\Mux1~4_combout ), + .combout(\Mux3~2_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \Mux1~4 .extended_lut = "off"; -defparam \Mux1~4 .lut_mask = 64'h8CCC8CCC04CC04CC; -defparam \Mux1~4 .shared_arith = "off"; +defparam \Mux3~2 .extended_lut = "off"; +defparam \Mux3~2 .lut_mask = 64'h0F0F0F0FCF0FCF0F; +defparam \Mux3~2 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X63_Y27_N27 -cyclonev_lcell_comb \Mux1~0 ( +// Location: LABCELL_X21_Y4_N12 +cyclonev_lcell_comb \Mux2~4 ( // Equation(s): -// \Mux1~0_combout = ( !\op[0]~input_o & ( ((!\op[2]~input_o & ((!\C[1]~input_o ))) # (\op[2]~input_o & (!\B[1]~input_o ))) # (\op[1]~input_o ) ) ) +// \Mux2~4_combout = ( \op[2]~input_o & ( (\A[1]~input_o & !\op[0]~input_o ) ) ) # ( !\op[2]~input_o & ( (\A[1]~input_o & ((!\op[0]~input_o ) # ((!\C[0]~input_o & !\C[1]~input_o )))) ) ) - .dataa(!\B[1]~input_o ), - .datab(!\C[1]~input_o ), - .datac(!\op[1]~input_o ), - .datad(!\op[2]~input_o ), + .dataa(!\C[0]~input_o ), + .datab(!\A[1]~input_o ), + .datac(!\op[0]~input_o ), + .datad(!\C[1]~input_o ), .datae(gnd), - .dataf(!\op[0]~input_o ), + .dataf(!\op[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\Mux1~0_combout ), + .combout(\Mux2~4_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \Mux1~0 .extended_lut = "off"; -defparam \Mux1~0 .lut_mask = 64'hCFAFCFAF00000000; -defparam \Mux1~0 .shared_arith = "off"; +defparam \Mux2~4 .extended_lut = "off"; +defparam \Mux2~4 .lut_mask = 64'h3230323030303030; +defparam \Mux2~4 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y27_N24 -cyclonev_lcell_comb \Mux1~1 ( -// Equation(s): -// \Mux1~1_combout = ( \Mux5~7_combout & ( \Mux1~0_combout & ( \op[1]~input_o ) ) ) # ( !\Mux5~7_combout & ( \Mux1~0_combout & ( ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) # (\op[1]~input_o ) ) ) ) - - .dataa(!\ShiftRight0~0_combout ), - .datab(!\B[2]~input_o ), - .datac(!\op[2]~input_o ), - .datad(!\op[1]~input_o ), - .datae(!\Mux5~7_combout ), - .dataf(!\Mux1~0_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux1~1_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux1~1 .extended_lut = "off"; -defparam \Mux1~1 .lut_mask = 64'h000000005CFF00FF; -defparam \Mux1~1 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y28_N48 -cyclonev_lcell_comb \Mux1~6 ( -// Equation(s): -// \Mux1~6_combout = ( !\op[1]~input_o & ( (!\op[0]~input_o & ((!\op[2]~input_o & ((\ShiftLeft0~0_combout ))) # (\op[2]~input_o & (!\B[2]~input_o )))) ) ) - - .dataa(!\op[0]~input_o ), - .datab(!\B[2]~input_o ), - .datac(!\ShiftLeft0~0_combout ), - .datad(!\op[2]~input_o ), - .datae(gnd), - .dataf(!\op[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux1~6_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux1~6 .extended_lut = "off"; -defparam \Mux1~6 .lut_mask = 64'h0A880A8800000000; -defparam \Mux1~6 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N0 -cyclonev_lcell_comb \Mux1~5 ( -// Equation(s): -// \Mux1~5_combout = ( \B[2]~input_o & ( (!\op[1]~input_o & (((!\ShiftRight0~0_combout ) # (\op[0]~input_o )) # (\op[2]~input_o ))) ) ) # ( !\B[2]~input_o & ( (!\op[1]~input_o & (((!\op[2]~input_o & !\ShiftRight0~0_combout )) # (\op[0]~input_o ))) ) ) - - .dataa(!\op[2]~input_o ), - .datab(!\op[1]~input_o ), - .datac(!\ShiftRight0~0_combout ), - .datad(!\op[0]~input_o ), - .datae(gnd), - .dataf(!\B[2]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux1~5_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux1~5 .extended_lut = "off"; -defparam \Mux1~5 .lut_mask = 64'h80CC80CCC4CCC4CC; -defparam \Mux1~5 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N42 -cyclonev_lcell_comb \Mux2~2 ( -// Equation(s): -// \Mux2~2_combout = ( \Mux6~3_combout & ( \ShiftRight1~3_combout & ( (!\A[7]~input_o & ((!\op[2]~input_o & (!\ShiftRight0~0_combout )) # (\op[2]~input_o & ((\B[2]~input_o ))))) ) ) ) # ( !\Mux6~3_combout & ( \ShiftRight1~3_combout & ( -// (!\op[2]~input_o & (!\ShiftRight0~0_combout & (!\A[7]~input_o ))) # (\op[2]~input_o & (((!\A[7]~input_o ) # (!\B[2]~input_o )))) ) ) ) # ( \Mux6~3_combout & ( !\ShiftRight1~3_combout & ( (!\A[7]~input_o & ((!\op[2]~input_o & -// (!\ShiftRight0~0_combout )) # (\op[2]~input_o & ((\B[2]~input_o ))))) ) ) ) # ( !\Mux6~3_combout & ( !\ShiftRight1~3_combout & ( (!\A[7]~input_o ) # ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) ) ) ) - - .dataa(!\op[2]~input_o ), - .datab(!\ShiftRight0~0_combout ), - .datac(!\A[7]~input_o ), - .datad(!\B[2]~input_o ), - .datae(!\Mux6~3_combout ), - .dataf(!\ShiftRight1~3_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux2~2_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux2~2 .extended_lut = "off"; -defparam \Mux2~2 .lut_mask = 64'hF7F280D0D5D080D0; -defparam \Mux2~2 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N6 +// Location: MLABCELL_X19_Y4_N33 cyclonev_lcell_comb \Mux2~1 ( // Equation(s): -// \Mux2~1_combout = ( \A[3]~input_o & ( (!\Mux5~7_combout ) # ((!\Mux5~6_combout & (\A[4]~input_o )) # (\Mux5~6_combout & ((\A[2]~input_o )))) ) ) # ( !\A[3]~input_o & ( (\Mux5~7_combout & ((!\Mux5~6_combout & (\A[4]~input_o )) # (\Mux5~6_combout & -// ((\A[2]~input_o ))))) ) ) +// \Mux2~1_combout = ( \A[3]~input_o & ( ((\C[0]~input_o & \A[2]~input_o )) # (\C[1]~input_o ) ) ) # ( !\A[3]~input_o & ( (\C[0]~input_o & (\A[2]~input_o & !\C[1]~input_o )) ) ) - .dataa(!\A[4]~input_o ), - .datab(!\Mux5~6_combout ), - .datac(!\A[2]~input_o ), - .datad(!\Mux5~7_combout ), + .dataa(!\C[0]~input_o ), + .datab(!\A[2]~input_o ), + .datac(!\C[1]~input_o ), + .datad(gnd), .datae(gnd), .dataf(!\A[3]~input_o ), .datag(gnd), @@ -2210,22 +591,46 @@ cyclonev_lcell_comb \Mux2~1 ( .shareout()); // synopsys translate_off defparam \Mux2~1 .extended_lut = "off"; -defparam \Mux2~1 .lut_mask = 64'h00470047FF47FF47; +defparam \Mux2~1 .lut_mask = 64'h101010101F1F1F1F; defparam \Mux2~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y27_N18 +// Location: MLABCELL_X19_Y4_N30 +cyclonev_lcell_comb \Mux2~2 ( +// Equation(s): +// \Mux2~2_combout = ( \B[0]~input_o & ( \A[2]~input_o ) ) # ( !\B[0]~input_o & ( \A[1]~input_o ) ) + + .dataa(gnd), + .datab(!\A[2]~input_o ), + .datac(!\A[1]~input_o ), + .datad(gnd), + .datae(gnd), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux2~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux2~2 .extended_lut = "off"; +defparam \Mux2~2 .lut_mask = 64'h0F0F0F0F33333333; +defparam \Mux2~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N6 cyclonev_lcell_comb \Mux2~3 ( // Equation(s): -// \Mux2~3_combout = ( \Mux2~1_combout & ( (!\Mux1~5_combout & (((!\Mux2~2_combout )) # (\Mux1~6_combout ))) # (\Mux1~5_combout & (((\ShiftLeft0~1_combout )))) ) ) # ( !\Mux2~1_combout & ( (!\Mux1~5_combout & (!\Mux1~6_combout & (!\Mux2~2_combout ))) -// # (\Mux1~5_combout & (((\ShiftLeft0~1_combout )))) ) ) +// \Mux2~3_combout = ( \ShiftLeft1~0_combout & ( \op[2]~input_o & ( \A[3]~input_o ) ) ) # ( !\ShiftLeft1~0_combout & ( \op[2]~input_o & ( (!\B[1]~input_o & ((\Mux2~2_combout ))) # (\B[1]~input_o & (\A[3]~input_o )) ) ) ) # ( \ShiftLeft1~0_combout & +// ( !\op[2]~input_o & ( \Mux2~1_combout ) ) ) # ( !\ShiftLeft1~0_combout & ( !\op[2]~input_o & ( \Mux2~1_combout ) ) ) - .dataa(!\Mux1~6_combout ), - .datab(!\Mux1~5_combout ), - .datac(!\Mux2~2_combout ), - .datad(!\ShiftLeft0~1_combout ), - .datae(gnd), - .dataf(!\Mux2~1_combout ), + .dataa(!\A[3]~input_o ), + .datab(!\B[1]~input_o ), + .datac(!\Mux2~1_combout ), + .datad(!\Mux2~2_combout ), + .datae(!\ShiftLeft1~0_combout ), + .dataf(!\op[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -2235,71 +640,122 @@ cyclonev_lcell_comb \Mux2~3 ( .shareout()); // synopsys translate_off defparam \Mux2~3 .extended_lut = "off"; -defparam \Mux2~3 .lut_mask = 64'h80B380B3C4F7C4F7; +defparam \Mux2~3 .lut_mask = 64'h0F0F0F0F11DD5555; defparam \Mux2~3 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X63_Y27_N57 -cyclonev_lcell_comb \Mux1~3 ( +// Location: LABCELL_X21_Y4_N48 +cyclonev_lcell_comb \ShiftLeft1~1 ( // Equation(s): -// \Mux1~3_combout = (!\op[2]~input_o & (\ShiftLeft0~0_combout & ((!\op[0]~input_o ) # (!\C[2]~input_o )))) # (\op[2]~input_o & (!\op[0]~input_o )) +// \ShiftLeft1~1_combout = ( \A[0]~input_o & ( \A[1]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & !\B[2]~input_o )) ) ) ) # ( !\A[0]~input_o & ( \A[1]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & (!\B[0]~input_o & !\B[2]~input_o ))) ) ) ) # ( +// \A[0]~input_o & ( !\A[1]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & (\B[0]~input_o & !\B[2]~input_o ))) ) ) ) - .dataa(!\op[0]~input_o ), - .datab(!\op[2]~input_o ), - .datac(!\C[2]~input_o ), - .datad(!\ShiftLeft0~0_combout ), + .dataa(!\B[3]~input_o ), + .datab(!\B[1]~input_o ), + .datac(!\B[0]~input_o ), + .datad(!\B[2]~input_o ), + .datae(!\A[0]~input_o ), + .dataf(!\A[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~1 .extended_lut = "off"; +defparam \ShiftLeft1~1 .lut_mask = 64'h0000080080008800; +defparam \ShiftLeft1~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X21_Y4_N54 +cyclonev_lcell_comb \ShiftRight2~1 ( +// Equation(s): +// \ShiftRight2~1_combout = ( \B[0]~input_o & ( \A[2]~input_o & ( (!\ShiftLeft1~0_combout & !\B[1]~input_o ) ) ) ) # ( !\B[0]~input_o & ( \A[2]~input_o & ( (!\ShiftLeft1~0_combout & ((!\B[1]~input_o & (\A[1]~input_o )) # (\B[1]~input_o & +// ((\A[3]~input_o ))))) ) ) ) # ( !\B[0]~input_o & ( !\A[2]~input_o & ( (!\ShiftLeft1~0_combout & ((!\B[1]~input_o & (\A[1]~input_o )) # (\B[1]~input_o & ((\A[3]~input_o ))))) ) ) ) + + .dataa(!\ShiftLeft1~0_combout ), + .datab(!\B[1]~input_o ), + .datac(!\A[1]~input_o ), + .datad(!\A[3]~input_o ), + .datae(!\B[0]~input_o ), + .dataf(!\A[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight2~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight2~1 .extended_lut = "off"; +defparam \ShiftRight2~1 .lut_mask = 64'h082A0000082A8888; +defparam \ShiftRight2~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X21_Y4_N6 +cyclonev_lcell_comb \ShiftLeft0~0 ( +// Equation(s): +// \ShiftLeft0~0_combout = (!\C[1]~input_o & ((!\C[0]~input_o & (\A[1]~input_o )) # (\C[0]~input_o & ((\A[0]~input_o ))))) + + .dataa(!\C[0]~input_o ), + .datab(!\C[1]~input_o ), + .datac(!\A[1]~input_o ), + .datad(!\A[0]~input_o ), .datae(gnd), .dataf(gnd), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\Mux1~3_combout ), + .combout(\ShiftLeft0~0_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \Mux1~3 .extended_lut = "off"; -defparam \Mux1~3 .lut_mask = 64'h22EA22EA22EA22EA; -defparam \Mux1~3 .shared_arith = "off"; +defparam \ShiftLeft0~0 .extended_lut = "off"; +defparam \ShiftLeft0~0 .lut_mask = 64'h084C084C084C084C; +defparam \ShiftLeft0~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X63_Y27_N54 -cyclonev_lcell_comb \Mux1~2 ( +// Location: LABCELL_X21_Y4_N15 +cyclonev_lcell_comb \ShiftRight0~1 ( // Equation(s): -// \Mux1~2_combout = ( \C[2]~input_o & ( (!\op[0]~input_o & (!\op[2]~input_o & ((\ShiftLeft0~0_combout )))) # (\op[0]~input_o & (\op[2]~input_o & (!\B[2]~input_o ))) ) ) # ( !\C[2]~input_o & ( (!\op[2]~input_o & (((\ShiftLeft0~0_combout )))) # -// (\op[2]~input_o & (\op[0]~input_o & (!\B[2]~input_o ))) ) ) +// \ShiftRight0~1_combout = ( \A[2]~input_o & ( (!\C[0]~input_o & ((!\C[1]~input_o & (\A[1]~input_o )) # (\C[1]~input_o & ((\A[3]~input_o ))))) # (\C[0]~input_o & (((!\C[1]~input_o )))) ) ) # ( !\A[2]~input_o & ( (!\C[0]~input_o & ((!\C[1]~input_o & +// (\A[1]~input_o )) # (\C[1]~input_o & ((\A[3]~input_o ))))) ) ) - .dataa(!\op[0]~input_o ), - .datab(!\op[2]~input_o ), - .datac(!\B[2]~input_o ), - .datad(!\ShiftLeft0~0_combout ), + .dataa(!\C[0]~input_o ), + .datab(!\A[1]~input_o ), + .datac(!\C[1]~input_o ), + .datad(!\A[3]~input_o ), .datae(gnd), - .dataf(!\C[2]~input_o ), + .dataf(!\A[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\Mux1~2_combout ), + .combout(\ShiftRight0~1_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \Mux1~2 .extended_lut = "off"; -defparam \Mux1~2 .lut_mask = 64'h10DC10DC10981098; -defparam \Mux1~2 .shared_arith = "off"; +defparam \ShiftRight0~1 .extended_lut = "off"; +defparam \ShiftRight0~1 .lut_mask = 64'h202A202A707A707A; +defparam \ShiftRight0~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X63_Y27_N21 +// Location: LABCELL_X21_Y4_N30 cyclonev_lcell_comb \Mux2~0 ( // Equation(s): -// \Mux2~0_combout = ( \ShiftRight0~1_combout & ( (!\Mux1~3_combout & (((\ShiftRight2~0_combout & \Mux1~2_combout )))) # (\Mux1~3_combout & (((\Mux1~2_combout )) # (\ShiftLeft1~0_combout ))) ) ) # ( !\ShiftRight0~1_combout & ( (!\Mux1~3_combout & -// (((\ShiftRight2~0_combout & \Mux1~2_combout )))) # (\Mux1~3_combout & (\ShiftLeft1~0_combout & ((!\Mux1~2_combout )))) ) ) +// \Mux2~0_combout = ( \ShiftRight0~1_combout & ( \op[2]~input_o & ( (!\op[0]~input_o & (\ShiftLeft1~1_combout )) # (\op[0]~input_o & ((\ShiftRight2~1_combout ))) ) ) ) # ( !\ShiftRight0~1_combout & ( \op[2]~input_o & ( (!\op[0]~input_o & +// (\ShiftLeft1~1_combout )) # (\op[0]~input_o & ((\ShiftRight2~1_combout ))) ) ) ) # ( \ShiftRight0~1_combout & ( !\op[2]~input_o & ( (\ShiftLeft0~0_combout ) # (\op[0]~input_o ) ) ) ) # ( !\ShiftRight0~1_combout & ( !\op[2]~input_o & ( +// (!\op[0]~input_o & \ShiftLeft0~0_combout ) ) ) ) - .dataa(!\ShiftLeft1~0_combout ), - .datab(!\ShiftRight2~0_combout ), - .datac(!\Mux1~3_combout ), - .datad(!\Mux1~2_combout ), - .datae(gnd), - .dataf(!\ShiftRight0~1_combout ), + .dataa(!\ShiftLeft1~1_combout ), + .datab(!\op[0]~input_o ), + .datac(!\ShiftRight2~1_combout ), + .datad(!\ShiftLeft0~0_combout ), + .datae(!\ShiftRight0~1_combout ), + .dataf(!\op[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -2309,344 +765,342 @@ cyclonev_lcell_comb \Mux2~0 ( .shareout()); // synopsys translate_off defparam \Mux2~0 .extended_lut = "off"; -defparam \Mux2~0 .lut_mask = 64'h05300530053F053F; +defparam \Mux2~0 .lut_mask = 64'h00CC33FF47474747; defparam \Mux2~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y27_N54 -cyclonev_lcell_comb \Mux2~4 ( +// Location: LABCELL_X21_Y4_N36 +cyclonev_lcell_comb \Mux2~5 ( // Equation(s): -// \Mux2~4_combout = ( \A[5]~input_o & ( ((!\Mux1~4_combout & (\Mux2~3_combout )) # (\Mux1~4_combout & ((\Mux2~0_combout )))) # (\Mux1~1_combout ) ) ) # ( !\A[5]~input_o & ( (!\Mux1~1_combout & ((!\Mux1~4_combout & (\Mux2~3_combout )) # -// (\Mux1~4_combout & ((\Mux2~0_combout ))))) ) ) +// \Mux2~5_combout = ( \Mux2~0_combout & ( (!\op[1]~input_o ) # (((\op[0]~input_o & \Mux2~3_combout )) # (\Mux2~4_combout )) ) ) # ( !\Mux2~0_combout & ( (\op[1]~input_o & (((\op[0]~input_o & \Mux2~3_combout )) # (\Mux2~4_combout ))) ) ) - .dataa(!\Mux1~4_combout ), - .datab(!\Mux1~1_combout ), - .datac(!\Mux2~3_combout ), - .datad(!\Mux2~0_combout ), + .dataa(!\op[1]~input_o ), + .datab(!\Mux2~4_combout ), + .datac(!\op[0]~input_o ), + .datad(!\Mux2~3_combout ), .datae(gnd), - .dataf(!\A[5]~input_o ), + .dataf(!\Mux2~0_combout ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\Mux2~4_combout ), + .combout(\Mux2~5_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \Mux2~4 .extended_lut = "off"; -defparam \Mux2~4 .lut_mask = 64'h084C084C3B7F3B7F; -defparam \Mux2~4 .shared_arith = "off"; +defparam \Mux2~5 .extended_lut = "off"; +defparam \Mux2~5 .lut_mask = 64'h11151115BBBFBBBF; +defparam \Mux2~5 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y27_N45 -cyclonev_lcell_comb \Mux1~9 ( +// Location: MLABCELL_X19_Y4_N42 +cyclonev_lcell_comb \Mux1~1 ( // Equation(s): -// \Mux1~9_combout = ( \Mux5~10_combout & ( \ShiftRight1~4_combout & ( (!\A[7]~input_o & ((!\op[2]~input_o & (!\ShiftRight0~0_combout )) # (\op[2]~input_o & ((\B[2]~input_o ))))) ) ) ) # ( !\Mux5~10_combout & ( \ShiftRight1~4_combout & ( -// (!\op[2]~input_o & (!\ShiftRight0~0_combout & ((!\A[7]~input_o )))) # (\op[2]~input_o & (((!\B[2]~input_o ) # (!\A[7]~input_o )))) ) ) ) # ( \Mux5~10_combout & ( !\ShiftRight1~4_combout & ( (!\A[7]~input_o & ((!\op[2]~input_o & -// (!\ShiftRight0~0_combout )) # (\op[2]~input_o & ((\B[2]~input_o ))))) ) ) ) # ( !\Mux5~10_combout & ( !\ShiftRight1~4_combout & ( (!\A[7]~input_o ) # ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) ) ) ) +// \Mux1~1_combout = ( \A[2]~input_o & ( \A[3]~input_o ) ) # ( !\A[2]~input_o & ( \A[3]~input_o & ( (\op[0]~input_o & ((!\op[2]~input_o & ((!\ShiftRight0~0_combout ))) # (\op[2]~input_o & (!\ShiftRight2~0_combout )))) ) ) ) # ( \A[2]~input_o & ( +// !\A[3]~input_o & ( (!\op[0]~input_o ) # ((!\op[2]~input_o & ((\ShiftRight0~0_combout ))) # (\op[2]~input_o & (\ShiftRight2~0_combout ))) ) ) ) - .dataa(!\op[2]~input_o ), - .datab(!\ShiftRight0~0_combout ), + .dataa(!\ShiftRight2~0_combout ), + .datab(!\op[0]~input_o ), + .datac(!\ShiftRight0~0_combout ), + .datad(!\op[2]~input_o ), + .datae(!\A[2]~input_o ), + .dataf(!\A[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~1 .extended_lut = "off"; +defparam \Mux1~1 .lut_mask = 64'h0000CFDD3022FFFF; +defparam \Mux1~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X21_Y4_N51 +cyclonev_lcell_comb \ShiftRight2~2 ( +// Equation(s): +// \ShiftRight2~2_combout = ( \A[3]~input_o & ( \A[2]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & !\B[2]~input_o )) ) ) ) # ( !\A[3]~input_o & ( \A[2]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & (!\B[2]~input_o & !\B[0]~input_o ))) ) ) ) # +// ( \A[3]~input_o & ( !\A[2]~input_o & ( (!\B[3]~input_o & (!\B[1]~input_o & (!\B[2]~input_o & \B[0]~input_o ))) ) ) ) + + .dataa(!\B[3]~input_o ), + .datab(!\B[1]~input_o ), .datac(!\B[2]~input_o ), - .datad(!\A[7]~input_o ), - .datae(!\Mux5~10_combout ), - .dataf(!\ShiftRight1~4_combout ), + .datad(!\B[0]~input_o ), + .datae(!\A[3]~input_o ), + .dataf(!\A[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\Mux1~9_combout ), + .combout(\ShiftRight2~2_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \Mux1~9 .extended_lut = "off"; -defparam \Mux1~9 .lut_mask = 64'hFF728D00DD508D00; -defparam \Mux1~9 .shared_arith = "off"; +defparam \ShiftRight2~2 .extended_lut = "off"; +defparam \ShiftRight2~2 .lut_mask = 64'h0000008080008080; +defparam \ShiftRight2~2 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y27_N9 -cyclonev_lcell_comb \Mux1~8 ( +// Location: LABCELL_X21_Y4_N9 +cyclonev_lcell_comb \ShiftLeft0~1 ( // Equation(s): -// \Mux1~8_combout = ( \A[5]~input_o & ( (!\Mux5~7_combout & (\A[4]~input_o )) # (\Mux5~7_combout & (((!\Mux5~6_combout ) # (\A[3]~input_o )))) ) ) # ( !\A[5]~input_o & ( (!\Mux5~7_combout & (\A[4]~input_o )) # (\Mux5~7_combout & (((\Mux5~6_combout & -// \A[3]~input_o )))) ) ) +// \ShiftLeft0~1_combout = ( \A[2]~input_o & ( (!\C[0]~input_o & ((!\C[1]~input_o ) # ((\A[0]~input_o )))) # (\C[0]~input_o & (!\C[1]~input_o & (\A[1]~input_o ))) ) ) # ( !\A[2]~input_o & ( (!\C[0]~input_o & (\C[1]~input_o & ((\A[0]~input_o )))) # +// (\C[0]~input_o & (!\C[1]~input_o & (\A[1]~input_o ))) ) ) - .dataa(!\A[4]~input_o ), - .datab(!\Mux5~6_combout ), - .datac(!\A[3]~input_o ), - .datad(!\Mux5~7_combout ), + .dataa(!\C[0]~input_o ), + .datab(!\C[1]~input_o ), + .datac(!\A[1]~input_o ), + .datad(!\A[0]~input_o ), .datae(gnd), - .dataf(!\A[5]~input_o ), + .dataf(!\A[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\Mux1~8_combout ), + .combout(\ShiftLeft0~1_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \Mux1~8 .extended_lut = "off"; -defparam \Mux1~8 .lut_mask = 64'h5503550355CF55CF; -defparam \Mux1~8 .shared_arith = "off"; +defparam \ShiftLeft0~1 .extended_lut = "off"; +defparam \ShiftLeft0~1 .lut_mask = 64'h042604268CAE8CAE; +defparam \ShiftLeft0~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y27_N21 -cyclonev_lcell_comb \Mux1~10 ( +// Location: LABCELL_X21_Y4_N18 +cyclonev_lcell_comb \ShiftLeft1~2 ( // Equation(s): -// \Mux1~10_combout = ( \Mux1~8_combout & ( (!\Mux1~5_combout & (((!\Mux1~9_combout )) # (\Mux1~6_combout ))) # (\Mux1~5_combout & (((\ShiftLeft0~2_combout )))) ) ) # ( !\Mux1~8_combout & ( (!\Mux1~5_combout & (!\Mux1~6_combout & (!\Mux1~9_combout ))) -// # (\Mux1~5_combout & (((\ShiftLeft0~2_combout )))) ) ) +// \ShiftLeft1~2_combout = ( \B[0]~input_o & ( \A[2]~input_o & ( (!\ShiftLeft1~0_combout & (!\B[1]~input_o & \A[1]~input_o )) ) ) ) # ( !\B[0]~input_o & ( \A[2]~input_o & ( (!\ShiftLeft1~0_combout & ((!\B[1]~input_o ) # (\A[0]~input_o ))) ) ) ) # ( +// \B[0]~input_o & ( !\A[2]~input_o & ( (!\ShiftLeft1~0_combout & (!\B[1]~input_o & \A[1]~input_o )) ) ) ) # ( !\B[0]~input_o & ( !\A[2]~input_o & ( (!\ShiftLeft1~0_combout & (\B[1]~input_o & \A[0]~input_o )) ) ) ) - .dataa(!\Mux1~6_combout ), - .datab(!\Mux1~5_combout ), - .datac(!\Mux1~9_combout ), - .datad(!\ShiftLeft0~2_combout ), - .datae(gnd), - .dataf(!\Mux1~8_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux1~10_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux1~10 .extended_lut = "off"; -defparam \Mux1~10 .lut_mask = 64'h80B380B3C4F7C4F7; -defparam \Mux1~10 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X63_Y27_N51 -cyclonev_lcell_comb \Mux1~7 ( -// Equation(s): -// \Mux1~7_combout = ( \ShiftLeft1~1_combout & ( (!\Mux1~3_combout & (((\ShiftRight2~1_combout & \Mux1~2_combout )))) # (\Mux1~3_combout & (((!\Mux1~2_combout )) # (\ShiftRight0~2_combout ))) ) ) # ( !\ShiftLeft1~1_combout & ( (\Mux1~2_combout & -// ((!\Mux1~3_combout & ((\ShiftRight2~1_combout ))) # (\Mux1~3_combout & (\ShiftRight0~2_combout )))) ) ) - - .dataa(!\ShiftRight0~2_combout ), - .datab(!\ShiftRight2~1_combout ), - .datac(!\Mux1~3_combout ), - .datad(!\Mux1~2_combout ), - .datae(gnd), - .dataf(!\ShiftLeft1~1_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux1~7_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux1~7 .extended_lut = "off"; -defparam \Mux1~7 .lut_mask = 64'h003500350F350F35; -defparam \Mux1~7 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y27_N57 -cyclonev_lcell_comb \Mux1~11 ( -// Equation(s): -// \Mux1~11_combout = ( \Mux1~7_combout & ( (!\Mux1~1_combout & (((\Mux1~10_combout )) # (\Mux1~4_combout ))) # (\Mux1~1_combout & (((\A[6]~input_o )))) ) ) # ( !\Mux1~7_combout & ( (!\Mux1~1_combout & (!\Mux1~4_combout & ((\Mux1~10_combout )))) # -// (\Mux1~1_combout & (((\A[6]~input_o )))) ) ) - - .dataa(!\Mux1~4_combout ), - .datab(!\Mux1~1_combout ), - .datac(!\A[6]~input_o ), - .datad(!\Mux1~10_combout ), - .datae(gnd), - .dataf(!\Mux1~7_combout ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux1~11_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux1~11 .extended_lut = "off"; -defparam \Mux1~11 .lut_mask = 64'h038B038B47CF47CF; -defparam \Mux1~11 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y28_N6 -cyclonev_lcell_comb \ShiftRight2~4 ( -// Equation(s): -// \ShiftRight2~4_combout = ( !\B[1]~input_o & ( (!\B[0]~input_o & (!\B[2]~input_o & \A[7]~input_o )) ) ) - - .dataa(gnd), - .datab(!\B[0]~input_o ), - .datac(!\B[2]~input_o ), - .datad(!\A[7]~input_o ), - .datae(gnd), - .dataf(!\B[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight2~4_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight2~4 .extended_lut = "off"; -defparam \ShiftRight2~4 .lut_mask = 64'h00C000C000000000; -defparam \ShiftRight2~4 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N57 -cyclonev_lcell_comb \ShiftLeft1~6 ( -// Equation(s): -// \ShiftLeft1~6_combout = ( \B[0]~input_o & ( \B[1]~input_o & ( \A[4]~input_o ) ) ) # ( !\B[0]~input_o & ( \B[1]~input_o & ( \A[5]~input_o ) ) ) # ( \B[0]~input_o & ( !\B[1]~input_o & ( \A[6]~input_o ) ) ) # ( !\B[0]~input_o & ( !\B[1]~input_o & -// ( \A[7]~input_o ) ) ) - - .dataa(!\A[5]~input_o ), - .datab(!\A[6]~input_o ), - .datac(!\A[4]~input_o ), - .datad(!\A[7]~input_o ), + .dataa(!\ShiftLeft1~0_combout ), + .datab(!\B[1]~input_o ), + .datac(!\A[1]~input_o ), + .datad(!\A[0]~input_o ), .datae(!\B[0]~input_o ), - .dataf(!\B[1]~input_o ), + .dataf(!\A[2]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\ShiftLeft1~6_combout ), + .combout(\ShiftLeft1~2_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \ShiftLeft1~6 .extended_lut = "off"; -defparam \ShiftLeft1~6 .lut_mask = 64'h00FF333355550F0F; -defparam \ShiftLeft1~6 .shared_arith = "off"; +defparam \ShiftLeft1~2 .extended_lut = "off"; +defparam \ShiftLeft1~2 .lut_mask = 64'h0022080888AA0808; +defparam \ShiftLeft1~2 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y28_N18 -cyclonev_lcell_comb \ShiftLeft1~7 ( +// Location: LABCELL_X21_Y4_N45 +cyclonev_lcell_comb \ShiftRight0~2 ( // Equation(s): -// \ShiftLeft1~7_combout = ( \B[2]~input_o & ( \ShiftLeft1~2_combout ) ) # ( !\B[2]~input_o & ( \ShiftLeft1~6_combout ) ) +// \ShiftRight0~2_combout = ( \A[2]~input_o & ( (!\C[1]~input_o & ((!\C[0]~input_o ) # (\A[3]~input_o ))) ) ) # ( !\A[2]~input_o & ( (\A[3]~input_o & (!\C[1]~input_o & \C[0]~input_o )) ) ) .dataa(gnd), - .datab(!\ShiftLeft1~6_combout ), + .datab(!\A[3]~input_o ), + .datac(!\C[1]~input_o ), + .datad(!\C[0]~input_o ), + .datae(gnd), + .dataf(!\A[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight0~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight0~2 .extended_lut = "off"; +defparam \ShiftRight0~2 .lut_mask = 64'h00300030F030F030; +defparam \ShiftRight0~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X21_Y4_N24 +cyclonev_lcell_comb \Mux1~0 ( +// Equation(s): +// \Mux1~0_combout = ( \ShiftRight0~2_combout & ( \op[2]~input_o & ( (!\op[0]~input_o & ((\ShiftLeft1~2_combout ))) # (\op[0]~input_o & (\ShiftRight2~2_combout )) ) ) ) # ( !\ShiftRight0~2_combout & ( \op[2]~input_o & ( (!\op[0]~input_o & +// ((\ShiftLeft1~2_combout ))) # (\op[0]~input_o & (\ShiftRight2~2_combout )) ) ) ) # ( \ShiftRight0~2_combout & ( !\op[2]~input_o & ( (\op[0]~input_o ) # (\ShiftLeft0~1_combout ) ) ) ) # ( !\ShiftRight0~2_combout & ( !\op[2]~input_o & ( +// (\ShiftLeft0~1_combout & !\op[0]~input_o ) ) ) ) + + .dataa(!\ShiftRight2~2_combout ), + .datab(!\ShiftLeft0~1_combout ), .datac(!\ShiftLeft1~2_combout ), + .datad(!\op[0]~input_o ), + .datae(!\ShiftRight0~2_combout ), + .dataf(!\op[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~0 .extended_lut = "off"; +defparam \Mux1~0 .lut_mask = 64'h330033FF0F550F55; +defparam \Mux1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X21_Y4_N39 +cyclonev_lcell_comb \Mux1~2 ( +// Equation(s): +// \Mux1~2_combout = ( \Mux1~0_combout & ( (!\op[1]~input_o ) # (\Mux1~1_combout ) ) ) # ( !\Mux1~0_combout & ( (\op[1]~input_o & \Mux1~1_combout ) ) ) + + .dataa(!\op[1]~input_o ), + .datab(gnd), + .datac(!\Mux1~1_combout ), .datad(gnd), .datae(gnd), - .dataf(!\B[2]~input_o ), + .dataf(!\Mux1~0_combout ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\ShiftLeft1~7_combout ), + .combout(\Mux1~2_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \ShiftLeft1~7 .extended_lut = "off"; -defparam \ShiftLeft1~7 .lut_mask = 64'h333333330F0F0F0F; -defparam \ShiftLeft1~7 .shared_arith = "off"; +defparam \Mux1~2 .extended_lut = "off"; +defparam \Mux1~2 .lut_mask = 64'h05050505AFAFAFAF; +defparam \Mux1~2 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y28_N15 -cyclonev_lcell_comb \ShiftRight0~4 ( +// Location: MLABCELL_X19_Y4_N27 +cyclonev_lcell_comb \ShiftRight0~3 ( // Equation(s): -// \ShiftRight0~4_combout = (\A[7]~input_o & (\ShiftRight0~0_combout & \ShiftRight1~2_combout )) +// \ShiftRight0~3_combout = ( \A[3]~input_o & ( (!\C[0]~input_o & !\C[1]~input_o ) ) ) - .dataa(gnd), - .datab(!\A[7]~input_o ), - .datac(!\ShiftRight0~0_combout ), - .datad(!\ShiftRight1~2_combout ), - .datae(gnd), - .dataf(gnd), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftRight0~4_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftRight0~4 .extended_lut = "off"; -defparam \ShiftRight0~4 .lut_mask = 64'h0003000300030003; -defparam \ShiftRight0~4 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X64_Y28_N54 -cyclonev_lcell_comb \ShiftLeft0~6 ( -// Equation(s): -// \ShiftLeft0~6_combout = ( \C[0]~input_o & ( \C[1]~input_o & ( \A[4]~input_o ) ) ) # ( !\C[0]~input_o & ( \C[1]~input_o & ( \A[5]~input_o ) ) ) # ( \C[0]~input_o & ( !\C[1]~input_o & ( \A[6]~input_o ) ) ) # ( !\C[0]~input_o & ( !\C[1]~input_o & -// ( \A[7]~input_o ) ) ) - - .dataa(!\A[5]~input_o ), - .datab(!\A[6]~input_o ), - .datac(!\A[7]~input_o ), - .datad(!\A[4]~input_o ), - .datae(!\C[0]~input_o ), - .dataf(!\C[1]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\ShiftLeft0~6_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \ShiftLeft0~6 .extended_lut = "off"; -defparam \ShiftLeft0~6 .lut_mask = 64'h0F0F3333555500FF; -defparam \ShiftLeft0~6 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X65_Y28_N9 -cyclonev_lcell_comb \ShiftLeft0~7 ( -// Equation(s): -// \ShiftLeft0~7_combout = ( \ShiftLeft0~6_combout & ( (\ShiftLeft0~0_combout & ((!\C[2]~input_o ) # (\ShiftLeft0~3_combout ))) ) ) # ( !\ShiftLeft0~6_combout & ( (\ShiftLeft0~0_combout & (\ShiftLeft0~3_combout & \C[2]~input_o )) ) ) - - .dataa(!\ShiftLeft0~0_combout ), + .dataa(!\C[0]~input_o ), .datab(gnd), - .datac(!\ShiftLeft0~3_combout ), - .datad(!\C[2]~input_o ), + .datac(!\C[1]~input_o ), + .datad(gnd), .datae(gnd), - .dataf(!\ShiftLeft0~6_combout ), + .dataf(!\A[3]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\ShiftLeft0~7_combout ), + .combout(\ShiftRight0~3_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \ShiftLeft0~7 .extended_lut = "off"; -defparam \ShiftLeft0~7 .lut_mask = 64'h0005000555055505; -defparam \ShiftLeft0~7 .shared_arith = "off"; +defparam \ShiftRight0~3 .extended_lut = "off"; +defparam \ShiftRight0~3 .lut_mask = 64'h00000000A0A0A0A0; +defparam \ShiftRight0~3 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y28_N24 -cyclonev_lcell_comb \Mux0~0 ( +// Location: LABCELL_X21_Y4_N42 +cyclonev_lcell_comb \ShiftRight2~3 ( // Equation(s): -// \Mux0~0_combout = ( \op[2]~input_o & ( \ShiftLeft0~7_combout & ( (!\op[0]~input_o & ((\ShiftLeft1~7_combout ))) # (\op[0]~input_o & (\ShiftRight2~4_combout )) ) ) ) # ( !\op[2]~input_o & ( \ShiftLeft0~7_combout & ( (!\op[0]~input_o ) # -// (\ShiftRight0~4_combout ) ) ) ) # ( \op[2]~input_o & ( !\ShiftLeft0~7_combout & ( (!\op[0]~input_o & ((\ShiftLeft1~7_combout ))) # (\op[0]~input_o & (\ShiftRight2~4_combout )) ) ) ) # ( !\op[2]~input_o & ( !\ShiftLeft0~7_combout & ( (\op[0]~input_o -// & \ShiftRight0~4_combout ) ) ) ) +// \ShiftRight2~3_combout = ( !\B[3]~input_o & ( (!\B[2]~input_o & (\A[3]~input_o & (!\B[0]~input_o & !\B[1]~input_o ))) ) ) - .dataa(!\op[0]~input_o ), - .datab(!\ShiftRight2~4_combout ), - .datac(!\ShiftLeft1~7_combout ), - .datad(!\ShiftRight0~4_combout ), - .datae(!\op[2]~input_o ), - .dataf(!\ShiftLeft0~7_combout ), + .dataa(!\B[2]~input_o ), + .datab(!\A[3]~input_o ), + .datac(!\B[0]~input_o ), + .datad(!\B[1]~input_o ), + .datae(gnd), + .dataf(!\B[3]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), - .combout(\Mux0~0_combout ), + .combout(\ShiftRight2~3_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off -defparam \Mux0~0 .extended_lut = "off"; -defparam \Mux0~0 .lut_mask = 64'h00551B1BAAFF1B1B; -defparam \Mux0~0 .shared_arith = "off"; +defparam \ShiftRight2~3 .extended_lut = "off"; +defparam \ShiftRight2~3 .lut_mask = 64'h2000200000000000; +defparam \ShiftRight2~3 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X65_Y28_N12 +// Location: MLABCELL_X19_Y4_N51 +cyclonev_lcell_comb \ShiftLeft1~3 ( +// Equation(s): +// \ShiftLeft1~3_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[2]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o & +// ( \A[3]~input_o ) ) ) + + .dataa(!\A[0]~input_o ), + .datab(!\A[2]~input_o ), + .datac(!\A[1]~input_o ), + .datad(!\A[3]~input_o ), + .datae(!\B[1]~input_o ), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~3 .extended_lut = "off"; +defparam \ShiftLeft1~3 .lut_mask = 64'h00FF0F0F33335555; +defparam \ShiftLeft1~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N48 +cyclonev_lcell_comb \ShiftLeft0~2 ( +// Equation(s): +// \ShiftLeft0~2_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[2]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o & +// ( \A[3]~input_o ) ) ) + + .dataa(!\A[0]~input_o ), + .datab(!\A[2]~input_o ), + .datac(!\A[3]~input_o ), + .datad(!\A[1]~input_o ), + .datae(!\C[1]~input_o ), + .dataf(!\C[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft0~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft0~2 .extended_lut = "off"; +defparam \ShiftLeft0~2 .lut_mask = 64'h0F0F00FF33335555; +defparam \ShiftLeft0~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N0 +cyclonev_lcell_comb \Mux0~2 ( +// Equation(s): +// \Mux0~2_combout = ( !\op[2]~input_o & ( (!\op[0]~input_o & (((\ShiftLeft0~2_combout )))) # (\op[0]~input_o & (\ShiftRight0~3_combout )) ) ) # ( \op[2]~input_o & ( ((!\op[0]~input_o & (!\ShiftLeft1~0_combout & ((\ShiftLeft1~3_combout )))) # +// (\op[0]~input_o & (((\ShiftRight2~3_combout ))))) ) ) + + .dataa(!\ShiftRight0~3_combout ), + .datab(!\op[0]~input_o ), + .datac(!\ShiftLeft1~0_combout ), + .datad(!\ShiftRight2~3_combout ), + .datae(!\op[2]~input_o ), + .dataf(!\ShiftLeft1~3_combout ), + .datag(!\ShiftLeft0~2_combout ), + .cin(gnd), + .sharein(gnd), + .combout(\Mux0~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux0~2 .extended_lut = "on"; +defparam \Mux0~2 .lut_mask = 64'h1D1D00331D1DC0F3; +defparam \Mux0~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X19_Y4_N24 cyclonev_lcell_comb \Mux0~1 ( // Equation(s): -// \Mux0~1_combout = ( \op[1]~input_o & ( \A[7]~input_o ) ) # ( !\op[1]~input_o & ( \Mux0~0_combout ) ) +// \Mux0~1_combout = ( \A[3]~input_o & ( (\op[1]~input_o ) # (\Mux0~2_combout ) ) ) # ( !\A[3]~input_o & ( (\Mux0~2_combout & !\op[1]~input_o ) ) ) .dataa(gnd), - .datab(!\A[7]~input_o ), - .datac(!\Mux0~0_combout ), - .datad(gnd), + .datab(gnd), + .datac(!\Mux0~2_combout ), + .datad(!\op[1]~input_o ), .datae(gnd), - .dataf(!\op[1]~input_o ), + .dataf(!\A[3]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -2656,11 +1110,11 @@ cyclonev_lcell_comb \Mux0~1 ( .shareout()); // synopsys translate_off defparam \Mux0~1 .extended_lut = "off"; -defparam \Mux0~1 .lut_mask = 64'h0F0F0F0F33333333; +defparam \Mux0~1 .lut_mask = 64'h0F000F000FFF0FFF; defparam \Mux0~1 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X58_Y37_N0 +// Location: LABCELL_X41_Y51_N0 cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( // Equation(s): diff --git a/modules/shifter.sv b/modules/shifter.sv index 7b84b49..a4070a9 100644 --- a/modules/shifter.sv +++ b/modules/shifter.sv @@ -1,8 +1,8 @@ `ifndef SHIFTER_H_SV `define SHIFTER_H_SV -module shifter #(width=8)(input logic [2:0] op, - input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B, - output logic[width-1:0] OUT_1); +module shifter #(width=2)(input logic [2:0] op, + input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C, + output logic[2**width-1:0] OUT_1); always_comb begin case (op) diff --git a/modules/shifter.sv.bak b/modules/shifter.sv.bak new file mode 100644 index 0000000..7b84b49 --- /dev/null +++ b/modules/shifter.sv.bak @@ -0,0 +1,19 @@ +`ifndef SHIFTER_H_SV +`define SHIFTER_H_SV +module shifter #(width=8)(input logic [2:0] op, + input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B, + output logic[width-1:0] OUT_1); + + always_comb begin + case (op) + 3'b000: OUT_1 = A << C; + 3'b001: OUT_1 = A >> C; + 3'b011: OUT_1 = $signed(A) >>> C; + 3'b100: OUT_1 = A << B; + 3'b101: OUT_1 = A >> B; + 3'b111: OUT_1 = $signed(A) >>> B; + default:OUT_1 = A; + endcase + end +endmodule +`endif \ No newline at end of file