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Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

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TroubleElectrical committed 2026-09-15 19:43:28 +10:00
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commit 9583abd307
75 files changed
+1545 -3442
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Quartus/A1_Q5/output_files/shifter.map.rpt
+54 -67
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for shifter
Tue Sep 15 10:06:09 2026
Tue Sep 15 19:38:48 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -14,11 +14,10 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Multiplexer Restructuring Statistics (Restructuring Performed)
10. Parameter Settings for User Entity Instance: Top-level Entity: |shifter
11. Post-Synthesis Netlist Statistics for Top Partition
12. Elapsed Time Per Partition
13. Analysis & Synthesis Messages
9. Parameter Settings for User Entity Instance: Top-level Entity: |shifter
10. Post-Synthesis Netlist Statistics for Top Partition
11. Elapsed Time Per Partition
12. Analysis & Synthesis Messages
@@ -45,14 +44,14 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:06:09 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:38:48 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; shifter ;
; Top-level Entity Name ; shifter ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 0 ;
; Total pins ; 30 ;
; Total pins ; 17 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; Total DSP Blocks ; 0 ;
@@ -177,31 +176,31 @@ on the Quartus Prime software download page.
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+
+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------------+
; Resource ; Usage ;
+---------------------------------------------+-------------+
; Estimate of Logic utilization (ALMs needed) ; 56 ;
; ; ;
; Combinational ALUT usage for logic ; 85 ;
; -- 7 input functions ; 3 ;
; -- 6 input functions ; 23 ;
; -- 5 input functions ; 41 ;
; -- 4 input functions ; 9 ;
; -- <=3 input functions ; 9 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 30 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; op[2]~input ;
; Maximum fan-out ; 29 ;
; Total fan-out ; 462 ;
; Average fan-out ; 3.19 ;
+---------------------------------------------+-------------+
+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------+
; Resource ; Usage ;
+---------------------------------------------+------------+
; Estimate of Logic utilization (ALMs needed) ; 23 ;
; ; ;
; Combinational ALUT usage for logic ; 32 ;
; -- 7 input functions ; 1 ;
; -- 6 input functions ; 13 ;
; -- 5 input functions ; 5 ;
; -- 4 input functions ; 6 ;
; -- <=3 input functions ; 7 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 17 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; A[3]~input ;
; Maximum fan-out ; 15 ;
; Total fan-out ; 173 ;
; Average fan-out ; 2.62 ;
+---------------------------------------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -209,7 +208,7 @@ on the Quartus Prime software download page.
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; |shifter ; 85 (85) ; 0 (0) ; 0 ; 0 ; 30 ; 0 ; |shifter ; shifter ; work ;
; |shifter ; 32 (32) ; 0 (0) ; 0 ; 0 ; 17 ; 0 ; |shifter ; shifter ; work ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -229,24 +228,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |shifter|ShiftLeft0 ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |shifter|ShiftRight2 ;
; 23:1 ; 2 bits ; 30 LEs ; 20 LEs ; 10 LEs ; No ; |shifter|Mux1 ;
; 21:1 ; 2 bits ; 28 LEs ; 20 LEs ; 8 LEs ; No ; |shifter|Mux5 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |shifter ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------+
; width ; 8 ; Signed Integer ;
; width ; 2 ; Signed Integer ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
@@ -256,19 +243,19 @@ Note: In order to hide this table in the UI and the text report file, please set
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_lcell_comb ; 85 ;
; extend ; 3 ;
; 7 data inputs ; 3 ;
; normal ; 82 ;
; arriav_lcell_comb ; 32 ;
; extend ; 1 ;
; 7 data inputs ; 1 ;
; normal ; 31 ;
; 2 data inputs ; 3 ;
; 3 data inputs ; 6 ;
; 4 data inputs ; 9 ;
; 5 data inputs ; 41 ;
; 6 data inputs ; 23 ;
; boundary_port ; 30 ;
; 3 data inputs ; 4 ;
; 4 data inputs ; 6 ;
; 5 data inputs ; 5 ;
; 6 data inputs ; 13 ;
; boundary_port ; 17 ;
; ; ;
; Max LUT depth ; 4.00 ;
; Average LUT depth ; 3.75 ;
; Average LUT depth ; 3.13 ;
+-----------------------+-----------------------------+
@@ -277,7 +264,7 @@ Note: In order to hide this table in the UI and the text report file, please set
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:01 ;
; Top ; 00:00:00 ;
+----------------+--------------+
@@ -287,7 +274,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 10:05:57 2026
Info: Processing started: Tue Sep 15 19:38:37 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
@@ -297,14 +284,14 @@ Info (12127): Elaborating entity "shifter" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 115 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 22 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 85 logic cells
Info (21057): Implemented 49 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 13 input pins
Info (21059): Implemented 4 output pins
Info (21061): Implemented 32 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 430 megabytes
Info: Processing ended: Tue Sep 15 10:06:09 2026
Info: Elapsed time: 00:00:12
Info: Total CPU time (on all processors): 00:00:25
Info: Peak virtual memory: 433 megabytes
Info: Processing ended: Tue Sep 15 19:38:48 2026
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:24