TroubleElectrical/FPGA_Uni
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Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

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TroubleElectrical committed 2026-09-15 19:43:28 +10:00
1 parent 9d0c7011ce
commit 9583abd307
75 files changed
+1545 -3442
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Quartus/A1_Q5/output_files/shifter.flow.rpt
+12 -12
View File
@@ -1,5 +1,5 @@
Flow report for shifter
Tue Sep 15 10:06:57 2026
Tue Sep 15 19:39:43 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,16 +41,16 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Sep 15 10:06:57 2026 ;
; Flow Status ; Successful - Tue Sep 15 19:39:43 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; shifter ;
; Top-level Entity Name ; shifter ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 48 / 29,080 ( < 1 % ) ;
; Logic utilization (in ALMs) ; 21 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 30 / 364 ( 8 % ) ;
; Total pins ; 17 / 364 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/15/2026 10:05:58 ;
; Start date & time ; 09/15/2026 19:38:37 ;
; Main task ; Compilation ;
; Revision Name ; shifter ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 253029099468756.178943075805931 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 268883478169649.178946511707335 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 413 MB ; 00:00:25 ;
; Fitter ; 00:00:31 ; 1.0 ; 1347 MB ; 00:00:48 ;
; Assembler ; 00:00:05 ; 1.0 ; 518 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 750 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
; Total ; 00:00:55 ; -- ; -- ; 00:01:24 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ;
; Fitter ; 00:00:36 ; 1.0 ; 1379 MB ; 00:00:50 ;
; Assembler ; 00:00:06 ; 1.0 ; 507 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 777 MB ; 00:00:06 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ;
; Total ; 00:01:00 ; -- ; -- ; 00:01:27 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+