Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

Quartus/A1_Q5/output_files/shifter.fit.summary

@@ -1,13 +1,13 @@
-Fitter Status : Successful - Tue Sep 15 10:06:41 2026
+Fitter Status : Successful - Tue Sep 15 19:39:25 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : shifter
 Top-level Entity Name : shifter
 Family : Cyclone V
 Device : 5CGXFC5C6F27C7
 Timing Models : Final
-Logic utilization (in ALMs) : 48 / 29,080 ( < 1 % )
+Logic utilization (in ALMs) : 21 / 29,080 ( < 1 % )
 Total registers : 0
-Total pins : 30 / 364 ( 8 % )
+Total pins : 17 / 364 ( 5 % )
 Total virtual pins : 0
 Total block memory bits : 0 / 4,567,040 ( 0 % )
 Total RAM Blocks : 0 / 446 ( 0 % )