TroubleElectrical/FPGA_Uni
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Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

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TroubleElectrical committed 2026-09-15 19:43:28 +10:00
1 parent 9d0c7011ce
commit 9583abd307
75 files changed
+1545 -3442
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Quartus/A1_Q5/output_files/shifter.fit.smsg
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Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks