Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM.

Added a QUARTUS_SYNTH around the display logic at the end of the module.
Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.

modules/control_unit.sv

@@ -23,13 +23,13 @@ module control_unit (
     instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
 
     always_comb begin
-        M2R = TYPE_M & op[3];
-        M2W = TYPE_M & ~op[3];
+        M2R = TYPE_M & ~((op & 6'b001000) >> 3);
+        M2W = TYPE_M & ((op & 6'b001000) >> 3);
         B = TYPE_B1 | TYPE_B2 | TYPE_J;
-        ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
-        ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
-        RDST = TYPE_I;  // Imm ops store back into rt
-        RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
+        ALU_FN = (func & {(4){TYPE_R}}) | ( {2'b00, (op & 6'b000011)} & {(4){TYPE_I}}) | (4'b0010 & {4{TYPE_B1 | TYPE_B2}});
+        ALU_SRC = TYPE_I | TYPE_M;
+        RDST = TYPE_R;  // Imm ops store back into rt
+        RW = TYPE_R | TYPE_I | M2R;
     end
 
 endmodule