From 92a0cb17da7f837175c689f4bd2c5ca19e7bdb7c Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Fri, 16 Oct 2026 11:38:35 +1100
Subject: [PATCH] Updated assignment 2 to reflect prior changes. Fixed
 instruction ordering for register file module (again). Fixed typo that
 limited the space the ALU could write its flags out to. Swapped ordering to
 be correct when determining if we are storing the result from ALU or MEM.
 Added a QUARTUS_SYNTH around the display logic at the end of the module.
 Partially fixed control_unit module, still seems to need some changes as
 branching doesn't appear to work at all.

---
 modules/assignment2.sv  | 25 +++++++++++--------------
 modules/control_unit.sv | 12 ++++++------
 2 files changed, 17 insertions(+), 20 deletions(-)

diff --git a/modules/assignment2.sv b/modules/assignment2.sv
index 36426c5..272b867 100644
--- a/modules/assignment2.sv
+++ b/modules/assignment2.sv
@@ -30,8 +30,8 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic[15:0] PC_Reg_Display;
 	
 	// Program / Instruction Counter Intermediates
-	logic [romsz-1:0] pc_addr;
-	logic [romsz-1:0] pc_addr_write;
+	logic [2**width-1:0] pc_addr;
+	logic [2**width-1:0] pc_addr_write;
 	logic [0:0] pc_we;
 	logic [2**width-1:0] instruction;
 	
@@ -54,10 +54,10 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	
 	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
 	
-	rom #(romsz, 2**width) ROM (pc_addr, instruction);
+	rom #(romsz, width) ROM (pc_addr, instruction);
 
 	logic [2**width-1:0] rd_mem;
-	ram #(ramsz, 2**width) RAM (clk, rd_alu, M2W, rt, rd_mem);
+	ram #(ramsz, width) RAM (clk, rd_alu, M2W, rt, rd_mem);
 	
 	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
 		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
@@ -66,30 +66,27 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 
 	register_file #(width, 5) REGS (
 		clk, rd_we, 
-		instruction[20:16], rd,
-		(RDST) ? instruction[15:11] : instruction[20:16], rt,
-		instruction[25:21], rs, 
+		(RDST) ? instruction[15:11] : instruction[20:16], rd,
+		instruction[25:21], rs,
+		instruction[20:16], rt, 
 		regs_out
    );
     // Always use sign-extension
     logic [2**width-1:0] rt_imm;
     sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
-    // TODO:
-    //  - ALU srcB
-    //  - PCBranch (rel jump of 4-byte words)
 
 	logic [2**width-1:0] rd_alu;
 	logic [2**width-1:0] rt_alu;
-	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
+	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags);
     assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
 
 	assign pc_we = B & flags[2];
 	assign pc_addr_write = (rt_imm << 2) + pc_addr;
 	assign rd_we = RW;
-	assign rd = (M2R) ? rd_alu : rd_mem;
-
+	assign rd = (M2R) ? rd_mem : rd_alu;
 
 
+`ifdef QUARTUS_SYNTH
 	// Temporary Test output
 	// assign PC_Reg_Display = 16'hC342;
 
@@ -102,6 +99,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 		.segments2(out_seg_2),
 		.segments3(out_seg_3)
 	);
-
+`endif
 endmodule
 `endif
diff --git a/modules/control_unit.sv b/modules/control_unit.sv
index 85a673c..58d7cdd 100644
--- a/modules/control_unit.sv
+++ b/modules/control_unit.sv
@@ -23,13 +23,13 @@ module control_unit (
     instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
 
     always_comb begin
-        M2R = TYPE_M & op[3];
-        M2W = TYPE_M & ~op[3];
+        M2R = TYPE_M & ~((op & 6'b001000) >> 3);
+        M2W = TYPE_M & ((op & 6'b001000) >> 3);
         B = TYPE_B1 | TYPE_B2 | TYPE_J;
-        ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
-        ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
-        RDST = TYPE_I;  // Imm ops store back into rt
-        RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
+        ALU_FN = (func & {(4){TYPE_R}}) | ( {2'b00, (op & 6'b000011)} & {(4){TYPE_I}}) | (4'b0010 & {4{TYPE_B1 | TYPE_B2}});
+        ALU_SRC = TYPE_I | TYPE_M;
+        RDST = TYPE_R;  // Imm ops store back into rt
+        RW = TYPE_R | TYPE_I | M2R;
     end
 
 endmodule