Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
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21 files changed
+388
-1322
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@@ -41,7 +41,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
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Top level modules:
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control_unit
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module rom
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-- Compiling module ram
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@@ -52,9 +52,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
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-- Compiling module asu
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-- Compiling module lu
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-- Compiling module alu
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** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(1)
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** while parsing file included at assignment2.sv(9)
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** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
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-- Compiling module shifter
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-- Compiling module sign_extender
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-- Compiling module seven_seg
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@@ -64,6 +61,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
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Top level modules:
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shifter
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seven_seg_4digit
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mips_tb
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
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@@ -88,7 +86,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
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Top level modules:
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shifter_tb
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module rom
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-- Compiling module ram
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@@ -99,8 +97,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
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-- Compiling module asu
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-- Compiling module lu
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-- Compiling module alu
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** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv(9)
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** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
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-- Compiling module shifter
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-- Compiling module sign_extender
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-- Compiling module seven_seg
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@@ -109,6 +105,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
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Top level modules:
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shifter
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seven_seg_4digit
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assignment2
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
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@@ -142,13 +139,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
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Top level modules:
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sign_extender
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module asu
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-- Compiling module lu
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-- Compiling module alu
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** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv(1)
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** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
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-- Compiling module alu_tb
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Top level modules:
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@@ -161,12 +156,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
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Top level modules:
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instruction_counter
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
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} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module asu
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-- Compiling module lu
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-- Compiling module alu
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** Warning: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
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Top level modules:
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alu
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+23
-23
@@ -220,7 +220,7 @@ Resolution = ps
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UserTimeUnit = default
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; Default run length
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RunLength = 1 ns
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RunLength = 1 us
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; Maximum iterations that can be run without advancing simulation time
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IterationLimit = 5000
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@@ -412,49 +412,49 @@ Project_DefaultLib = work
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Project_SortMethod = unused
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Project_Files_Count = 22
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Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv
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Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
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Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792107144 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792114203 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_2 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv
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Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_3 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv
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Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_4 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
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Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792039197 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_5 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv
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Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792040117 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_6 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
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Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792104861 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_7 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
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Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228118 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228118 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_8 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
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Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_9 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
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Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789513270 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_10 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
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Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792106709 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_11 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
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Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788418794 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788418794 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_12 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
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Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789513270 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_13 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
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Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_14 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
|
||||
Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792038654 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_15 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
|
||||
Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
|
||||
Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1791854498 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
|
||||
Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792036226 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792113810 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_18 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
|
||||
Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792106811 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1792112374 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
|
||||
Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1791866874 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1791866874 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_20 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
|
||||
Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
|
||||
Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792035553 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_Sim_Count = 0
|
||||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
`include "rom.sv"
|
||||
|
||||
module ByteIM #(parameter m=5,n=2) (
|
||||
input logic [m-1:0] Ad,
|
||||
output logic [(2**n)*8-1:0] Dout );
|
||||
|
||||
// 2**n byte wide words
|
||||
// m bit wide byte address
|
||||
// 2**m bytes of memory
|
||||
// 2**(m-n) memory words
|
||||
// 2**(n+3) bit wide words
|
||||
// Reads the whole word that contains the addressed byte
|
||||
ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
|
||||
endmodule
|
||||
+17
-12
@@ -6,6 +6,7 @@
|
||||
|
||||
// flags[0:0] = Cout
|
||||
// flags[1:1] = Overflow
|
||||
// flags[2:2] = Zero
|
||||
module alu #(parameter width=2)(input logic [3:0] op,
|
||||
input logic [2**width-1:0] A, input logic [2**width-1:0] B,
|
||||
output logic [2**width-1:0] OUT_1, output logic[2:0] flags
|
||||
@@ -15,26 +16,30 @@ module alu #(parameter width=2)(input logic [3:0] op,
|
||||
logic [2**width-1:0] asu_out;
|
||||
logic [2:0] asu_flags;
|
||||
|
||||
asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
|
||||
assign asu_op = op[1];
|
||||
logic [0:0] asu_cout_flag;
|
||||
asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_cout_flag);
|
||||
|
||||
logic [2**width-1:0] lu_out;
|
||||
lu #(width) logic_unit(op[1:0], A, B, lu_out);
|
||||
|
||||
assign asu_flags[1] = asu_cout_flag ^ asu_flags[0];
|
||||
always_comb begin
|
||||
case (op)
|
||||
4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
|
||||
4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
|
||||
4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
|
||||
4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
|
||||
4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
|
||||
4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
|
||||
4'b0110: begin OUT_1 = lu_out; flags = asu_flags; end
|
||||
4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
|
||||
4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
|
||||
4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
|
||||
default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
|
||||
4'b0000: begin OUT_1 = asu_out; end
|
||||
4'b0001: begin OUT_1 = asu_out; end
|
||||
4'b0010: begin OUT_1 = asu_out; end
|
||||
4'b0011: begin OUT_1 = asu_out; end
|
||||
4'b0100: begin OUT_1 = lu_out; end
|
||||
4'b0101: begin OUT_1 = lu_out; end
|
||||
4'b0110: begin OUT_1 = lu_out; end
|
||||
4'b0111: begin OUT_1 = lu_out; end
|
||||
4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; end
|
||||
4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; end
|
||||
default: begin OUT_1 = {(2**width){1'b0}}; end
|
||||
endcase
|
||||
asu_flags[2] = OUT_1 == 0;
|
||||
flags = asu_flags;
|
||||
end
|
||||
endmodule
|
||||
`endif
|
||||
+16
-16
@@ -13,7 +13,9 @@
|
||||
|
||||
|
||||
module assignment2 #(width=5, ramsz=9, romsz=10) (
|
||||
input logic [0:0] clk,
|
||||
input logic [0:0] clk, input logic [0:0] rst
|
||||
`ifdef QUARTUS_SYNTH
|
||||
,
|
||||
input logic [4:0] HID_Register,
|
||||
input logic [0:0] HID_PC,
|
||||
input logic [0:0] HID_Hi_Low,
|
||||
@@ -22,13 +24,14 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
|
||||
output logic[7:0] out_seg_1,
|
||||
output logic[7:0] out_seg_2,
|
||||
output logic[7:0] out_seg_3
|
||||
`endif
|
||||
);
|
||||
// Intermediate for displaying high / low of PC or Register
|
||||
logic[15:0] PC_Reg_Display;
|
||||
|
||||
// Program / Instruction Counter Intermediates
|
||||
logic [romsz-1:0] pc_addr;
|
||||
logic [romsz-1:0] pc_addr_write;
|
||||
logic [2**width-1:0] pc_addr;
|
||||
logic [2**width-1:0] pc_addr_write;
|
||||
logic [0:0] pc_we;
|
||||
logic [2**width-1:0] instruction;
|
||||
|
||||
@@ -49,16 +52,16 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
|
||||
logic [0:0] rd_we;
|
||||
logic [31:0] regs_out [32];
|
||||
|
||||
// ALU intermeduates
|
||||
// ALU intermediates
|
||||
logic [2**width-1:0] rd_alu;
|
||||
logic [2**width-1:0] rt_alu;
|
||||
|
||||
instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
|
||||
instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
|
||||
|
||||
rom #(romsz, 2**width) ROM (pc_addr, instruction);
|
||||
rom #(romsz, width) ROM (pc_addr, instruction);
|
||||
|
||||
logic [2**width-1:0] rd_mem;
|
||||
ram #(ramsz, 2**width) RAM (clk, rd_alu, M2W, rt, rd_mem);
|
||||
ram #(ramsz, width) RAM (clk, rst, rd_alu, M2W, rt, rd_mem);
|
||||
|
||||
control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
|
||||
M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
|
||||
@@ -67,28 +70,25 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
|
||||
|
||||
register_file #(width, 5) REGS (
|
||||
clk, rd_we,
|
||||
instruction[20:16], rd,
|
||||
(RDST) ? instruction[15:11] : instruction[20:16], rt,
|
||||
(RDST) ? instruction[15:11] : instruction[20:16], rd,
|
||||
instruction[25:21], rs,
|
||||
instruction[20:16], rt,
|
||||
regs_out
|
||||
);
|
||||
// Always use sign-extension
|
||||
logic [2**width-1:0] rt_imm;
|
||||
sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
|
||||
// TODO:
|
||||
// - ALU srcB
|
||||
// - PCBranch (rel jump of 4-byte words)
|
||||
|
||||
alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
|
||||
alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags);
|
||||
assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
|
||||
|
||||
assign pc_we = B & flags[2];
|
||||
assign pc_addr_write = (rt_imm << 2) + pc_addr;
|
||||
assign rd_we = RW;
|
||||
assign rd = (M2R) ? rd_alu : rd_mem;
|
||||
|
||||
assign rd = (M2R) ? rd_mem : rd_alu;
|
||||
|
||||
|
||||
`ifdef QUARTUS_SYNTH
|
||||
// Temporary Test output
|
||||
// assign PC_Reg_Display = 16'hC342;
|
||||
|
||||
@@ -101,6 +101,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
|
||||
.segments2(out_seg_2),
|
||||
.segments3(out_seg_3)
|
||||
);
|
||||
|
||||
`endif
|
||||
endmodule
|
||||
`endif
|
||||
@@ -23,13 +23,13 @@ module control_unit (
|
||||
instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
|
||||
|
||||
always_comb begin
|
||||
M2R = TYPE_M & op[3];
|
||||
M2W = TYPE_M & ~op[3];
|
||||
M2R = TYPE_M & ~((op & 6'b001000) >> 3);
|
||||
M2W = TYPE_M & ((op & 6'b001000) >> 3);
|
||||
B = TYPE_B1 | TYPE_B2 | TYPE_J;
|
||||
ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
|
||||
ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
|
||||
RDST = TYPE_I; // Imm ops store back into rt
|
||||
RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
|
||||
ALU_FN = (func & {(4){TYPE_R}}) | ( {2'b00, (op & 6'b000011)} & {(4){TYPE_I}}) | (4'b0010 & {4{TYPE_B1 | TYPE_B2}});
|
||||
ALU_SRC = TYPE_I | TYPE_M;
|
||||
RDST = TYPE_R; // Imm ops store back into rt
|
||||
RW = TYPE_R | TYPE_I | M2R;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -2,14 +2,17 @@
|
||||
`define INSTRUCTION_COUNTER_H
|
||||
|
||||
module instruction_counter #(parameter width=5)(
|
||||
input logic [0:0] clk, input logic [0:0] we,
|
||||
input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] we,
|
||||
input logic [2**width-1:0] W,
|
||||
output logic [2**width-1:0] addr
|
||||
);
|
||||
|
||||
logic [2**width-1:0] pc;
|
||||
always_ff @(posedge clk) begin
|
||||
if (we) begin
|
||||
|
||||
always_ff @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
pc <= {(2**width){1'b0}};
|
||||
end else if (we) begin
|
||||
pc <= W;
|
||||
end else begin
|
||||
pc <= pc + 4;
|
||||
|
||||
+55
-27
@@ -1,76 +1,101 @@
|
||||
`include "assignment2.sv"
|
||||
|
||||
`timescale 1us/10ns
|
||||
|
||||
`define PRINT_REGISTERS(regs)\
|
||||
$display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",\
|
||||
regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15], \
|
||||
regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23] \
|
||||
);
|
||||
`define TEST_CHECK(cond) if (cond) begin end else begin \
|
||||
$display("Check %s failed\n", `"cond`"); \
|
||||
$display("Check %s failed", `"cond`"); \
|
||||
`PRINT_REGISTERS(CPU.REGS.regs); \
|
||||
num_errors += 1; \
|
||||
end
|
||||
|
||||
module mips_tb(input logic [0:0] clk);
|
||||
assignment2 #(5) CPU (clk);
|
||||
module mips_tb();
|
||||
logic [0:0] clk;
|
||||
logic [0:0] rst;
|
||||
assignment2 #(5) CPU (clk, rst);
|
||||
|
||||
initial clk = 0;
|
||||
initial rst = 0;
|
||||
always #1 clk = ~clk;
|
||||
|
||||
integer num_errors = 0;
|
||||
initial begin
|
||||
rst = 1;
|
||||
#2;
|
||||
rst = 0;
|
||||
#2;
|
||||
|
||||
$dumpfile("output.vcd");
|
||||
$dumpvars(0, clk);
|
||||
$dumpvars(1, CPU.REGS);
|
||||
$dumpvars(2, CPU.ROM);
|
||||
$dumpvars(3, CPU.PC);
|
||||
$dumpvars(4, CPU.pc_addr);
|
||||
$dumpvars(5, CPU.CONTROL_UNIT);
|
||||
$dumpvars(5, CPU.instruction);
|
||||
$dumpvars(5, CPU.ALU);
|
||||
$dumpvars(6, CPU.flags);
|
||||
|
||||
// Zero out lower registers
|
||||
$display("Beginning MIPS tests");
|
||||
assign num_errors = 0;
|
||||
|
||||
for (integer N = 1; N < 32; ++N)
|
||||
CPU.REGS.regs[N] = 32'd0;
|
||||
|
||||
// Check R-type / initialise
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7));
|
||||
|
||||
// Check load-store
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.RAM.mem[0] == CPU.REGS.regs[9]);
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[10] == CPU.RAM.mem[0]);
|
||||
|
||||
// Check arithmetic
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[9] + CPU.REGS.regs[10]));
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[12] == (CPU.REGS.regs[9] - CPU.REGS.regs[11]));
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3));
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[14] == (CPU.REGS.regs[12] + CPU.REGS.regs[13]));
|
||||
|
||||
// Check logic instructions
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[16] == (CPU.REGS.regs[9] & CPU.REGS.regs[13]));
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[17] == (CPU.REGS.regs[9] | CPU.REGS.regs[13]));
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[18] == (CPU.REGS.regs[9] ^ CPU.REGS.regs[13]));
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ));
|
||||
|
||||
// Check SLT instructions
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[20] == $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]));
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[21] == $unsigned(CPU.REGS.regs[12]) < $unsigned(CPU.REGS.regs[14]));
|
||||
|
||||
// Check loop branching
|
||||
#2;
|
||||
for (integer N = 1; N < 11; ++N) begin
|
||||
#1;
|
||||
`TEST_CHECK(CPU.REGS.regs[0] == 32'(N));
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[8] == 32'(N));
|
||||
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[22] == $unsigned(CPU.REGS.regs[8]) < $unsigned(CPU.REGS.regs[13]));
|
||||
if (N < 10)
|
||||
#2;
|
||||
#2;
|
||||
end
|
||||
|
||||
// Final state check
|
||||
#1;
|
||||
#2;
|
||||
`TEST_CHECK(CPU.REGS.regs[8] == 32'd10);
|
||||
`TEST_CHECK(CPU.REGS.regs[9] == 32'd7);
|
||||
`TEST_CHECK(CPU.REGS.regs[10] == 32'd7);
|
||||
@@ -89,7 +114,10 @@ module mips_tb(input logic [0:0] clk);
|
||||
`TEST_CHECK(CPU.REGS.regs[22] == 32'd0);
|
||||
`TEST_CHECK(CPU.REGS.regs[23] == 32'd0);
|
||||
|
||||
if (num_errors == 0) $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m");
|
||||
else $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors);
|
||||
if (num_errors == 0) begin $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m");
|
||||
end else begin $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors); end
|
||||
|
||||
$dumpflush;
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
+8
-11
@@ -2,25 +2,22 @@
|
||||
`define RAM_H
|
||||
|
||||
module ram #(addrwidth=9, datawidth=5)(
|
||||
input logic [0:0] clk,
|
||||
input logic [2**addrwidth-1:0] addr,
|
||||
input logic [0:0] clk, input logic [0:0] rst,
|
||||
input logic [addrwidth-1:0] addr,
|
||||
input logic [0:0] we,
|
||||
input logic [datawidth-1:0] data_in,
|
||||
output logic [datawidth-1:0] data_out
|
||||
);
|
||||
|
||||
// TODO: Make this byte-sized, NOT word-sized!
|
||||
logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
|
||||
|
||||
// NOTE: Possible issue with assignments still pending by end of initial block
|
||||
initial begin
|
||||
for (integer ADDR = 0; ADDR < 2**(addrwidth+$clog2(datawidth)-3); ++ADDR) begin
|
||||
mem[ADDR] <= 8'b0;
|
||||
end
|
||||
end
|
||||
logic [2**datawidth-1:0] mem[0:255];
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (we) begin
|
||||
if (rst) begin
|
||||
for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
|
||||
mem[ADDR] <= 32'b0;
|
||||
end
|
||||
end else if (we) begin
|
||||
mem[addr] <= data_in;
|
||||
end
|
||||
end
|
||||
|
||||
@@ -12,7 +12,8 @@ module register_file #(parameter width=5, parameter nregs=5)(
|
||||
logic [2**width-1:0] regs[2**nregs];
|
||||
|
||||
initial begin
|
||||
regs[0] = {(2**width){1'b0}};
|
||||
for (integer N = 0; N < (2**nregs); ++N)
|
||||
regs[N] = 32'd0;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
|
||||
+5
-5
@@ -3,19 +3,19 @@
|
||||
|
||||
module rom #(parameter m=7,p=4) (
|
||||
input logic [m-1:0] Ad,
|
||||
output logic [p-1:0] Dout
|
||||
output logic [2**p-1:0] Dout
|
||||
);
|
||||
|
||||
logic [p-1:0] mem[2**m-1:0];
|
||||
assign Dout = mem[Ad];
|
||||
logic [2**p-1:0] mem[2**m];
|
||||
assign Dout = mem[Ad>>2]; // Because word-size versus byte size hack
|
||||
|
||||
//Load the program in memory
|
||||
// The machine code stored in text file program.dat written in Hex format
|
||||
initial begin
|
||||
`ifdef QUARTUS_SYNTH
|
||||
$readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
|
||||
$readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
|
||||
`else
|
||||
$readmemh("../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
|
||||
$readmemh("../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
|
||||
`endif
|
||||
end
|
||||
endmodule // end rom module
|
||||
|
||||
+5
-5
@@ -3,19 +3,19 @@
|
||||
|
||||
module rom #(parameter m=7,p=4) (
|
||||
input logic [m-1:0] Ad,
|
||||
output logic [p-1:0] Dout
|
||||
output logic [2**p-1:0] Dout
|
||||
);
|
||||
|
||||
logic [p-1:0] mem[2**m-1:0];
|
||||
assign Dout = mem[Ad];
|
||||
logic [2**p-1:0] mem[2**m];
|
||||
assign Dout = mem[Ad>>2]; // Because word-size versus byte size hack
|
||||
|
||||
//Load the program in memory
|
||||
// The machine code stored in text file program.dat written in Hex format
|
||||
initial begin
|
||||
`ifdef QUARTUS_SYNTH
|
||||
$readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
|
||||
$readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
|
||||
`else
|
||||
$readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
|
||||
$readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
|
||||
`endif
|
||||
end
|
||||
endmodule // end rom module
|
||||
|
||||
@@ -6,9 +6,11 @@ module sign_extender #(in_width=4, out_width=5)(
|
||||
input logic [2**in_width-1:0] val,
|
||||
output logic [2**out_width-1:0] ext_val
|
||||
);
|
||||
logic [0:0] msb;
|
||||
assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
|
||||
always_comb begin
|
||||
if (op) begin
|
||||
ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
|
||||
ext_val = { {(2**(out_width-in_width)){msb}}, val};
|
||||
end else begin
|
||||
ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
|
||||
end
|
||||
|
||||
+74
-1052
File diff suppressed because it is too large.
Load diff
Binary file not shown.
+148
-148
@@ -11,32 +11,32 @@ cModel Technology
|
||||
d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
|
||||
valu
|
||||
Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
|
||||
Z1 !s110 1792107153
|
||||
Z1 !s110 1792115142
|
||||
!i10b 1
|
||||
!s100 meV@F]8El[fjh_ULLA@iR2
|
||||
!s100 kh0:K2RRk@<XUA5?_0ad>1
|
||||
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
|
||||
I<0ZXcWH[]FIo]cjVef19`2
|
||||
Im?EZg:mSI^D?=D>QBY^1B0
|
||||
Z3 VDg1SIo80bB@j0V0VzS_@n1
|
||||
S1
|
||||
Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
|
||||
w1792036226
|
||||
Z5 w1792113810
|
||||
8alu.sv
|
||||
Falu.sv
|
||||
!i122 90
|
||||
L0 9 31
|
||||
Z5 OV;L;2020.1;71
|
||||
!i122 179
|
||||
L0 10 33
|
||||
Z6 OV;L;2020.1;71
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
Z6 !s108 1792107152.000000
|
||||
Z7 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
|
||||
Z8 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
|
||||
Z7 !s108 1792115141.000000
|
||||
Z8 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
|
||||
Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
|
||||
!i113 1
|
||||
Z9 o-work work -sv
|
||||
Z10 tCvgOpt 0
|
||||
Z10 o-work work -sv
|
||||
Z11 tCvgOpt 0
|
||||
valu_tb
|
||||
R0
|
||||
Z11 !s110 1792107152
|
||||
Z12 !s110 1792115141
|
||||
!i10b 1
|
||||
!s100 8=>8o`KV]hRM]V8AV?S[C1
|
||||
R2
|
||||
@@ -44,46 +44,46 @@ Iz[VXe9HJ@koSDFNR185;i1
|
||||
R3
|
||||
S1
|
||||
R4
|
||||
Z12 w1789355084
|
||||
Z13 w1789355084
|
||||
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
|
||||
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
|
||||
!i122 79
|
||||
!i122 168
|
||||
L0 3 214
|
||||
R5
|
||||
R6
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R6
|
||||
R7
|
||||
!s107 lu.sv|asu.sv|alu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
|
||||
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
|
||||
!i113 1
|
||||
R9
|
||||
R10
|
||||
R11
|
||||
vassignment2
|
||||
R0
|
||||
R1
|
||||
!i10b 1
|
||||
!s100 GJCIM_l8Wa[9;0<RIgA[E0
|
||||
!s100 9I6c?eD<Ld>]amhL__2Jz1
|
||||
R2
|
||||
I7i7cEGK6dmN[?gYSA`MeR3
|
||||
IFfHj7VAM^H^0]`kMd62bZ2
|
||||
R3
|
||||
S1
|
||||
R4
|
||||
w1792106709
|
||||
R5
|
||||
8assignment2.sv
|
||||
Fassignment2.sv
|
||||
!i122 90
|
||||
!i122 179
|
||||
L0 15 91
|
||||
R5
|
||||
R6
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R6
|
||||
R7
|
||||
R8
|
||||
!i113 1
|
||||
R9
|
||||
!i113 1
|
||||
R10
|
||||
R11
|
||||
vasu
|
||||
R0
|
||||
R1
|
||||
@@ -97,21 +97,21 @@ R4
|
||||
w1790228118
|
||||
8asu.sv
|
||||
Fasu.sv
|
||||
!i122 90
|
||||
!i122 179
|
||||
L0 4 21
|
||||
R5
|
||||
R6
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R6
|
||||
R7
|
||||
R8
|
||||
!i113 1
|
||||
R9
|
||||
!i113 1
|
||||
R10
|
||||
R11
|
||||
vasu_tb
|
||||
R0
|
||||
R11
|
||||
R12
|
||||
!i10b 1
|
||||
!s100 ?AMT1ejDgW=83T_P=nh4G1
|
||||
R2
|
||||
@@ -119,24 +119,24 @@ IcS>Hk9oO:RGFmfdUY9[i90
|
||||
R3
|
||||
S1
|
||||
R4
|
||||
Z13 w1789513270
|
||||
Z14 w1789513270
|
||||
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
|
||||
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
|
||||
!i122 82
|
||||
!i122 171
|
||||
L0 3 120
|
||||
R5
|
||||
R6
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R6
|
||||
R7
|
||||
!s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
|
||||
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
|
||||
!i113 1
|
||||
R9
|
||||
R10
|
||||
R11
|
||||
vByteIM
|
||||
R0
|
||||
R11
|
||||
R12
|
||||
!i10b 1
|
||||
!s100 ]V5Di195@?V=P`Y?PM;U=0
|
||||
R2
|
||||
@@ -144,47 +144,47 @@ Ie:hP;^zFCE^LSAOVoDF6C3
|
||||
R3
|
||||
S1
|
||||
R4
|
||||
w1792106811
|
||||
w1792112374
|
||||
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
|
||||
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
|
||||
!i122 83
|
||||
!i122 172
|
||||
L0 3 12
|
||||
R5
|
||||
R6
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R6
|
||||
R7
|
||||
!s107 rom.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
|
||||
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
|
||||
!i113 1
|
||||
R9
|
||||
R10
|
||||
R11
|
||||
n@byte@i@m
|
||||
vcontrol_unit
|
||||
R0
|
||||
R1
|
||||
!i10b 1
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Reference in new issue
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