diff --git a/ModelSim/Assignment_2.cr.mti b/ModelSim/Assignment_2.cr.mti
index ca7cdef..3c10b2c 100644
--- a/ModelSim/Assignment_2.cr.mti
+++ b/ModelSim/Assignment_2.cr.mti
@@ -41,7 +41,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	control_unit
 
-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module rom
 -- Compiling module ram
@@ -52,9 +52,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 -- Compiling module asu
 -- Compiling module lu
 -- Compiling module alu
-** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(1)
-** while parsing file included at assignment2.sv(9)
-** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
 -- Compiling module shifter
 -- Compiling module sign_extender
 -- Compiling module seven_seg
@@ -64,6 +61,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 
 Top level modules:
 	shifter
+	seven_seg_4digit
 	mips_tb
 
 } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
@@ -88,7 +86,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	shifter_tb
 
-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module rom
 -- Compiling module ram
@@ -99,8 +97,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 -- Compiling module asu
 -- Compiling module lu
 -- Compiling module alu
-** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv(9)
-** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
 -- Compiling module shifter
 -- Compiling module sign_extender
 -- Compiling module seven_seg
@@ -109,6 +105,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 
 Top level modules:
 	shifter
+	seven_seg_4digit
 	assignment2
 
 } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
@@ -142,13 +139,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	sign_extender
 
-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module asu
 -- Compiling module lu
 -- Compiling module alu
-** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv(1)
-** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
 -- Compiling module alu_tb
 
 Top level modules:
@@ -161,12 +156,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
 Top level modules:
 	instruction_counter
 
-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module asu
 -- Compiling module lu
 -- Compiling module alu
-** Warning: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
 
 Top level modules:
 	alu
diff --git a/ModelSim/Assignment_2.mpf b/ModelSim/Assignment_2.mpf
index 62dffb1..09c2ff3 100644
--- a/ModelSim/Assignment_2.mpf
+++ b/ModelSim/Assignment_2.mpf
@@ -220,7 +220,7 @@ Resolution = ps
 UserTimeUnit = default
 
 ; Default run length
-RunLength = 1 ns
+RunLength = 1 us
 
 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 5000
@@ -412,49 +412,49 @@ Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 22
 Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv
-Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
-Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792107144 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792114203 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_2 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv
-Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_3 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv
-Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_4 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
-Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792039197 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_5 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv
-Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792040117 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_6 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
-Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792104861 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_7 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
-Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228118 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228118 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_8 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
-Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_9 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
-Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789513270 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_10 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
-Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792106709 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_11 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
-Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788418794 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788418794 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_12 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
-Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789513270 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_13 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
-Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_14 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
-Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792038654 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_15 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
-Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
-Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1791854498 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
-Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792036226 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792113810 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_18 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
-Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792106811 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1792112374 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
-Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1791866874 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1791866874 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_20 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
-Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
-Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792035553 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
diff --git a/ModelSim/ByteIM.sv.bak b/ModelSim/ByteIM.sv.bak
new file mode 100644
index 0000000..6e913a7
--- /dev/null
+++ b/ModelSim/ByteIM.sv.bak
@@ -0,0 +1,14 @@
+`include "rom.sv"
+
+module ByteIM #(parameter m=5,n=2) (
+    input logic [m-1:0] Ad,
+    output logic [(2**n)*8-1:0] Dout );
+
+    // 2**n byte wide words
+    // m bit wide byte address
+    // 2**m bytes of memory
+    // 2**(m-n) memory words
+    // 2**(n+3) bit wide words
+    // Reads the whole word that contains the addressed byte
+    ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
+endmodule
diff --git a/ModelSim/alu.sv b/ModelSim/alu.sv
index 4bc9398..77f31e5 100644
--- a/ModelSim/alu.sv
+++ b/ModelSim/alu.sv
@@ -6,6 +6,7 @@
 
 // flags[0:0] = Cout
 // flags[1:1] = Overflow
+// flags[2:2] = Zero
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
     output logic [2**width-1:0] OUT_1, output logic[2:0] flags
@@ -15,26 +16,30 @@ module alu #(parameter width=2)(input logic [3:0] op,
     logic [2**width-1:0] asu_out;
     logic [2:0] asu_flags;
 
-    asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+    assign asu_op = op[1];
+    logic [0:0] asu_cout_flag;
+    asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_cout_flag);
 
     logic [2**width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
 
+    assign asu_flags[1] = asu_cout_flag ^ asu_flags[0];
     always_comb begin
         case (op) 
-            4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b0110: begin OUT_1 = lu_out;  flags = asu_flags; end
-            4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
-            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
-            default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
+            4'b0000: begin OUT_1 = asu_out; end
+            4'b0001: begin OUT_1 = asu_out; end
+            4'b0010: begin OUT_1 = asu_out; end
+            4'b0011: begin OUT_1 = asu_out; end
+            4'b0100: begin OUT_1 = lu_out; end
+            4'b0101: begin OUT_1 = lu_out; end
+            4'b0110: begin OUT_1 = lu_out; end
+            4'b0111: begin OUT_1 = lu_out; end
+            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; end
+            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; end
+            default: begin OUT_1 = {(2**width){1'b0}}; end
         endcase
         asu_flags[2] = OUT_1 == 0;
+        flags = asu_flags;
     end
 endmodule
 `endif
diff --git a/ModelSim/assignment2.sv b/ModelSim/assignment2.sv
index 716d8f7..eb13b83 100644
--- a/ModelSim/assignment2.sv
+++ b/ModelSim/assignment2.sv
@@ -13,7 +13,9 @@
 
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (
-	input logic [0:0] clk,
+	input logic [0:0] clk, input logic [0:0] rst
+`ifdef QUARTUS_SYNTH
+    ,
 	input logic [4:0] HID_Register,
 	input logic [0:0] HID_PC,
 	input logic [0:0] HID_Hi_Low,
@@ -22,13 +24,14 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	output logic[7:0] out_seg_1,
 	output logic[7:0] out_seg_2,
 	output logic[7:0] out_seg_3
+`endif
 	);
 	// Intermediate for displaying high / low of PC or Register
 	logic[15:0] PC_Reg_Display;
 	
 	// Program / Instruction Counter Intermediates
-	logic [romsz-1:0] pc_addr;
-	logic [romsz-1:0] pc_addr_write;
+	logic [2**width-1:0] pc_addr;
+	logic [2**width-1:0] pc_addr_write;
 	logic [0:0] pc_we;
 	logic [2**width-1:0] instruction;
 	
@@ -49,16 +52,16 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [0:0] rd_we;
 	logic [31:0] regs_out [32];
 
-    // ALU intermeduates
+    // ALU intermediates
 	logic [2**width-1:0] rd_alu;
 	logic [2**width-1:0] rt_alu;
 	
-	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
+	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
 	
-	rom #(romsz, 2**width) ROM (pc_addr, instruction);
+	rom #(romsz, width) ROM (pc_addr, instruction);
 
 	logic [2**width-1:0] rd_mem;
-	ram #(ramsz, 2**width) RAM (clk, rd_alu, M2W, rt, rd_mem);
+	ram #(ramsz, width) RAM (clk, rst, rd_alu, M2W, rt, rd_mem);
 	
 	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
 		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
@@ -67,28 +70,25 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 
 	register_file #(width, 5) REGS (
 		clk, rd_we, 
-		instruction[20:16], rd,
-		(RDST) ? instruction[15:11] : instruction[20:16], rt,
-		instruction[25:21], rs, 
+		(RDST) ? instruction[15:11] : instruction[20:16], rd,
+		instruction[25:21], rs,
+		instruction[20:16], rt, 
 		regs_out
    );
     // Always use sign-extension
     logic [2**width-1:0] rt_imm;
     sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
-    // TODO:
-    //  - ALU srcB
-    //  - PCBranch (rel jump of 4-byte words)
 
-	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
+	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags);
     assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
 
 	assign pc_we = B & flags[2];
 	assign pc_addr_write = (rt_imm << 2) + pc_addr;
 	assign rd_we = RW;
-	assign rd = (M2R) ? rd_alu : rd_mem;
-
+	assign rd = (M2R) ? rd_mem : rd_alu;
 
 
+`ifdef QUARTUS_SYNTH
 	// Temporary Test output
 	// assign PC_Reg_Display = 16'hC342;
 
@@ -101,6 +101,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 		.segments2(out_seg_2),
 		.segments3(out_seg_3)
 	);
-
+`endif
 endmodule
 `endif
diff --git a/ModelSim/control_unit.sv b/ModelSim/control_unit.sv
index 85a673c..58d7cdd 100644
--- a/ModelSim/control_unit.sv
+++ b/ModelSim/control_unit.sv
@@ -23,13 +23,13 @@ module control_unit (
     instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
 
     always_comb begin
-        M2R = TYPE_M & op[3];
-        M2W = TYPE_M & ~op[3];
+        M2R = TYPE_M & ~((op & 6'b001000) >> 3);
+        M2W = TYPE_M & ((op & 6'b001000) >> 3);
         B = TYPE_B1 | TYPE_B2 | TYPE_J;
-        ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
-        ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
-        RDST = TYPE_I;  // Imm ops store back into rt
-        RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
+        ALU_FN = (func & {(4){TYPE_R}}) | ( {2'b00, (op & 6'b000011)} & {(4){TYPE_I}}) | (4'b0010 & {4{TYPE_B1 | TYPE_B2}});
+        ALU_SRC = TYPE_I | TYPE_M;
+        RDST = TYPE_R;  // Imm ops store back into rt
+        RW = TYPE_R | TYPE_I | M2R;
     end
 
 endmodule
diff --git a/ModelSim/instruction_counter.sv b/ModelSim/instruction_counter.sv
index 780b99a..773d81b 100644
--- a/ModelSim/instruction_counter.sv
+++ b/ModelSim/instruction_counter.sv
@@ -2,14 +2,17 @@
 `define INSTRUCTION_COUNTER_H
 
 module instruction_counter #(parameter width=5)(
-    input logic [0:0] clk, input logic [0:0] we,
+    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] we,
     input logic [2**width-1:0] W,
     output logic [2**width-1:0] addr
 );
 
     logic [2**width-1:0] pc;
-    always_ff @(posedge clk) begin
-        if (we) begin
+    
+    always_ff @(posedge clk or posedge rst) begin
+        if (rst) begin
+            pc <= {(2**width){1'b0}};
+        end else if (we) begin
             pc <= W;
         end else begin
             pc <= pc + 4;
diff --git a/ModelSim/mips.sv b/ModelSim/mips.sv
index 4ff213c..4a0a0d7 100644
--- a/ModelSim/mips.sv
+++ b/ModelSim/mips.sv
@@ -1,76 +1,101 @@
 `include "assignment2.sv"
 
+`timescale 1us/10ns
+
 `define PRINT_REGISTERS(regs)\
     $display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",\
         regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15],   \
         regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23]  \
     );
 `define TEST_CHECK(cond) if (cond) begin end else begin   \
-        $display("Check %s failed\n", `"cond`");          \
+        $display("Check %s failed", `"cond`");            \
         `PRINT_REGISTERS(CPU.REGS.regs);                  \
         num_errors += 1;                                  \
     end
 
-module mips_tb(input logic [0:0] clk);
-    assignment2 #(5) CPU (clk);
+module mips_tb();
+    logic [0:0] clk;
+    logic [0:0] rst;
+    assignment2 #(5) CPU (clk, rst);
+
+    initial clk = 0;
+    initial rst = 0;
+    always #1 clk = ~clk;
 
     integer num_errors = 0;
     initial begin
+        rst = 1;
+        #2;
+        rst = 0;
+        #2;
+
+        $dumpfile("output.vcd");
+		$dumpvars(0, clk);
+		$dumpvars(1, CPU.REGS);
+		$dumpvars(2, CPU.ROM);
+		$dumpvars(3, CPU.PC);
+		$dumpvars(4, CPU.pc_addr);
+		$dumpvars(5, CPU.CONTROL_UNIT);
+		$dumpvars(5, CPU.instruction);
+		$dumpvars(5, CPU.ALU);
+		$dumpvars(6, CPU.flags);
+
         // Zero out lower registers
         $display("Beginning MIPS tests");
-        assign num_errors = 0;
-
-        for (integer N = 1; N < 32; ++N)
-            CPU.REGS.regs[N] = 32'd0;
 
         // Check R-type / initialise
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7));
 
         // Check load-store
-        #1;
+        #2;
         `TEST_CHECK(CPU.RAM.mem[0] == CPU.REGS.regs[9]);
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[10] == CPU.RAM.mem[0]);
 
         // Check arithmetic
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[9] + CPU.REGS.regs[10]));
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[12] == (CPU.REGS.regs[9] - CPU.REGS.regs[11]));
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3));
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[14] == (CPU.REGS.regs[12] + CPU.REGS.regs[13]));
 
         // Check logic instructions
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[16] == (CPU.REGS.regs[9] & CPU.REGS.regs[13]));
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[17] == (CPU.REGS.regs[9] | CPU.REGS.regs[13]));
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[18] == (CPU.REGS.regs[9] ^ CPU.REGS.regs[13]));
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ));
 
         // Check SLT instructions
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[20] == $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]));
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[21] == $unsigned(CPU.REGS.regs[12]) < $unsigned(CPU.REGS.regs[14]));
         
         // Check loop branching
+        #2;
         for (integer N = 1; N < 11; ++N) begin
-            #1;
-            `TEST_CHECK(CPU.REGS.regs[0] == 32'(N));
-            #1;
+            #2;
+            `TEST_CHECK(CPU.REGS.regs[8] == 32'(N));
+            
+            #2;
             `TEST_CHECK(CPU.REGS.regs[22] == $unsigned(CPU.REGS.regs[8]) < $unsigned(CPU.REGS.regs[13]));
+            if (N < 10)
+                #2;
+            #2;
         end
 
         // Final state check
-        #1;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[8]  == 32'd10);
         `TEST_CHECK(CPU.REGS.regs[9]  == 32'd7);
         `TEST_CHECK(CPU.REGS.regs[10] == 32'd7);
@@ -89,7 +114,10 @@ module mips_tb(input logic [0:0] clk);
         `TEST_CHECK(CPU.REGS.regs[22] == 32'd0);
         `TEST_CHECK(CPU.REGS.regs[23] == 32'd0);
 
-        if (num_errors == 0) $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m");
-        else $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors);
+        if (num_errors == 0) begin $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m");
+        end else begin $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors); end
+
+        $dumpflush;
+        $finish;
     end
 endmodule
\ No newline at end of file
diff --git a/ModelSim/ram.sv b/ModelSim/ram.sv
index eaddf77..40d16dd 100644
--- a/ModelSim/ram.sv
+++ b/ModelSim/ram.sv
@@ -2,25 +2,22 @@
 `define RAM_H
 
 module ram #(addrwidth=9, datawidth=5)(
-    input logic [0:0] clk,
-    input logic [2**addrwidth-1:0] addr,
+    input logic [0:0] clk, input logic [0:0] rst,
+    input logic [addrwidth-1:0] addr,
     input logic [0:0] we,
     input logic [datawidth-1:0] data_in,
     output logic [datawidth-1:0] data_out
 );
 
     // TODO: Make this byte-sized, NOT word-sized!
-    logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
-
-    // NOTE: Possible issue with assignments still pending by end of initial block
-    initial begin
-        for (integer ADDR = 0; ADDR < 2**(addrwidth+$clog2(datawidth)-3); ++ADDR) begin
-            mem[ADDR] <= 8'b0;
-        end
-    end
+    logic [2**datawidth-1:0] mem[0:255];
 
     always_ff @(posedge clk) begin
-        if (we) begin
+        if (rst) begin
+            for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
+                mem[ADDR] <= 32'b0;
+            end
+        end else if (we) begin
             mem[addr] <= data_in;
         end
     end
diff --git a/ModelSim/register_file.sv b/ModelSim/register_file.sv
index f159ccd..5100916 100644
--- a/ModelSim/register_file.sv
+++ b/ModelSim/register_file.sv
@@ -12,7 +12,8 @@ module register_file #(parameter width=5, parameter nregs=5)(
     logic [2**width-1:0] regs[2**nregs];
 
     initial begin
-        regs[0] = {(2**width){1'b0}};
+        for (integer N = 0; N < (2**nregs); ++N)
+            regs[N] = 32'd0;
     end
 
     always_ff @(posedge clk) begin
diff --git a/ModelSim/rom.sv b/ModelSim/rom.sv
index f41020f..08e882a 100644
--- a/ModelSim/rom.sv
+++ b/ModelSim/rom.sv
@@ -3,19 +3,19 @@
 
 module rom #(parameter m=7,p=4) (
         input logic [m-1:0] Ad,
-        output logic [p-1:0] Dout
+        output logic [2**p-1:0] Dout
     );
     
-    logic [p-1:0] mem[2**m-1:0];
-    assign Dout = mem[Ad];
+    logic [2**p-1:0] mem[2**m];
+    assign Dout = mem[Ad>>2];   // Because word-size versus byte size hack
 
     //Load the program in memory
     // The machine code stored in text file program.dat written in Hex format
     initial begin
         `ifdef QUARTUS_SYNTH
-            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
         `else
-            $readmemh("../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+            $readmemh("../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
         `endif
     end
 endmodule // end rom module
diff --git a/ModelSim/rom.sv.bak b/ModelSim/rom.sv.bak
index e18e3c7..9f9a666 100644
--- a/ModelSim/rom.sv.bak
+++ b/ModelSim/rom.sv.bak
@@ -3,19 +3,19 @@
 
 module rom #(parameter m=7,p=4) (
         input logic [m-1:0] Ad,
-        output logic [p-1:0] Dout
+        output logic [2**p-1:0] Dout
     );
     
-    logic [p-1:0] mem[2**m-1:0];
-    assign Dout = mem[Ad];
+    logic [2**p-1:0] mem[2**m];
+    assign Dout = mem[Ad>>2];   // Because word-size versus byte size hack
 
     //Load the program in memory
     // The machine code stored in text file program.dat written in Hex format
     initial begin
         `ifdef QUARTUS_SYNTH
-            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
         `else
-            $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
+            $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
         `endif
     end
 endmodule // end rom module
diff --git a/ModelSim/sign_extender.sv b/ModelSim/sign_extender.sv
index 77a9ae1..a0e2ef9 100644
--- a/ModelSim/sign_extender.sv
+++ b/ModelSim/sign_extender.sv
@@ -6,9 +6,11 @@ module sign_extender #(in_width=4, out_width=5)(
     input logic [2**in_width-1:0] val,
     output logic [2**out_width-1:0] ext_val
 );
+    logic [0:0] msb;
+    assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
     always_comb begin
         if (op) begin
-            ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
+            ext_val = { {(2**(out_width-in_width)){msb}}, val};
         end else begin
             ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
         end
diff --git a/ModelSim/transcript b/ModelSim/transcript
index bbc6bf7..e4c5b17 100644
--- a/ModelSim/transcript
+++ b/ModelSim/transcript
@@ -1,40 +1,7 @@
-# Loading project Assignment_1_Q2
-# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini
 # Loading project Assignment_2
-# Compile of alu.sv was successful with warnings.
-# Compile of alu_tb.sv was successful with warnings.
-# Compile of assignment2.sv failed with 3 errors.
-# Compile of asu.sv was successful.
-# Compile of asu_tb.sv was successful.
-# Compile of ByteIM.sv failed with 1 errors.
-# Compile of control_unit.sv was successful.
-# Compile of instruction_classifier.sv was successful.
-# Compile of instruction_classifier_tb.sv was successful.
-# Compile of instruction_counter.sv was successful.
-# Compile of lu.sv was successful.
-# Compile of lu_tb.sv was successful.
-# Compile of mips.sv failed with 3 errors.
-# Compile of ram.sv was successful.
-# Compile of register_file.sv was successful.
-# Compile of rom.sv was successful.
-# Compile of seven_seg.sv was successful.
-# Compile of seven_seg_4digit.sv was successful.
-# Compile of seven_seg_tb.sv was successful.
-# Compile of shifter.sv was successful.
-# Compile of shifter_tb.sv was successful.
-# Compile of sign_extender.sv was successful.
-# Compile of tests.sv failed with 6 errors.
-# 23 compiles, 4 failed with 13 errors.
-# Compile of assignment2.sv failed with 3 errors.
-# Compile of assignment2.sv failed with 1 errors.
-# Compile of assignment2.sv failed with 1 errors.
-# Compile of assignment2.sv was successful with warnings.
-# Compile of mips.sv was successful with warnings.
-# Compile of ByteIM.sv failed with 1 errors.
-# Compile of ByteIM.sv was successful.
-# Compile of alu.sv was successful with warnings.
-# Compile of alu_tb.sv was successful with warnings.
-# Compile of assignment2.sv was successful with warnings.
+# Compile of alu.sv was successful.
+# Compile of alu_tb.sv was successful.
+# Compile of assignment2.sv was successful.
 # Compile of asu.sv was successful.
 # Compile of asu_tb.sv was successful.
 # Compile of ByteIM.sv was successful.
@@ -44,7 +11,7 @@
 # Compile of instruction_counter.sv was successful.
 # Compile of lu.sv was successful.
 # Compile of lu_tb.sv was successful.
-# Compile of mips.sv was successful with warnings.
+# Compile of mips.sv was successful.
 # Compile of ram.sv was successful.
 # Compile of register_file.sv was successful.
 # Compile of rom.sv was successful.
@@ -57,7 +24,7 @@
 # 22 compiles, 0 failed with no errors.
 vsim work.mips_tb
 # vsim work.mips_tb 
-# Start time: 10:28:41 on Oct 16,2026
+# Start time: 12:45:51 on Oct 16,2026
 # Loading sv_std.std
 # Loading work.mips_tb
 # Loading work.assignment2
@@ -71,188 +38,67 @@ vsim work.mips_tb
 # Loading work.alu
 # Loading work.asu
 # Loading work.lu
-# Loading work.seven_seg_4digit
-# Loading work.seven_seg
-# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'.  Expected 8, found 1.
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'.
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61
-# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82
+# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
+# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
+# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
+# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
+add wave -position end  sim:/mips_tb/rst
 add wave -position end  sim:/mips_tb/clk
+run
+# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18.    : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM
+run
+force -freeze sim:/mips_tb/clk 1 0, 0 {50 ns} -r 100
+force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20
+run
+quit -sim
+# End time: 12:47:55 on Oct 16,2026, Elapsed time: 0:02:04
+# Errors: 0, Warnings: 7
+vsim work.mips_tb
+# vsim work.mips_tb 
+# Start time: 12:47:56 on Oct 16,2026
+# Loading sv_std.std
+# Loading work.mips_tb
+# Loading work.assignment2
+# Loading work.instruction_counter
+# Loading work.rom
+# Loading work.ram
+# Loading work.control_unit
+# Loading work.instruction_classifier
+# Loading work.register_file
+# Loading work.sign_extender
+# Loading work.alu
+# Loading work.asu
+# Loading work.lu
+# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
+# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
+# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
+# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
+add wave -position end  sim:/mips_tb/clk
+add wave -position end  sim:/mips_tb/rst
 add wave -position end  sim:/mips_tb/num_errors
-add wave -position end  sim:/mips_tb/CPU/instruction
+force -freeze sim:/mips_tb/rst 1 0 -cancel 20
+force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20
+force -freeze sim:/mips_tb/clk 0 0, 1 {50 ns} -r 100
+run
+# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18.    : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM
+add wave -position end  sim:/mips_tb/CPU/regs_out
 run
-# ** Warning: (vsim-7) Failed to open readmem file "./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt" in read mode.
-# No such file or directory. (errno = ENOENT)    : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/ROM
-# Beginning MIPS tests
-# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[8]  == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[9]  == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[10] == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[11] == 32'd14 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[12] == -32'sd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[14] == 32'd3 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[16] == 32'd2 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[17] == 32'd15 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[18] == 32'd13 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == -32'sd16 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[20] == 32'd1 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# All MIPS tests passing
 quit -sim
-# End time: 10:32:02 on Oct 16,2026, Elapsed time: 0:03:21
-# Errors: 0, Warnings: 27
-# Compile of alu.sv was successful with warnings.
-# Compile of alu_tb.sv was successful with warnings.
-# Compile of assignment2.sv was successful with warnings.
-# Compile of asu.sv was successful.
-# Compile of asu_tb.sv was successful.
-# Compile of ByteIM.sv was successful.
-# Compile of control_unit.sv was successful.
-# Compile of instruction_classifier.sv was successful.
-# Compile of instruction_classifier_tb.sv was successful.
-# Compile of instruction_counter.sv was successful.
-# Compile of lu.sv was successful.
-# Compile of lu_tb.sv was successful.
-# Compile of mips.sv was successful with warnings.
-# Compile of ram.sv was successful.
-# Compile of register_file.sv was successful.
-# Compile of rom.sv was successful.
-# Compile of seven_seg.sv was successful.
-# Compile of seven_seg_4digit.sv was successful.
-# Compile of seven_seg_tb.sv was successful.
-# Compile of shifter.sv was successful.
-# Compile of shifter_tb.sv was successful.
-# Compile of sign_extender.sv was successful.
-# 22 compiles, 0 failed with no errors.
+# End time: 12:50:34 on Oct 16,2026, Elapsed time: 0:02:38
+# Errors: 0, Warnings: 6
 vsim work.mips_tb
 # vsim work.mips_tb 
-# Start time: 10:33:32 on Oct 16,2026
+# Start time: 12:50:36 on Oct 16,2026
 # Loading sv_std.std
 # Loading work.mips_tb
 # Loading work.assignment2
@@ -266,844 +112,20 @@ vsim work.mips_tb
 # Loading work.alu
 # Loading work.asu
 # Loading work.lu
-# Loading work.seven_seg_4digit
-# Loading work.seven_seg
-# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'.  Expected 8, found 1.
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'.
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61
-# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82
-run
-# Beginning MIPS tests
-# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[8]  == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[9]  == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[10] == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[11] == 32'd14 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[12] == -32'sd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[14] == 32'd3 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[16] == 32'd2 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[17] == 32'd15 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[18] == 32'd13 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == -32'sd16 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[20] == 32'd1 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# All MIPS tests passing
+# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
+# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
+# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
+# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
 add wave -position end  sim:/mips_tb/clk
-run -all
-run
-quit -sim
-# End time: 10:42:49 on Oct 16,2026, Elapsed time: 0:09:17
-# Errors: 0, Warnings: 14
-vsim work.mips_tb
-# vsim work.mips_tb 
-# Start time: 10:42:57 on Oct 16,2026
-# Loading sv_std.std
-# Loading work.mips_tb
-# Loading work.assignment2
-# Loading work.instruction_counter
-# Loading work.rom
-# Loading work.ram
-# Loading work.control_unit
-# Loading work.instruction_classifier
-# Loading work.register_file
-# Loading work.sign_extender
-# Loading work.alu
-# Loading work.asu
-# Loading work.lu
-# Loading work.seven_seg_4digit
-# Loading work.seven_seg
-# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'.  Expected 8, found 1.
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'.
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61
-# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82
-add wave -position end  sim:/mips_tb/clk
-add wave -position end  sim:/mips_tb/CPU/instruction
-run
-# Beginning MIPS tests
-# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[8]  == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[9]  == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[10] == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[11] == 32'd14 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[12] == -32'sd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[14] == 32'd3 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[16] == 32'd2 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[17] == 32'd15 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[18] == 32'd13 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == -32'sd16 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[20] == 32'd1 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# All MIPS tests passing
-quit -sim
-# End time: 10:44:19 on Oct 16,2026, Elapsed time: 0:01:22
-# Errors: 0, Warnings: 13
-vsim work.mips_tb
-# vsim work.mips_tb 
-# Start time: 10:47:26 on Oct 16,2026
-# Loading sv_std.std
-# Loading work.mips_tb
-# Loading work.assignment2
-# Loading work.instruction_counter
-# Loading work.rom
-# Loading work.ram
-# Loading work.control_unit
-# Loading work.instruction_classifier
-# Loading work.register_file
-# Loading work.sign_extender
-# Loading work.alu
-# Loading work.asu
-# Loading work.lu
-# Loading work.seven_seg_4digit
-# Loading work.seven_seg
-# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'.  Expected 8, found 1.
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'.
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61
-# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82
-add wave -position end  sim:/mips_tb/clk
-force -freeze sim:/mips_tb/clk 1 0, 0 {10 ps} -r 20
-run
-# Beginning MIPS tests
-# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[8]  == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[9]  == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[10] == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[11] == 32'd14 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[12] == -32'sd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[14] == 32'd3 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[16] == 32'd2 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[17] == 32'd15 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[18] == 32'd13 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == -32'sd16 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[20] == 32'd1 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# All MIPS tests passing
+add wave -position end  sim:/mips_tb/rst
 add wave -position end  sim:/mips_tb/num_errors
+add wave -position end  sim:/mips_tb/CPU/regs_out
 run
-run
-quit -sim
-# End time: 10:49:38 on Oct 16,2026, Elapsed time: 0:02:12
-# Errors: 0, Warnings: 13
-vsim work.mips_tb
-# vsim work.mips_tb 
-# Start time: 10:49:39 on Oct 16,2026
-# Loading sv_std.std
-# Loading work.mips_tb
-# Loading work.assignment2
-# Loading work.instruction_counter
-# Loading work.rom
-# Loading work.ram
-# Loading work.control_unit
-# Loading work.instruction_classifier
-# Loading work.register_file
-# Loading work.sign_extender
-# Loading work.alu
-# Loading work.asu
-# Loading work.lu
-# Loading work.seven_seg_4digit
-# Loading work.seven_seg
-# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'.  Expected 8, found 1.
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'.
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61
-# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82
-add wave -position end  sim:/mips_tb/clk
-add wave -position end  sim:/mips_tb/num_errors
-add wave -position end  sim:/mips_tb/CPU/REGS/regs_out
-add wave -position end  sim:/mips_tb/CPU/REGS/regs
-force -freeze sim:/mips_tb/clk 1 0, 0 {5 ps} -r 10
-run
-# Beginning MIPS tests
-# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[8]  == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[9]  == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[10] == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[11] == 32'd14 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[12] == -32'sd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[14] == 32'd3 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[16] == 32'd2 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[17] == 32'd15 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[18] == 32'd13 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == -32'sd16 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[20] == 32'd1 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# All MIPS tests passing
-quit -sim
-# End time: 10:59:29 on Oct 16,2026, Elapsed time: 0:09:50
-# Errors: 0, Warnings: 13
-vsim work.ram
-# vsim work.ram 
-# Start time: 10:59:43 on Oct 16,2026
-# Loading sv_std.std
-# Loading work.ram
-quit -sim
-# End time: 10:59:51 on Oct 16,2026, Elapsed time: 0:00:08
-# Errors: 0, Warnings: 1
-vsim work.mips_tb
-# vsim work.mips_tb 
-# Start time: 10:59:55 on Oct 16,2026
-# Loading sv_std.std
-# Loading work.mips_tb
-# Loading work.assignment2
-# Loading work.instruction_counter
-# Loading work.rom
-# Loading work.ram
-# Loading work.control_unit
-# Loading work.instruction_classifier
-# Loading work.register_file
-# Loading work.sign_extender
-# Loading work.alu
-# Loading work.asu
-# Loading work.lu
-# Loading work.seven_seg_4digit
-# Loading work.seven_seg
-# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'.  Expected 8, found 1.
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'.
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56
-# ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61
-# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11).
-#    Time: 0 ps  Iteration: 0  Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82
-add wave -position end  sim:/mips_tb/CPU/instruction
-add wave -position end  sim:/mips_tb/clk
-add wave -position end  sim:/mips_tb/CPU/clk
-force -freeze sim:/mips_tb/clk 1 0, 0 {25 ps} -r 50
-force -freeze sim:/mips_tb/CPU/clk 1 0, 0 {25 ps} -r 50
-run
-# Beginning MIPS tests
-# Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[0] == 32'(N) failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[8]  == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[9]  == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[10] == 32'd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[11] == 32'd14 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[12] == -32'sd7 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[13] == 32'd10 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[14] == 32'd3 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[16] == 32'd2 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[17] == 32'd15 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[18] == 32'd13 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[19] == -32'sd16 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# Check CPU.REGS.regs[20] == 32'd1 failed
-# 
-# 	t0-t8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 	s0-s8: 	0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
-# 
-# All MIPS tests passing
-# End time: 11:31:43 on Oct 16,2026, Elapsed time: 0:31:48
-# Errors: 0, Warnings: 13
+# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18.    : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
+#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM
+# End time: 12:55:34 on Oct 16,2026, Elapsed time: 0:04:58
+# Errors: 0, Warnings: 6
diff --git a/ModelSim/vsim.wlf b/ModelSim/vsim.wlf
index d736fde..6e97881 100644
Binary files a/ModelSim/vsim.wlf and b/ModelSim/vsim.wlf differ
diff --git a/ModelSim/work/_info b/ModelSim/work/_info
index 48be210..7f05651 100644
--- a/ModelSim/work/_info
+++ b/ModelSim/work/_info
@@ -11,32 +11,32 @@ cModel Technology
 d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
 valu
 Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
-Z1 !s110 1792107153
+Z1 !s110 1792115142
 !i10b 1
-!s100 meV@F]8El[fjh_ULLA@iR2
+!s100 kh0:K2RRk@<XUA5?_0ad>1
 Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
-I<0ZXcWH[]FIo]cjVef19`2
+Im?EZg:mSI^D?=D>QBY^1B0
 Z3 VDg1SIo80bB@j0V0VzS_@n1
 S1
 Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
-w1792036226
+Z5 w1792113810
 8alu.sv
 Falu.sv
-!i122 90
-L0 9 31
-Z5 OV;L;2020.1;71
+!i122 179
+L0 10 33
+Z6 OV;L;2020.1;71
 r1
 !s85 0
 31
-Z6 !s108 1792107152.000000
-Z7 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
-Z8 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
+Z7 !s108 1792115141.000000
+Z8 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
+Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
 !i113 1
-Z9 o-work work -sv
-Z10 tCvgOpt 0
+Z10 o-work work -sv
+Z11 tCvgOpt 0
 valu_tb
 R0
-Z11 !s110 1792107152
+Z12 !s110 1792115141
 !i10b 1
 !s100 8=>8o`KV]hRM]V8AV?S[C1
 R2
@@ -44,46 +44,46 @@ Iz[VXe9HJ@koSDFNR185;i1
 R3
 S1
 R4
-Z12 w1789355084
+Z13 w1789355084
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
-!i122 79
+!i122 168
 L0 3 214
-R5
+R6
 r1
 !s85 0
 31
-R6
+R7
 !s107 lu.sv|asu.sv|alu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
 !i113 1
-R9
 R10
+R11
 vassignment2
 R0
 R1
 !i10b 1
-!s100 GJCIM_l8Wa[9;0<RIgA[E0
+!s100 9I6c?eD<Ld>]amhL__2Jz1
 R2
-I7i7cEGK6dmN[?gYSA`MeR3
+IFfHj7VAM^H^0]`kMd62bZ2
 R3
 S1
 R4
-w1792106709
+R5
 8assignment2.sv
 Fassignment2.sv
-!i122 90
+!i122 179
 L0 15 91
-R5
+R6
 r1
 !s85 0
 31
-R6
 R7
 R8
-!i113 1
 R9
+!i113 1
 R10
+R11
 vasu
 R0
 R1
@@ -97,21 +97,21 @@ R4
 w1790228118
 8asu.sv
 Fasu.sv
-!i122 90
+!i122 179
 L0 4 21
-R5
+R6
 r1
 !s85 0
 31
-R6
 R7
 R8
-!i113 1
 R9
+!i113 1
 R10
+R11
 vasu_tb
 R0
-R11
+R12
 !i10b 1
 !s100 ?AMT1ejDgW=83T_P=nh4G1
 R2
@@ -119,24 +119,24 @@ IcS>Hk9oO:RGFmfdUY9[i90
 R3
 S1
 R4
-Z13 w1789513270
+Z14 w1789513270
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
-!i122 82
+!i122 171
 L0 3 120
-R5
+R6
 r1
 !s85 0
 31
-R6
+R7
 !s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
 !i113 1
-R9
 R10
+R11
 vByteIM
 R0
-R11
+R12
 !i10b 1
 !s100 ]V5Di195@?V=P`Y?PM;U=0
 R2
@@ -144,47 +144,47 @@ Ie:hP;^zFCE^LSAOVoDF6C3
 R3
 S1
 R4
-w1792106811
+w1792112374
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
-!i122 83
+!i122 172
 L0 3 12
-R5
+R6
 r1
 !s85 0
 31
-R6
+R7
 !s107 rom.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
 !i113 1
-R9
 R10
+R11
 n@byte@i@m
 vcontrol_unit
 R0
 R1
 !i10b 1
-!s100 8=J_D2S47^DbodSznO_Zc3
+!s100 Un]HJ_Po@5PR5RoPMSiFc3
 R2
-ICLPRW`?<4jEk;O<a<:JfD1
+IN9L1dbI=^fl9KlmLIEFaZ0
 R3
 S1
 R4
-w1792040117
+Z15 w1792112234
 8control_unit.sv
 Fcontrol_unit.sv
-!i122 90
+!i122 179
 L0 5 31
-R5
+R6
 r1
 !s85 0
 31
-R6
 R7
 R8
-!i113 1
 R9
+!i113 1
 R10
+R11
 vinstruction_classifier
 R0
 R1
@@ -195,24 +195,24 @@ I[MC9A^:kRAc`nk8<MdaKg2
 R3
 S1
 R4
-Z14 w1790228042
+Z16 w1790228042
 8instruction_classifier.sv
 Finstruction_classifier.sv
-!i122 90
+!i122 179
 L0 3 18
-R5
+R6
 r1
 !s85 0
 31
-R6
 R7
 R8
-!i113 1
 R9
+!i113 1
 R10
+R11
 vinstruction_classifier_tb
 R0
-R11
+R12
 !i10b 1
 !s100 UcoUK1il@9RM[8`l`mYQh2
 R2
@@ -220,46 +220,46 @@ I;:>eJ6i8o;@kY_?aVJn:d3
 R3
 S1
 R4
-R12
+R13
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
-!i122 86
+!i122 175
 L0 2 51
-R5
+R6
 r1
 !s85 0
 31
-R6
+R7
 !s107 instruction_classifier.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv|
 !i113 1
-R9
 R10
+R11
 vinstruction_counter
 R0
 R1
 !i10b 1
-!s100 Gl3QY26LJ15Q7EONh4SzK3
+!s100 `Y=MBPBYNS6?lYoGX6gKQ3
 R2
-I1hlbD0fJDW[G]0]A8ceHA0
+In<Vi_TenOEn@V0998749H1
 R3
 S1
 R4
-w1791854498
+R5
 8instruction_counter.sv
 Finstruction_counter.sv
-!i122 90
-L0 4 17
-R5
+!i122 179
+L0 4 20
+R6
 r1
 !s85 0
 31
-R6
 R7
 R8
-!i113 1
 R9
+!i113 1
 R10
+R11
 vlu
 R0
 R1
@@ -270,24 +270,24 @@ IObN^<8?MCaP;K@UKCVaP^1
 R3
 S1
 R4
-R14
+R16
 8lu.sv
 Flu.sv
-!i122 90
-Z15 L0 3 16
-R5
+!i122 179
+Z17 L0 3 16
+R6
 r1
 !s85 0
 31
-R6
 R7
 R8
-!i113 1
 R9
+!i113 1
 R10
+R11
 vlu_tb
 R0
-R11
+R12
 !i10b 1
 !s100 AE_liX6DCD[3>b;K6Wgf72
 R2
@@ -298,118 +298,118 @@ R4
 w1788926090
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
-!i122 89
+!i122 178
 L0 3 58
-R5
+R6
 r1
 !s85 0
 31
-R6
+R7
 !s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
 !i113 1
-R9
 R10
+R11
 vmips_tb
 R0
 R1
 !i10b 1
-!s100 [;3LLg]jz>CL@TZ0g[C5g2
+!s100 kG?GBRChF[jJll1:hnGSE3
 R2
-ImO]Pc4zj;o69UAilj_VEd3
+IY51_GQHHW95C`9PL^lW1^1
 R3
 S1
 R4
-w1792104861
+R5
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
-!i122 90
-L0 14 82
-R5
+!i122 179
+L0 16 103
+R6
 r1
 !s85 0
 31
-R6
 R7
 R8
-!i113 1
 R9
+!i113 1
 R10
+R11
 vram
 R0
 R1
 !i10b 1
-!s100 a80AX>=1K`e^Xe^?2?j331
+!s100 KIM1Bhf3dZb;O;EN9OH^^3
 R2
-I9H<bBYRWPh>SjRizgnUC41
+IKXXONS>@k4@GP6o<Rk0zM0
 R3
 S1
 R4
-w1792039197
+R5
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
-!i122 91
-L0 4 26
-R5
+!i122 180
+L0 4 23
+R6
 r1
 !s85 0
 31
-Z16 !s108 1792107153.000000
+Z18 !s108 1792115142.000000
 !s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv|
 !i113 1
-R9
 R10
+R11
 vregister_file
 R0
 R1
 !i10b 1
-!s100 FhA1A;hJHXYBBj3k;<@TW0
+!s100 TM=bHR22b5BF7BGjf7QYh2
 R2
-I7[zSLUT47VibC4BZ`m8FC1
+IeQ`65;PU]l@K@hnj8YkL62
 R3
 S1
 R4
-w1792035553
+R15
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
-!i122 92
-L0 4 24
-R5
+!i122 181
+L0 4 25
+R6
 r1
 !s85 0
 31
-R16
+R18
 !s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv|
 !i113 1
-R9
 R10
+R11
 vrom
 R0
 R1
 !i10b 1
-!s100 WU3`[b3K8gX:gOXzLkih[1
+!s100 Vd76Vlo;I1?9UcSC7fcOP0
 R2
-INYZO14fR4zIzAHU<HO=jM1
+I:a:Y?o9P[59dd<zBhnkfn0
 R3
 S1
 R4
-w1792107144
+w1792114203
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
-!i122 93
+!i122 182
 L0 4 18
-R5
+R6
 r1
 !s85 0
 31
-R16
+R18
 !s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv|
 !i113 1
-R9
 R10
+R11
 vseven_seg
 R0
 R1
@@ -420,21 +420,21 @@ IedFU7?nB5ZOibY?bC8=L41
 R3
 S1
 R4
-R14
+R16
 8seven_seg.sv
 Fseven_seg.sv
-!i122 96
+!i122 185
 L0 3 23
-R5
+R6
 r1
 !s85 0
 31
-R16
-Z17 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
-Z18 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
+R18
+Z19 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
+Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
 !i113 1
-R9
 R10
+R11
 vseven_seg_4digit
 R0
 R1
@@ -448,18 +448,18 @@ R4
 w1791866874
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
-!i122 95
+!i122 184
 L0 5 37
-R5
+R6
 r1
 !s85 0
 31
-R16
+R18
 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv|
 !i113 1
-R9
 R10
+R11
 vseven_seg_tb
 R0
 R1
@@ -473,18 +473,18 @@ R4
 w1788418794
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
-!i122 96
+!i122 185
 L0 3 66
-R5
+R6
 r1
 !s85 0
 31
-R16
-R17
 R18
+R19
+R20
 !i113 1
-R9
 R10
+R11
 vshifter
 R0
 R1
@@ -495,21 +495,21 @@ IzJzhQo`olGLa0f4lM55A42
 R3
 S1
 R4
-R14
+R16
 8shifter.sv
 Fshifter.sv
-!i122 98
-R15
-R5
+!i122 187
+R17
+R6
 r1
 !s85 0
 31
-R16
-Z19 !s107 shifter.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
-Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
+R18
+Z21 !s107 shifter.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
+Z22 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
 !i113 1
-R9
 R10
+R11
 vshifter_tb
 R0
 R1
@@ -520,43 +520,43 @@ Ia6ohf92lD=P<P]lDi667i2
 R3
 S1
 R4
-R13
+R14
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
-!i122 98
+!i122 187
 L0 2 76
-R5
+R6
 r1
 !s85 0
 31
-R16
-R19
-R20
+R18
+R21
+R22
 !i113 1
-R9
 R10
+R11
 vsign_extender
 R0
 R1
 !i10b 1
-!s100 aKV[]M4PV<7m9ohWC7JSA0
+!s100 VOYzaEd320YMo:nYU=@hG2
 R2
-I6?e[:9@XB<KdO1NP<2VSz0
+Ic?f[J?J3HD0]DeV]c1EoN3
 R3
 S1
 R4
-w1792038654
+R15
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
-!i122 99
-L0 4 13
-R5
+!i122 188
+L0 4 15
+R6
 r1
 !s85 0
 31
-R16
+R18
 !s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv|
 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv|
 !i113 1
-R9
 R10
+R11
diff --git a/ModelSim/work/_lib.qdb b/ModelSim/work/_lib.qdb
index 346a15c..87aa818 100644
Binary files a/ModelSim/work/_lib.qdb and b/ModelSim/work/_lib.qdb differ
diff --git a/ModelSim/work/_lib1_12.qtl b/ModelSim/work/_lib1_12.qtl
deleted file mode 100644
index b36e387..0000000
Binary files a/ModelSim/work/_lib1_12.qtl and /dev/null differ
diff --git a/ModelSim/work/_lib1_12.qdb b/ModelSim/work/_lib1_24.qdb
similarity index 83%
rename from ModelSim/work/_lib1_12.qdb
rename to ModelSim/work/_lib1_24.qdb
index 92e1bbc..4718d45 100644
Binary files a/ModelSim/work/_lib1_12.qdb and b/ModelSim/work/_lib1_24.qdb differ
diff --git a/ModelSim/work/_lib1_12.qpg b/ModelSim/work/_lib1_24.qpg
similarity index 50%
rename from ModelSim/work/_lib1_12.qpg
rename to ModelSim/work/_lib1_24.qpg
index f5f7399..cca64b6 100644
Binary files a/ModelSim/work/_lib1_12.qpg and b/ModelSim/work/_lib1_24.qpg differ
diff --git a/ModelSim/work/_lib1_24.qtl b/ModelSim/work/_lib1_24.qtl
new file mode 100644
index 0000000..25ba9c6
Binary files /dev/null and b/ModelSim/work/_lib1_24.qtl differ