TroubleElectrical/FPGA_Uni
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Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)

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TroubleElectrical committed 2026-10-16 12:59:50 +11:00
1 parent 2f652705cc
commit 91a5090528
21 files changed
+389 -1323
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ModelSim/control_unit.sv
+6 -6
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@@ -23,13 +23,13 @@ module control_unit (
instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
always_comb begin
M2R = TYPE_M & op[3];
M2W = TYPE_M & ~op[3];
M2R = TYPE_M & ~((op & 6'b001000) >> 3);
M2W = TYPE_M & ((op & 6'b001000) >> 3);
B = TYPE_B1 | TYPE_B2 | TYPE_J;
ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
RDST = TYPE_I; // Imm ops store back into rt
RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
ALU_FN = (func & {(4){TYPE_R}}) | ( {2'b00, (op & 6'b000011)} & {(4){TYPE_I}}) | (4'b0010 & {4{TYPE_B1 | TYPE_B2}});
ALU_SRC = TYPE_I | TYPE_M;
RDST = TYPE_R; // Imm ops store back into rt
RW = TYPE_R | TYPE_I | M2R;
end
endmodule