TroubleElectrical/FPGA_Uni
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Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)

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TroubleElectrical committed 2026-10-16 12:59:50 +11:00
1 parent 2f652705cc
commit 91a5090528
21 files changed
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ModelSim/alu.sv
+17 -12
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@@ -6,6 +6,7 @@
// flags[0:0] = Cout
// flags[1:1] = Overflow
// flags[2:2] = Zero
module alu #(parameter width=2)(input logic [3:0] op,
input logic [2**width-1:0] A, input logic [2**width-1:0] B,
output logic [2**width-1:0] OUT_1, output logic[2:0] flags
@@ -15,26 +16,30 @@ module alu #(parameter width=2)(input logic [3:0] op,
logic [2**width-1:0] asu_out;
logic [2:0] asu_flags;
asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
assign asu_op = op[1];
logic [0:0] asu_cout_flag;
asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_cout_flag);
logic [2**width-1:0] lu_out;
lu #(width) logic_unit(op[1:0], A, B, lu_out);
assign asu_flags[1] = asu_cout_flag ^ asu_flags[0];
always_comb begin
case (op)
4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
4'b0110: begin OUT_1 = lu_out; flags = asu_flags; end
4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
4'b0000: begin OUT_1 = asu_out; end
4'b0001: begin OUT_1 = asu_out; end
4'b0010: begin OUT_1 = asu_out; end
4'b0011: begin OUT_1 = asu_out; end
4'b0100: begin OUT_1 = lu_out; end
4'b0101: begin OUT_1 = lu_out; end
4'b0110: begin OUT_1 = lu_out; end
4'b0111: begin OUT_1 = lu_out; end
4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; end
4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; end
default: begin OUT_1 = {(2**width){1'b0}}; end
endcase
asu_flags[2] = OUT_1 == 0;
flags = asu_flags;
end
endmodule
`endif