TroubleElectrical/FPGA_Uni
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Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)

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TroubleElectrical committed 2026-10-16 12:59:50 +11:00
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commit 91a5090528
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ModelSim/Assignment_2.cr.mti
+6 -12
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@@ -41,7 +41,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
control_unit
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module rom
-- Compiling module ram
@@ -52,9 +52,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
-- Compiling module asu
-- Compiling module lu
-- Compiling module alu
** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(1)
** while parsing file included at assignment2.sv(9)
** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
-- Compiling module shifter
-- Compiling module sign_extender
-- Compiling module seven_seg
@@ -64,6 +61,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
shifter
seven_seg_4digit
mips_tb
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
@@ -88,7 +86,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
shifter_tb
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module rom
-- Compiling module ram
@@ -99,8 +97,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
-- Compiling module asu
-- Compiling module lu
-- Compiling module alu
** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv(9)
** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
-- Compiling module shifter
-- Compiling module sign_extender
-- Compiling module seven_seg
@@ -109,6 +105,7 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
shifter
seven_seg_4digit
assignment2
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
@@ -142,13 +139,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
sign_extender
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module asu
-- Compiling module lu
-- Compiling module alu
** Warning: ** while parsing file included at /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv(1)
** at alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
-- Compiling module alu_tb
Top level modules:
@@ -161,12 +156,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
instruction_counter
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {2 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module asu
-- Compiling module lu
-- Compiling module alu
** Warning: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv(25): (vlog-2182) 'asu_flags[2]' might be read before written in always_comb or always @* block.
Top level modules:
alu