From 8c6765eb83ac1e44833ecc6d01ce08172fe52fd2 Mon Sep 17 00:00:00 2001 From: TroubleElectrical Date: Thu, 15 Oct 2026 14:49:32 +1100 Subject: [PATCH] Updated reg file and assignment for compilation --- Quartus/A2/assignment2.qws | Bin 1391 -> 0 bytes Quartus/A2/db/assignment2.(0).cnf.cdb | Bin 5602 -> 0 bytes Quartus/A2/db/assignment2.(0).cnf.hdb | Bin 3127 -> 0 bytes Quartus/A2/db/assignment2.(16).cnf.cdb | Bin 3834 -> 0 bytes Quartus/A2/db/assignment2.(16).cnf.hdb | Bin 1673 -> 0 bytes Quartus/A2/db/assignment2.(25).cnf.cdb | Bin 3834 -> 0 bytes Quartus/A2/db/assignment2.(25).cnf.hdb | Bin 1650 -> 0 bytes Quartus/A2/db/assignment2.(31).cnf.cdb | Bin 3831 -> 0 bytes Quartus/A2/db/assignment2.(31).cnf.hdb | Bin 1669 -> 0 bytes Quartus/A2/db/assignment2.(42).cnf.cdb | Bin 3832 -> 0 bytes Quartus/A2/db/assignment2.(42).cnf.hdb | Bin 1658 -> 0 bytes Quartus/A2/db/assignment2.(43).cnf.cdb | Bin 3831 -> 0 bytes Quartus/A2/db/assignment2.(43).cnf.hdb | Bin 1682 -> 0 bytes Quartus/A2/db/assignment2.(53).cnf.cdb | Bin 3832 -> 0 bytes Quartus/A2/db/assignment2.(53).cnf.hdb | Bin 1668 -> 0 bytes Quartus/A2/db/assignment2.(64).cnf.cdb | Bin 3832 -> 0 bytes Quartus/A2/db/assignment2.(64).cnf.hdb | Bin 1655 -> 0 bytes Quartus/A2/db/assignment2.(7).cnf.cdb | Bin 3833 -> 0 bytes Quartus/A2/db/assignment2.(7).cnf.hdb | Bin 1665 -> 0 bytes Quartus/A2/db/assignment2.cmp.rdb | Bin 4399 -> 4398 bytes Quartus/A2/db/assignment2.db_info | 2 +- Quartus/A2/db/assignment2.hif | Bin 2048 -> 1610 bytes Quartus/A2/db/assignment2.map.qmsg | 28 +++-------- Quartus/A2/db/assignment2.map.rdb | Bin 1152 -> 1145 bytes Quartus/A2/db/assignment2.map_bb.hdb | Bin 12696 -> 11583 bytes .../A2/db/assignment2.quiproj.4395.rdr.flock | 0 Quartus/A2/db/prev_cmp_assignment2.qmsg | 17 +++++-- Quartus/A2/output_files/assignment2.flow.rpt | 12 ++--- Quartus/A2/output_files/assignment2.map.rpt | 46 ++++-------------- .../A2/output_files/assignment2.map.summary | 2 +- modules/assignment2.sv | 8 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"Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792033111354 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 15 13:58:31 2026 " "Processing started: Thu Oct 15 13:58:31 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792033111354 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792033111354 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792033111354 ""} -{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792033111740 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792033120668 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792033120668 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792033120814 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(58) " "Verilog HDL or VHDL warning at assignment2.sv(58): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 58 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1792033120815 "|assignment2"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792033120860 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792033120867 ""} -{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1792033120875 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792033120907 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792033120907 "|assignment2|rom:ROM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792033120907 "|assignment2|rom:ROM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792033120911 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 72 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792033120914 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792033120916 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_extender sign_extender:SIGNEXT " "Elaborating entity \"sign_extender\" for hierarchy \"sign_extender:SIGNEXT\"" { } { { "../../modules/assignment2.sv" "SIGNEXT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792033120924 ""} -{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT" "sign_extender.sv(10) " "Verilog HDL unsupported feature error at sign_extender.sv(10): Procedural Continuous Assignment to register is not supported" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 10 0 0 } } } 0 10043 "Verilog HDL unsupported feature error at %1!s!: Procedural Continuous Assignment to register is not supported" 0 0 "Analysis & Synthesis" 0 -1 1792033120924 ""} -{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "sign_extender:SIGNEXT " "Can't elaborate user hierarchy \"sign_extender:SIGNEXT\"" { } { { "../../modules/assignment2.sv" "SIGNEXT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 81 0 0 } } } 0 12152 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792033120925 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 5 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 5 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792033120976 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 15 13:58:40 2026 " "Processing ended: Thu Oct 15 13:58:40 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792033120976 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792033120976 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792033120976 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792033120976 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792035855968 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792035855968 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 15 14:44:15 2026 " "Processing started: Thu Oct 15 14:44:15 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792035855968 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035855968 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035855968 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792035856269 ""} +{ "Error" "EVRFX_VERI_MIXED_BY_NAME_BY_ORDER_PORT_CONNECT" "assignment2.sv(80) " "Verilog HDL Module Instantiation error at assignment2.sv(80): cannot connect instance ports both by order and by name" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } } } 0 10267 "Verilog HDL Module Instantiation error at %1!s!: cannot connect instance ports both by order and by name" 0 0 "Analysis & Synthesis" 0 -1 1792035865333 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(16) " "Ignored design unit \"assignment2\" at assignment2.sv(16) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1792035865334 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035865334 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792035865378 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 15 14:44:25 2026 " "Processing ended: Thu Oct 15 14:44:25 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792035865378 ""} { "Error" "EQEXE_ELAPSED_TIME" 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a/Quartus/A2/db/prev_cmp_assignment2.qmsg +++ b/Quartus/A2/db/prev_cmp_assignment2.qmsg @@ -1,5 +1,12 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791870416152 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791870416153 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 16:46:55 2026 " "Processing started: Tue Oct 13 16:46:55 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791870416153 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791870416153 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791870416153 ""} -{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1791870416494 ""} -{ "Warning" "WQCU_PARALLEL_TOO_MANY_PROCESSORS" "4 2 " "Parallel compilation is enabled for 4 processors, but there are only 2 processors in the system. Runtime may increase due to over usage of the processor space." { } { } 0 20031 "Parallel compilation is enabled for %1!i! processors, but there are only %2!i! processors in the system. Runtime may increase due to over usage of the processor space." 0 0 "Analysis & Synthesis" 0 -1 1791870416494 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792035814963 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792035814963 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 15 14:43:34 2026 " "Processing started: Thu Oct 15 14:43:34 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792035814963 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035814963 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035814964 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792035815265 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035824809 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792035824965 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(58) " "Verilog HDL or VHDL warning at assignment2.sv(58): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 58 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1792035824966 "|assignment2"} +{ "Error" "EVRFX_SV_TYPES_CANT_BE_ASSIGNED" "packed array unpacked array types do not match assignment2.sv(80) " "SystemVerilog error at assignment2.sv(80): packed array type cannot be assigned to unpacked array type - types do not match" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } } } 0 10928 "SystemVerilog error at %4!s!: %1!s! type cannot be assigned to %2!s! type - %3!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035824969 ""} +{ "Error" "EVRFX_SV_1071_UNCONVERTED" "RD2 assignment2.sv(80) " "SystemVerilog error at assignment2.sv(80): can't pass value from formal output RD2 to actual with incompatible type" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } } } 0 10715 "SystemVerilog error at %2!s!: can't pass value from formal output %1!s! to actual with incompatible type" 0 0 "Analysis & Synthesis" 0 -1 1792035824969 ""} +{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" { } { } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792035824970 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792035825024 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 15 14:43:45 2026 " "Processing ended: Thu Oct 15 14:43:45 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792035825024 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792035825024 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792035825024 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035825024 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 1 " "Quartus Prime Full Compilation was unsuccessful. 5 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035825689 ""} diff --git a/Quartus/A2/output_files/assignment2.flow.rpt b/Quartus/A2/output_files/assignment2.flow.rpt index 3904043..44aa1aa 100644 --- a/Quartus/A2/output_files/assignment2.flow.rpt +++ b/Quartus/A2/output_files/assignment2.flow.rpt @@ -1,5 +1,5 @@ Flow report for assignment2 -Thu Oct 15 13:58:40 2026 +Thu Oct 15 14:44:25 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,7 +41,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------------------+ ; Flow Summary ; +-----------------------------+-------------------------------------------------+ -; Flow Status ; Flow Failed - Thu Oct 15 13:58:40 2026 ; +; Flow Status ; Flow Failed - Thu Oct 15 14:44:25 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; @@ -63,7 +63,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 10/15/2026 13:58:31 ; +; Start date & time ; 10/15/2026 14:44:16 ; ; Main task ; Compilation ; ; Revision Name ; assignment2 ; +-------------------+---------------------+ @@ -74,7 +74,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 268883478169649.179203311102359 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 268883478169649.179203585604765 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -98,8 +98,8 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 403 MB ; 00:00:23 ; -; Total ; 00:00:09 ; -- ; -- ; 00:00:23 ; +; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 400 MB ; 00:00:23 ; +; Total ; 00:00:10 ; -- ; -- ; 00:00:23 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A2/output_files/assignment2.map.rpt b/Quartus/A2/output_files/assignment2.map.rpt index 8f4daf0..f8d839c 100644 --- a/Quartus/A2/output_files/assignment2.map.rpt +++ b/Quartus/A2/output_files/assignment2.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for assignment2 -Thu Oct 15 13:58:40 2026 +Thu Oct 15 14:44:25 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Failed - Thu Oct 15 13:58:40 2026 ; +; Analysis & Synthesis Status ; Failed - Thu Oct 15 14:44:25 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; @@ -162,42 +162,16 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Oct 15 13:58:31 2026 + Info: Processing started: Thu Oct 15 14:44:15 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 Info (20032): Parallel compilation is enabled and will use up to 2 processors -Info (12021): Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv - Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4 - Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4 - Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4 - Info (12023): Found entity 4: instruction_counter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv Line: 4 - Info (12023): Found entity 5: instruction_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv Line: 3 - Info (12023): Found entity 6: instruction_module_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv Line: 4 - Info (12023): Found entity 7: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4 - Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3 - Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9 - Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3 - Info (12023): Found entity 11: sign_extender File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 4 - Info (12023): Found entity 12: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv Line: 3 - Info (12023): Found entity 13: seven_seg_4digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 5 - Info (12023): Found entity 14: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16 -Info (12127): Elaborating entity "assignment2" for the top level hierarchy -Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(58): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 58 -Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 61 -Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 63 -Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16 -Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 -Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 -Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 -Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 65 -Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 72 -Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 78 -Info (12128): Elaborating entity "sign_extender" for hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 81 -Error (10043): Verilog HDL unsupported feature error at sign_extender.sv(10): Procedural Continuous Assignment to register is not supported File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 10 -Error (12152): Can't elaborate user hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 81 -Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 5 warnings - Error: Peak virtual memory: 403 megabytes - Error: Processing ended: Thu Oct 15 13:58:40 2026 - Error: Elapsed time: 00:00:09 +Error (10267): Verilog HDL Module Instantiation error at assignment2.sv(80): cannot connect instance ports both by order and by name File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 80 +Error (10112): Ignored design unit "assignment2" at assignment2.sv(16) due to previous errors File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16 +Info (12021): Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv +Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings + Error: Peak virtual memory: 400 megabytes + Error: Processing ended: Thu Oct 15 14:44:25 2026 + Error: Elapsed time: 00:00:10 Error: Total CPU time (on all processors): 00:00:23 diff --git a/Quartus/A2/output_files/assignment2.map.summary b/Quartus/A2/output_files/assignment2.map.summary index d05b648..299f647 100644 --- a/Quartus/A2/output_files/assignment2.map.summary +++ b/Quartus/A2/output_files/assignment2.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Failed - Thu Oct 15 13:58:40 2026 +Analysis & Synthesis Status : Failed - Thu Oct 15 14:44:25 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : assignment2 Top-level Entity Name : assignment2 diff --git a/modules/assignment2.sv b/modules/assignment2.sv index 2cdff95..3f3e869 100644 --- a/modules/assignment2.sv +++ b/modules/assignment2.sv @@ -57,6 +57,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( logic [2**width-1:0] rt; logic [2**width-1:0] rd; logic [0:0] rd_we; + logic [31:0] regs_out [32]; instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr); @@ -71,11 +72,10 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( en_alu ); - register_file #(width, 5) REGS (clk, + register_file #(width, 5) REGS (clk rd_we, instruction[15:11], rs, instruction[25:21], - rt, instruction[20:16], - regs_out + rt, instruction[20:16] ); // Always use sign-extension logic [2**width-1:0] rt_imm; @@ -101,7 +101,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( // Temporary Test output assign PC_Reg_Display = 16'hC342; - assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0]; + assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0]; seven_seg_4digit display ( .num(PC_Reg_Display), diff --git a/modules/register_file.sv b/modules/register_file.sv index 8b386f2..f159ccd 100644 --- a/modules/register_file.sv +++ b/modules/register_file.sv @@ -5,7 +5,7 @@ module register_file #(parameter width=5, parameter nregs=5)( input logic [0:0] clk, input logic[0:0] we, input logic [nregs-1:0] WA, input logic [2**width-1:0] WD, input logic [nregs-1:0] RA1, output logic [2**width-1:0] RD1, - input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2 + input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2, output logic [2**width-1:0] regs_out [2**nregs] ); localparam BW = 2**width;