TroubleElectrical/FPGA_Uni
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Updated reg file and assignment for compilation

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TroubleElectrical committed 2026-10-15 14:49:32 +11:00
1 parent ac1062fbd5
commit 8c6765eb83
32 files changed
+43 -74
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Quartus/A2/output_files/assignment2.flow.rpt
+6 -6
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@@ -1,5 +1,5 @@
Flow report for assignment2
Thu Oct 15 13:58:40 2026
Thu Oct 15 14:44:25 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------------+-------------------------------------------------+
; Flow Status ; Flow Failed - Thu Oct 15 13:58:40 2026 ;
; Flow Status ; Flow Failed - Thu Oct 15 14:44:25 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
@@ -63,7 +63,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/15/2026 13:58:31 ;
; Start date & time ; 10/15/2026 14:44:16 ;
; Main task ; Compilation ;
; Revision Name ; assignment2 ;
+-------------------+---------------------+
@@ -74,7 +74,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 268883478169649.179203311102359 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 268883478169649.179203585604765 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -98,8 +98,8 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 403 MB ; 00:00:23 ;
; Total ; 00:00:09 ; -- ; -- ; 00:00:23 ;
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 400 MB ; 00:00:23 ;
; Total ; 00:00:10 ; -- ; -- ; 00:00:23 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+