Repaired Sign extender module again to ensure only combinational logic used

(There was a compilation error before, also compiled and tested code on board)

Quartus/A2/output_files/assignment2.map.summary

@@ -1,10 +1,10 @@
-Analysis & Synthesis Status : Successful - Fri Oct 16 14:21:03 2026
+Analysis & Synthesis Status : Successful - Thu Oct 22 15:42:41 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : assignment2
 Top-level Entity Name : assignment2
 Family : Cyclone V
 Logic utilization (in ALMs) : N/A
-Total registers : 2302
+Total registers : 9182
 Total pins : 41
 Total virtual pins : 0
 Total block memory bits : 0