Repaired Sign extender module again to ensure only combinational logic used

(There was a compilation error before, also compiled and tested code on board)

Quartus/A2/output_files/assignment2.fit.summary

@@ -1,12 +1,12 @@
-Fitter Status : Successful - Fri Oct 16 14:22:59 2026
+Fitter Status : Successful - Thu Oct 22 15:47:44 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : assignment2
 Top-level Entity Name : assignment2
 Family : Cyclone V
 Device : 5CGXFC5C6F27C7
 Timing Models : Final
-Logic utilization (in ALMs) : 1,735 / 29,080 ( 6 % )
-Total registers : 2524
+Logic utilization (in ALMs) : 5,271 / 29,080 ( 18 % )
+Total registers : 9403
 Total pins : 41 / 364 ( 11 % )
 Total virtual pins : 0
 Total block memory bits : 0 / 4,567,040 ( 0 % )